Ignore:
Timestamp:
12/13/00 18:09:48 (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
0289674
Parents:
0ef748fb
Message:

2000-12-13 Joel Sherrill <joel@…>

  • cpu_asm.h: Removed.
  • Makefile.am: Remove cpu_asm.h.
  • rtems/score/mips64orion.h: Renamed mips.h.
  • rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros.
  • rtems/score/Makefile.am: Reflect renaming mips64orion.h.
  • asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>.
  • cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C.
  • cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas.
  • idtcpu.h: Made ifdef report an error.
  • iregdef.h: Removed warning.
  • rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
File:
1 edited

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  • c/src/exec/score/cpu/mips/ChangeLog

    r0ef748fb r32f415d  
     12000-12-13      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.h: Removed.
     4        * Makefile.am: Remove cpu_asm.h.
     5        * rtems/score/mips64orion.h: Renamed mips.h.
     6        * rtems/score/mips.h: New file, formerly mips64orion.h.
     7        Header rewritten.
     8        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
     9        mips_disable_in_interrupt_mask): New macros.
     10        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
     11        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
     12        few defines that were in <cpu_asm.h>.
     13        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
     14        MIPS ISA 3 is still in assembly for now.
     15        (_CPU_Thread_Idle_body): Rewrote in C.
     16        * cpu_asm.S: Rewrote file header.
     17        (FRAME,ENDFRAME) now in asm.h.
     18        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
     19        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
     20        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
     21        leaves other bits in SR alone on task switch.
     22        (mips_enable_interrupts,mips_disable_interrupts,
     23        mips_enable_global_interrupts,mips_disable_global_interrupts,
     24        disable_int, enable_int): Removed.
     25        (mips_get_sr): Rewritten as C macro.
     26        (_CPU_Thread_Idle_body): Rewritten in C.
     27        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
     28        placed in libcpu.
     29        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
     30        to libcpu/mips/shared/interrupts.
     31        (general): Cleaned up comment blocks and #if 0 areas.
     32        * idtcpu.h: Made ifdef report an error.
     33        * iregdef.h: Removed warning.
     34        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
     35        number defined by libcpu.
     36        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
     37        to access SR.
     38        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
     39        (_CPU_Context_Initialize): Honor ISR level in task initialization.
     40        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
     41
    1422000-12-06      Joel Sherrill <joel@OARcorp.com>
    243
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