Changeset 32b4a0c in rtems


Ignore:
Timestamp:
06/09/17 05:25:02 (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
f7d0f5e
Parents:
a66accc5
git-author:
Sebastian Huber <sebastian.huber@…> (06/09/17 05:25:02)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/09/17 05:30:41)
Message:

Simplify TLS support in context switch

There is no need to save the thread pointer in _CPU_Context_switch()
since it is a thread invariant. It is initialized once in
_CPU_Context_Initialize().

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/irq_asm.S

    ra66accc5 r32b4a0c  
    6060SYM(_CPU_Context_switch):
    6161        st      %g5, [%o0 + G5_OFFSET]       ! save the global registers
    62         st      %g7, [%o0 + G7_OFFSET]
     62
     63        /*
     64         * No need to save the thread pointer %g7 since it is a thread
     65         * invariant.  It is initialized once in _CPU_Context_Initialize().
     66         */
    6367
    6468        std     %l0, [%o0 + L0_OFFSET]       ! save the local registers
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S

    ra66accc5 r32b4a0c  
    337337        PPC_GPR_STORE   r31, PPC_CONTEXT_OFFSET_GPR31(r3)
    338338
    339         stw     r2, PPC_CONTEXT_OFFSET_GPR2(r3)
    340339        stw     r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r3)
    341340
  • cpukit/score/cpu/arm/cpu_asm.S

    ra66accc5 r32b4a0c  
    5757/* Start saving context */
    5858        GET_SELF_CPU_CONTROL    r2
     59        ldr     r3, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
    5960        stm     r0, {r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    60 
    61 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
    62         mrc     p15, 0, r3, c13, c0, 3
    63 #endif
    64 
    65         ldr     r4, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
    6661
    6762#ifdef ARM_MULTILIB_VFP
     
    7065#endif
    7166
    72 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
    73         str     r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
    74 #endif
    75 
    76         str     r4, [r0, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE]
     67        str     r3, [r0, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE]
    7768
    7869#ifdef RTEMS_SMP
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