Changeset 322c894 in rtems


Ignore:
Timestamp:
05/31/00 15:27:40 (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
e89694e
Parents:
3081446
Message:

Patch to:

  1. Fixes a typo in the code conditionalized by GEN68360_WITH_SRAM
  2. Mods the code to add support for an additional bank of SRAM (needed more RAM to run the web server!)

From <vac4050@…> reviewed by Eric Norum <eric@…>.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libbsp/m68k/gen68360/startup/init68360.c

    r3081446 r322c894  
    348348    *  CS0* - 512kx8 flash memory                     *
    349349    *  CS1* - 512kx32 static RAM                      *
     350    *  CS2* - 512kx32 static RAM                      *
    350351    ***************************************************
    351352    */
    … …  
    419420    * Step 12: Set up main memory
    420421    * 512Kx32 SRAM on CS1*
     422    * 512Kx32 SRAM on CS2*
    421423    * 0 wait states
    422424    */
    423    ramSize = 1 * 1024 * 1024;
     425   ramSize = 4 * 1024 * 1024;
    424426   m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
    425427   m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
     428                                                   M360_MEMC_OR_32BIT;
     429   m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V;
     430   m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
    426431                                                   M360_MEMC_OR_32BIT;
    427432   /*
    … …  
    464469    */
    465470   m360.mcr = 0x4C7F;
    466          *      No show cycles
    467          *      User/supervisor access
    468          *      Bus clear interrupt service level 7
    469          *      SIM60 interrupt sources higher priority than CPM
    470          */
    471         m360.mcr = 0x4C7F;
    472471
    473472#else
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