Ignore:
Timestamp:
May 5, 2009, 4:18:06 PM (11 years ago)
Author:
Jennifer Averett <Jennifer.Averett@…>
Branches:
4.9
Children:
8e230e6
Parents:
56e12a17
Message:

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
  • irq/no_pic.c: New file.
  • irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
File:
1 edited

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  • c/src/lib/libbsp/powerpc/score603e/irq/irq.h

    r56e12a17 r31a5ec8  
    44 *  by RTEMS to write interrupt handlers.
    55 *
    6  *  Copyright (C) 1999 valette@crf.canon.fr
    7  *
    86 *  This code is heavilly inspired by the public specification of STREAM V2
    97 *  that can be found at :
    108 *
    11  *      <http://www.chorus.com/Documentation/index.html> by following
     9 *  <http://www.chorus.com/Documentation/index.html> by following
    1210 *  the STREAM API Specification Document link.
    1311 *
     12 *  COPYRIGHT (c) 1989-2009.
     13 *  On-Line Applications Research Corporation (OAR).
     14 *
    1415 *  The license and distribution terms for this file may be
    15  *  found in found in the file LICENSE in this distribution or at
     16 *  found in the file LICENSE in this distribution or at
    1617 *  http://www.rtems.com/license/LICENSE.
    1718 *
     
    2526#include <rtems/irq.h>
    2627
    27 /*
    28  * 8259 edge/level control definitions at VIA
    29  */
    30 #define ISA8259_M_ELCR          0x4d0
    31 #define ISA8259_S_ELCR          0x4d1
    32 
    33 #define ELCRS_INT15_LVL         0x80
    34 #define ELCRS_INT14_LVL         0x40
    35 #define ELCRS_INT13_LVL         0x20
    36 #define ELCRS_INT12_LVL         0x10
    37 #define ELCRS_INT11_LVL         0x08
    38 #define ELCRS_INT10_LVL         0x04
    39 #define ELCRS_INT9_LVL          0x02
    40 #define ELCRS_INT8_LVL          0x01
    41 #define ELCRM_INT7_LVL          0x80
    42 #define ELCRM_INT6_LVL          0x40
    43 #define ELCRM_INT5_LVL          0x20
    44 #define ELCRM_INT4_LVL          0x10
    45 #define ELCRM_INT3_LVL          0x8
    46 #define ELCRM_INT2_LVL          0x4
    47 #define ELCRM_INT1_LVL          0x2
    48 #define ELCRM_INT0_LVL          0x1
    49 
    50     /* PIC's command and mask registers */
    51 #define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
    52 #define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
    53 #define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
    54 #define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
    55 
    56     /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    57 #define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
    58 #define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    59 #define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    60 
    6128#ifndef ASM
    6229
     
    6431extern "C" {
    6532#endif
     33
    6634
    6735/*
     
    7543#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
    7644#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
     45
    7746/*
    7847 * PCI IRQ handlers related definitions
    79  * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
    8048 */
    8149#define BSP_PCI_IRQ_NUMBER              (16)
    8250#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
    8351#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
     52
     53/*
     54 * PMC IRQ
     55 */
     56#define BSP_PMC_IRQ_NUMBER              (4)
     57#define BSP_PMC_IRQ_LOWEST_OFFSET       (BSP_PCI_IRQ_MAX_OFFSET + 1)
     58#define BSP_PMC_IRQ_MAX_OFFSET          (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
     59
     60
    8461/*
    8562 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
     
    8764 */
    8865#define BSP_PROCESSOR_IRQ_NUMBER        (1)
    89 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
     66#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
    9067#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
     68
    9169/* Misc vectors for OPENPIC irqs (IPI, timers)
    9270 */
     
    10078#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
    10179#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    102 /*
    103  * Some ISA IRQ symbolic name definition
    104  */
    105 #define BSP_ISA_PERIODIC_TIMER          (0)
    106 #define BSP_ISA_KEYBOARD                (1)
    107 #define BSP_ISA_UART_COM2_IRQ           (3)
    108 #define BSP_ISA_UART_COM1_IRQ           (4)
    109 #define BSP_ISA_RT_TIMER1               (8)
    110 #define BSP_ISA_RT_TIMER3               (10)
    111 /*
    112  * Some PCI IRQ symbolic name definition
    113  */
    114 #define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
    115 #define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
    116 
    117 #if defined(mvme2100)
    118 #define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
    119 #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
    120 #define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
    121 #define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
    122 #define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
    123 #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
    124 #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
    125 #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
    126 #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
    127 #define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
    128 #define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
    129 #define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
    130 #else
    131 #define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
    132 #define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
    133 #endif
    13480
    13581/*
     
    13884#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    13985
     86/*
     87 * First Score Unique IRQ
     88 */
     89#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
    14090
    14191/*
    142  * Type definition for RTEMS managed interrupts
     92 * The Following Are part of a Score603e FPGA.
    14393 */
    144 typedef unsigned short rtems_i8259_masks;
     94#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
     95#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
     96#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
     97#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
     98#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
     99#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
     100#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
     101#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
     102#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
     103#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
     104#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
     105#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
     106#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
     107#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
     108#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
     109#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
    145110
    146 extern  volatile rtems_i8259_masks i8259s_cache;
    147 
    148 /*-------------------------------------------------------------------------+
    149 | Function Prototypes.
    150 +--------------------------------------------------------------------------*/
    151 /*
    152  * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
    153  */
    154 void BSP_i8259s_init(void);
     111#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
     112#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
     113#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
     114#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
     115#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
     116#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
     117#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
     118#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
     119#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
     120#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
     121#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
     122#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
     123#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
     124#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
     125#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
     126#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
    155127
    156128/*
    157  * function to disable a particular irq at 8259 level. After calling
    158  * this function, even if the device asserts the interrupt line it will
    159  * not be propagated further to the processor
    160  *
    161  * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
    162  *          a value < 0 on error.
     129 * The Score FPGA maps all interrupts comming from the PMC card to
     130 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
     131 * read to indicate which interrupt was chained to the FPGA.
    163132 */
    164 int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
     133#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
     134#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
     135#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
     136#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
     137
    165138/*
    166  * function to enable a particular irq at 8259 level. After calling
    167  * this function, if the device asserts the interrupt line it will
    168  * be propagated further to the processor
     139 * IRQ'a read from the PMC card
    169140 */
    170 int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
    171 /*
    172  * function to acknowledge a particular irq at 8259 level. After calling
    173  * this function, if a device asserts an enabled interrupt line it will
    174  * be propagated further to the processor. Mainly usefull for people
    175  * writing raw handlers as this is automagically done for RTEMS managed
    176  * handlers.
    177  */
    178 int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
    179 /*
    180  * function to check if a particular irq is enabled at 8259 level. After calling
    181  */
    182 int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
     141#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
     142#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
     143#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
     144#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
    183145
    184 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
    185 extern void BSP_i8259s_init(void);
    186 
    187 /* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
    188 /* #include <bsp/irq_supp.h> */
     146#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
    189147
    190148#ifdef __cplusplus
    191 };
     149}
    192150#endif
    193151
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