Changeset 31a5ec8 in rtems


Ignore:
Timestamp:
May 5, 2009, 4:18:06 PM (11 years ago)
Author:
Jennifer Averett <Jennifer.Averett@…>
Branches:
4.9
Children:
8e230e6
Parents:
56e12a17
Message:

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
  • irq/no_pic.c: New file.
  • irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
Location:
c/src/lib/libbsp/powerpc/score603e
Files:
1 added
4 deleted
27 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/score603e/ChangeLog

    r56e12a17 r31a5ec8  
     12009-05-05      Jennifer Averett <jennifer.averett@OARcorp.com>
     2
     3        * Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c,
     4        PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c,
     5        console/85c30.h, console/console.c, console/consolebsp.h,
     6        console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h,
     7        include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h,
     8        irq/irq_init.c, start/start.S, startup/Hwr_init.c,
     9        startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with
     10        the latest powerpc isr source
     11        * irq/no_pic.c: New file.
     12        * irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
     13
    1142008-12-08      Ralf Corsépius <ralf.corsepius@rtems.org>
    215
  • c/src/lib/libbsp/powerpc/score603e/Makefile.am

    r56e12a17 r31a5ec8  
    2727    startup/bspstart.c ../../shared/bootcard.c \
    2828    ../../shared/sbrk.c startup/Hwr_init.c \
    29     startup/genpvec.c ../../shared/gnatinstallhandler.c \
     29    ../../shared/gnatinstallhandler.c \
    3030    ../../powerpc/shared/showbats.c
    3131
     
    3838        ../../powerpc/shared/residual/residual.h \
    3939        ../../powerpc/shared/residual/pnp.h \
    40         ../../powerpc/shared/console/consoleIo.h \
    41         ../../shared/include/irq-generic.h \
    42         include/irq-config.h
     40        ../../powerpc/shared/console/consoleIo.h
    4341
    44 pci_SOURCES = ../../powerpc/shared/pci/pci.c \
     42pci_SOURCES = PCI_bus/flash.c ../../powerpc/shared/pci/pci.c \
    4543    ../../powerpc/shared/pci/pcifinddevice.c  PCI_bus/PCI.c  PCI_bus/universe.c
    4644
     
    4947        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    5048        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    51 irq_SOURCES = include/irq-config.h \
    52     irq/FPGA.c irq/irq.c       \
    53     ../../shared/src/irq-generic.c       \
    54     ../../powerpc/shared/irq/irq_asm.S
    5549
    56 include_bsp_HEADERS += ../../powerpc/shared/vectors/vectors.h
    57 vectors_SOURCES = ../../powerpc/shared/vectors/vectors_init.c \
    58     ../../powerpc/shared/vectors/vectors.S
     50irq_SOURCES =  irq/no_pic.c irq/irq_init.c \
     51    irq/FPGA.c
    5952
    60 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
    61     ../../shared/include/irq-generic.h \
    62     ../../shared/vmeUniverse/vme_am_defs.h \
    63     ../../shared/vmeUniverse/VME.h \
    64     vme/VMEConfig.h \
    65     ../../powerpc/shared/motorola/motorola.h \
    66     ../../shared/vmeUniverse/vmeUniverseDMA.h\
    67     ../../shared/vmeUniverse/bspVmeDmaList.h\
    68     ../../shared/vmeUniverse/VMEDMA.h
    69 vme_SOURCES = \
    70     ../../shared/vmeUniverse/bspVmeDmaList.c \
    71     ../../shared/vmeUniverse/vme_am_defs.h \
    72         ../shared/vme/vmeconfig.c
     53vectors_SOURCES =
    7354
    7455EXTRA_DIST = start/start.S
     
    8465noinst_LIBRARIES = libbsp.a
    8566libbsp_a_SOURCES = $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
    86     $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) $(vme_SOURCES)
     67    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES)
    8768
    8869libbsp_a_LIBADD = \
     
    9273    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    9374    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     75    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
    9476    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    9577     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c

    r56e12a17 r31a5ec8  
    11/*
    22 *
    3  *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
     3 *  COPYRIGHT (c) 1989-2009.
    44 *  On-Line Applications Research Corporation (OAR).
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in the file LICENSE in this distribution or at
     8 *  http://www.rtems.com/license/LICENSE.
    59 *
    610 * $Id$
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h

    r56e12a17 r31a5ec8  
    44 *  PCI bus.
    55 *
    6  *  COPYRIGHT (c) 1989-1997.
     6 *  COPYRIGHT (c) 1989-2009.
    77 *  On-Line Applications Research Corporation (OAR).
    88 *
    9  *  The license and distribution terms for this file may in
    10  *  the file LICENSE in this distribution or at
     9 *  The license and distribution terms for this file may be
     10 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.rtems.com/license/LICENSE.
    1212 *
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c

    r56e12a17 r31a5ec8  
    11/*
    22 *
    3  *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
     3 *  COPYRIGHT (c) 1989-2009.
    44 *  On-Line Applications Research Corporation (OAR).
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in the file LICENSE in this distribution or at
     8 *  http://www.rtems.com/license/LICENSE.
    59 *
    610 * $Id$
     
    1216
    1317#include <bsp.h>
     18#include <bsp/irq.h>
    1419#include "PCI.h"
     20
    1521/*PAGE
    1622 *
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c

    r56e12a17 r31a5ec8  
    11/*
     2 *  COPYRIGHT (c) 1989-2009.
     3 *  On-Line Applications Research Corporation (OAR).
    24 *
    3  *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
    4  *  On-Line Applications Research Corporation (OAR).
     5 *  The license and distribution terms for this file may be
     6 *  found in the file LICENSE in this distribution or at
     7 *  http://www.rtems.com/license/LICENSE.
    58 *
    69 * $Id$
  • c/src/lib/libbsp/powerpc/score603e/README

    r56e12a17 r31a5ec8  
    2323SCSI:               none
    2424NETWORKING:         none
     25MEZZANINE CARD      optional with HAS_PMC_PSC8
     26                    4 Z85C30s
     27                    ACE1553
    2528
    2629DRIVER INFORMATION
     
    4447=====
    4548This BSP has been modified to use the latest exception model.
    46 However, the modifications were never verified.  This version
    47 has been partially verified in that Hello.ralf will load and
    48 run on the board.
     49The modifications were verified.
    4950
    5051This BSP has been tested using DINK Rom monitor.  There have
  • c/src/lib/libbsp/powerpc/score603e/configure.ac

    r56e12a17 r31a5ec8  
    3838[whether using console interrupts])
    3939
    40 RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[1])
     40RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[0])
    4141RTEMS_BSPOPTS_HELP([HAS_PMC_PSC8],
    4242[whether has a PSC8 PMC board attached to PMC slot])
  • c/src/lib/libbsp/powerpc/score603e/console/85c30.c

    r56e12a17 r31a5ec8  
    55 *  Currently only polled mode is supported.
    66 *
    7  *  COPYRIGHT (c) 1989-2008.
     7 *  COPYRIGHT (c) 1989-2009.
    88 *  On-Line Applications Research Corporation (OAR).
    99 *
     
    1111 *  found in the file LICENSE in this distribution or at
    1212 *  http://www.rtems.com/license/LICENSE.
    13  *
    14  *  $Id:
     13 * 
     14 *  $Id$
    1515 */
    1616
     
    130130  uint16_t                baud_constant;
    131131
    132 printk("initialize_85c30_port start\n");
    133 
    134132  Setup = Port->Protocol;
    135133  ctrl  = Port->ctrl;
     
    156154   *  Set Write Register 2 to contain the interrupt vector
    157155   */
    158 printk("initialize_85c30_port 2, %d\n", Port->Chip->vector );
    159156  Write_85c30_register( ctrl, 2, Port->Chip->vector );
    160157#endif
     
    163160   *  Set Write Register 3 to disable the Receiver
    164161   */
    165 printk("initialize_85c30_port 0x03, 0x00\n");
    166162  Write_85c30_register( ctrl, 0x03, 0x00 );
    167163
     
    169165   *  Set Write Register 5 to disable the Transmitter
    170166   */
    171 printk("initialize_85c30_port 5, 0x00\n");
    172167  Write_85c30_register( ctrl, 5, 0x00 );
    173168
     
    179174   *  Set Write Register 9 to disable all interrupt sources
    180175   */
    181 printk("initialize_85c30_port 9, 0x00\n");
    182176  Write_85c30_register( ctrl, 9, 0x00 );
    183177
     
    185179   *  Set Write Register 10 for simple Asynchronous operation
    186180   */
    187 printk("initialize_85c30_port 0x0a, 0x00\n");
    188181  Write_85c30_register( ctrl, 0x0a, 0x00 );
    189182
     
    193186   * as the output source for TRxC pin via register 11
    194187   */
    195 printk("initialize_85c30_port 0x0b, 0x56\n");
    196188  Write_85c30_register( ctrl, 0x0b, 0x56 );
    197189
     
    203195   * baud rate will be equilvalent to 9600, via register 12.
    204196   */
    205 printk("initialize_85c30_port 0x0c, 0x%x\n", value & 0xff);
    206197  Write_85c30_register( ctrl, 0x0c, value & 0xff );
    207198
     
    210201   * Setup the upper 8 bits time constants = 0
    211202   */
    212 printk("initialize_85c30_port 0x0d, 0x%x\n", value>>8);
    213203  Write_85c30_register( ctrl, 0x0d, value>>8 );
    214204
     
    219209   * SCC's PCLK input via register 14.
    220210   */
    221 printk("initialize_85c30_port 0x0e, 0x07\n");
    222211  Write_85c30_register( ctrl, 0x0e, 0x07 );
    223212
     
    235224  value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
    236225
    237 printk("initialize_85c30_port 0x03, 0x%x\n", value);
    238226  Write_85c30_register( ctrl, 0x03, value );
    239227
     
    250238  value = 0x8a;
    251239  value = value |  Char_size_85c30[ Setup->write_char_bits ].write_setup;
    252 printk("initialize_85c30_port 0x05, 0x%x\n", value);
    253240  Write_85c30_register( ctrl, 0x05, value );
    254241
     
    257244   * via register 0
    258245   */
    259 printk("initialize_85c30_port 0x00, 0xf0\n");
    260246   Write_85c30_register( ctrl, 0x00, 0xf0 );
    261247
     
    264250   *  Set Write Register 1 to interrupt on Rx characters or special condition.
    265251   */
    266 printk("initialize_85c30_port 1, 0x10\n");
    267252  Write_85c30_register( ctrl, 1, 0x10 );
    268253#endif
     
    272257   */
    273258
    274 printk("initialize_85c30_port 15, 0x00\n");
    275259  Write_85c30_register( ctrl, 15, 0x00 );
    276260
     
    278262   *  Set the Command Register to Reset Ext/STATUS.
    279263   */
    280 printk("initialize_85c30_port 0x00, 0x10\n");
    281264  Write_85c30_register( ctrl, 0x00, 0x10 );
    282265
     
    289272   *    Enables Tx interrupt.
    290273   */
    291 printk("initialize_85c30_port 1, 0x16\n");
    292274  Write_85c30_register( ctrl, 1, 0x16 );
    293275
     
    296278   *  Changed from 0 to a
    297279   */
    298 printk("initialize_85c30_port 9, 0x0A\n");
    299280  Write_85c30_register( ctrl, 9, 0x0A );
    300281
     
    304285   *  Issue reset highest Interrupt Under Service (IUS) command.
    305286   */
    306 printk("initialize_85c30_port STATUS_REGISTER, 0X38\n");
    307287  Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
    308288
    309289#endif
    310290
    311 printk("initialize_85c30_port end of method\n");
    312291}
    313292
  • c/src/lib/libbsp/powerpc/score603e/console/85c30.h

    r56e12a17 r31a5ec8  
    33 *  This include file contains z85c30 chip information.
    44 *
    5  *  COPYRIGHT (c) 1989-1999.
     5 *  COPYRIGHT (c) 1989-2009.
    66 *  On-Line Applications Research Corporation (OAR).
    77 *
    8  *  The license and distribution terms for this file may in
    9  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    1111 *
    12  *  $Id:
     12 *  $Id$
    1313 */
    1414
  • c/src/lib/libbsp/powerpc/score603e/console/console.c

    r56e12a17 r31a5ec8  
    66 *  Currently only polled mode is supported.
    77 *
    8  *  COPYRIGHT (c) 1989-1997.
     8 *  COPYRIGHT (c) 1989-2009.
    99 *  On-Line Applications Research Corporation (OAR).
    1010 *
     
    182182  int                        port, chip, p0,p1;
    183183
    184 printk("console_initialize start\n");
    185 
    186184  /*
    187185   * initialize the termio interface.
     
    208206 */
    209207#if ( INITIALIZE_COM_PORTS )
    210 
    211208  /*
    212209   * Force to perform a hardware reset w/o
     
    240237  for (port=1; port<NUM_Z85C30_PORTS; port++) {
    241238   chip = port >> 1;
    242 printk("console_initialize initialize_85c30_port %d\n", port);
    243239    initialize_85c30_port( &Ports_85C30[port] );
    244240  }
    245241
    246242#if CONSOLE_USE_INTERRUPTS
    247 printk("console_initialize console_initialize_interrupts\n");
    248243  console_initialize_interrupts();
    249244#endif
    250245
    251 printk("console_initialize end\n");
    252246  return RTEMS_SUCCESSFUL;
    253247}
     
    421415    rtems_interrupt_disable( isrlevel );
    422416    outbyte_polled_85c30( csr, '\r' );
     417    asm volatile("isync");
    423418    rtems_interrupt_enable( isrlevel );
    424     asm volatile("isync");
    425419  }
    426420
    427421  rtems_interrupt_disable( isrlevel );
    428422  outbyte_polled_85c30( csr, c );
     423  asm volatile("isync");
    429424  rtems_interrupt_enable( isrlevel );
    430425}
  • c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h

    r56e12a17 r31a5ec8  
    33 *  This include file contains all console driver definations
    44 *
    5  *  COPYRIGHT (c) 1989-1997.
     5 *  COPYRIGHT (c) 1989-2009.
    66 *  On-Line Applications Research Corporation (OAR).
    77 *
    8  *  The license and distribution terms for this file may in
    9  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    1111 *
    12  *  $Id:
     12 *  $Id$
    1313 */
    1414
  • c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c

    r56e12a17 r31a5ec8  
    33 *  used by the console driver.
    44 *
    5  *  COPYRIGHT (c) 1989-1997.
     5 *  COPYRIGHT (c) 1989-2009.
    66 *  On-Line Applications Research Corporation (OAR).
    77 *
     
    1010 *  http://www.rtems.com/license/LICENSE.
    1111 *
    12  *  $Id:
     12 *  $Id$
    1313 */
    1414
    1515#include "consolebsp.h"
    1616#include <bsp.h>
     17#include <bsp/irq.h>
    1718
    1819#define CONSOLE_DEFAULT_BAUD_RATE            9600
  • c/src/lib/libbsp/powerpc/score603e/include/bsp.h

    r56e12a17 r31a5ec8  
    33 *  This include file contains all board IO definitions.
    44 *
    5  *  COPYRIGHT (c) 1989-1997.
     5 *  COPYRIGHT (c) 1989-2009.
    66 *  On-Line Applications Research Corporation (OAR).
    77 *
    8  *  The license and distribution terms for this file may in
    9  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    1111 *
     
    1919extern "C" {
    2020#endif
     21
     22#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
    2123
    2224#include <bspopts.h>
     
    3638#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
    3739#else
    38 /* XXXXX FIX THIS */
    39 #error "MUST HAVE PSC8 SET FOR BOEING CODE"
    4040#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
    4141#endif
     
    5656
    5757#include <gen2.h>
     58#include <bsp/irq.h>
    5859
    5960/*
     
    174175);
    175176
     177void mask_irq(
     178  uint16_t         irq_idx
     179);
     180
    176181void init_irq_data_register();
    177182
  • c/src/lib/libbsp/powerpc/score603e/include/coverhd.h

    r56e12a17 r31a5ec8  
    1616 *
    1717 *
    18  *  COPYRIGHT (c) 1989-1997.
     18 *  COPYRIGHT (c) 1989-2009.
    1919 *  On-Line Applications Research Corporation (OAR).
    2020 *
    21  *  The license and distribution terms for this file may in
    22  *  the file LICENSE in this distribution or at
     21 *  The license and distribution terms for this file may be
     22 *  found in the file LICENSE in this distribution or at
    2323 *  http://www.rtems.com/license/LICENSE.
    2424 *
  • c/src/lib/libbsp/powerpc/score603e/include/gen2.h

    r56e12a17 r31a5ec8  
    33 *  This include file contains all Generation 2 board addreses
    44 *
    5  *  COPYRIGHT (c) 1989-1997.
     5 *  COPYRIGHT (c) 1989-2009.
    66 *  On-Line Applications Research Corporation (OAR).
    77 *
    8  *  The license and distribution terms for this file may in
    9  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    1111 *
    12  *  $Id:
     12 *  $Id$
    1313 */
    1414
     
    179179 */
    180180
    181 /*
    182  * First Score Unique IRQ
    183  */
    184 #define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
    185 
    186 /*
    187  * The Following Are part of a Score603e FPGA.
    188  */
    189 #define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
    190 #define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
    191 #define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
    192 #define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
    193 #define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
    194 #define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
    195 #define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
    196 #define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
    197 #define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
    198 #define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
    199 #define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
    200 #define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
    201 #define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
    202 #define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
    203 #define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
    204 #define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
    205 
    206 #define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
    207 #define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
    208 #define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
    209 #define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
    210 #define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
    211 #define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
    212 #define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
    213 #define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
    214 #define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
    215 #define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
    216 #define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
    217 #define SCORE603E_1553_IRQ             SCORE603E_IRQ11
    218 #define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
    219 #define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
    220 #define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
    221 #define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
    222 
    223 /*
    224  * The Score FPGA maps all interrupts comming from the PMC card to
    225  * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
    226  * read to indicate which interrupt was chained to the FPGA.
    227  */
    228 #define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
    229 #define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
    230 #define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
    231 #define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
    232 
    233 /*
    234  * IRQ'a read from the PMC card
    235  */
    236 #define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
    237 #define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
    238 #define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
    239 #define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
    240 
    241 #define MAX_BOARD_IRQS                 SCORE603E_IRQ19
    242181
    243182/*
     
    265204  (int) (((_value) * 4000) / 6667)
    266205
    267 #endif
    268 
    269206#ifdef __cplusplus
    270207}
    271208#endif
     209
     210#endif
     211
  • c/src/lib/libbsp/powerpc/score603e/include/irq-config.h

    r56e12a17 r31a5ec8  
    55 *
    66 * @brief BSP interrupt support configuration.
     7 *
     8 * $Id$
    79 */
    810
  • c/src/lib/libbsp/powerpc/score603e/include/tm27.h

    r56e12a17 r31a5ec8  
    11/*
    22 *  tm27.h
     3 *
     4 *  COPYRIGHT (c) 1989-2009.
     5 *  On-Line Applications Research Corporation (OAR).
    36 *
    47 *  The license and distribution terms for this file may be
  • c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c

    r56e12a17 r31a5ec8  
    11/*  FPGA.c -- Bridge for second and subsequent generations
    22 *
    3  *  COPYRIGHT (c) 1989-2001.
     3 *  COPYRIGHT (c) 1989-2009.
    44 *  On-Line Applications Research Corporation (OAR).
    55 *
    6  *  The license and distribution terms for this file may in
    7  *  the file LICENSE in this distribution or at
     6 *  The license and distribution terms for this file may be
     7 *  found in the file LICENSE in this distribution or at
    88 *  http://www.rtems.com/license/LICENSE.
    99 *
     
    1212
    1313#include <bsp.h>
     14#include <bsp/irq.h>
    1415#include <string.h>
    1516#include <fcntl.h>
     
    2829   *       change anything.
    2930   */
    30   printk("initialize_PCI_bridge: \n");
    3131}
    3232
     
    3535)
    3636{
    37   uint16_t          *loc;
     37  volatile uint16_t   *loc;
    3838
    3939  loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;
     
    4444uint16_t         get_irq_mask(voi)
    4545{
    46   uint16_t          *loc;
    47   uint16_t          value;
     46  volatile uint16_t  *loc;
     47  uint16_t            value;
    4848
    4949  loc =  (uint16_t*)SCORE603E_FPGA_MASK_DATA;
     
    5252
    5353  return value;
     54}
     55
     56void mask_irq(
     57  uint16_t         irq_idx
     58)
     59{
     60  uint16_t         value;
     61  uint32_t         mask_idx = irq_idx;
     62
     63  value = get_irq_mask();
     64
     65#if (HAS_PMC_PSC8)
     66  switch (irq_idx + Score_IRQ_First ) {
     67    case SCORE603E_85C30_4_IRQ:
     68    case SCORE603E_85C30_2_IRQ:
     69    case SCORE603E_85C30_5_IRQ:
     70    case SCORE603E_85C30_3_IRQ:
     71      mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
     72      break;
     73    default:
     74      break;
     75  }
     76#endif
     77
     78  value |= (0x1 << mask_idx);
     79  set_irq_mask( value );
    5480}
    5581
     
    101127)
    102128{
    103   uint16_t            status_word = irq;
     129  uint16_t   status_word = irq;
    104130
    105131  status_word = (*BSP_PMC_STATUS_ADDRESS);
     
    140166  uint16_t            irq;
    141167
     168
    142169  irq = (*SCORE603E_FPGA_VECT_DATA);
    143 
     170  Processor_Synchronize();
    144171  if ((irq & 0xffff0) != 0x10) {
    145     printk( "ERROR:: no irq data\n");
     172    printk( "read_and_clear_irq:: ERROR==>no irq data 0x%x\n", irq);
    146173    return (irq | 0x80);
    147174  }
    148175
    149176  irq &=0xf;
    150 
     177  irq += Score_IRQ_First;
    151178  return irq;
    152179}
  • c/src/lib/libbsp/powerpc/score603e/irq/irq.h

    r56e12a17 r31a5ec8  
    44 *  by RTEMS to write interrupt handlers.
    55 *
    6  *  Copyright (C) 1999 valette@crf.canon.fr
    7  *
    86 *  This code is heavilly inspired by the public specification of STREAM V2
    97 *  that can be found at :
    108 *
    11  *      <http://www.chorus.com/Documentation/index.html> by following
     9 *  <http://www.chorus.com/Documentation/index.html> by following
    1210 *  the STREAM API Specification Document link.
    1311 *
     12 *  COPYRIGHT (c) 1989-2009.
     13 *  On-Line Applications Research Corporation (OAR).
     14 *
    1415 *  The license and distribution terms for this file may be
    15  *  found in found in the file LICENSE in this distribution or at
     16 *  found in the file LICENSE in this distribution or at
    1617 *  http://www.rtems.com/license/LICENSE.
    1718 *
     
    2526#include <rtems/irq.h>
    2627
    27 /*
    28  * 8259 edge/level control definitions at VIA
    29  */
    30 #define ISA8259_M_ELCR          0x4d0
    31 #define ISA8259_S_ELCR          0x4d1
    32 
    33 #define ELCRS_INT15_LVL         0x80
    34 #define ELCRS_INT14_LVL         0x40
    35 #define ELCRS_INT13_LVL         0x20
    36 #define ELCRS_INT12_LVL         0x10
    37 #define ELCRS_INT11_LVL         0x08
    38 #define ELCRS_INT10_LVL         0x04
    39 #define ELCRS_INT9_LVL          0x02
    40 #define ELCRS_INT8_LVL          0x01
    41 #define ELCRM_INT7_LVL          0x80
    42 #define ELCRM_INT6_LVL          0x40
    43 #define ELCRM_INT5_LVL          0x20
    44 #define ELCRM_INT4_LVL          0x10
    45 #define ELCRM_INT3_LVL          0x8
    46 #define ELCRM_INT2_LVL          0x4
    47 #define ELCRM_INT1_LVL          0x2
    48 #define ELCRM_INT0_LVL          0x1
    49 
    50     /* PIC's command and mask registers */
    51 #define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
    52 #define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
    53 #define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
    54 #define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
    55 
    56     /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    57 #define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
    58 #define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    59 #define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    60 
    6128#ifndef ASM
    6229
     
    6431extern "C" {
    6532#endif
     33
    6634
    6735/*
     
    7543#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
    7644#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
     45
    7746/*
    7847 * PCI IRQ handlers related definitions
    79  * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
    8048 */
    8149#define BSP_PCI_IRQ_NUMBER              (16)
    8250#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
    8351#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
     52
     53/*
     54 * PMC IRQ
     55 */
     56#define BSP_PMC_IRQ_NUMBER              (4)
     57#define BSP_PMC_IRQ_LOWEST_OFFSET       (BSP_PCI_IRQ_MAX_OFFSET + 1)
     58#define BSP_PMC_IRQ_MAX_OFFSET          (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
     59
     60
    8461/*
    8562 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
     
    8764 */
    8865#define BSP_PROCESSOR_IRQ_NUMBER        (1)
    89 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
     66#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
    9067#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
     68
    9169/* Misc vectors for OPENPIC irqs (IPI, timers)
    9270 */
     
    10078#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
    10179#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    102 /*
    103  * Some ISA IRQ symbolic name definition
    104  */
    105 #define BSP_ISA_PERIODIC_TIMER          (0)
    106 #define BSP_ISA_KEYBOARD                (1)
    107 #define BSP_ISA_UART_COM2_IRQ           (3)
    108 #define BSP_ISA_UART_COM1_IRQ           (4)
    109 #define BSP_ISA_RT_TIMER1               (8)
    110 #define BSP_ISA_RT_TIMER3               (10)
    111 /*
    112  * Some PCI IRQ symbolic name definition
    113  */
    114 #define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
    115 #define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
    116 
    117 #if defined(mvme2100)
    118 #define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
    119 #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
    120 #define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
    121 #define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
    122 #define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
    123 #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
    124 #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
    125 #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
    126 #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
    127 #define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
    128 #define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
    129 #define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
    130 #else
    131 #define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
    132 #define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
    133 #endif
    13480
    13581/*
     
    13884#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    13985
     86/*
     87 * First Score Unique IRQ
     88 */
     89#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
    14090
    14191/*
    142  * Type definition for RTEMS managed interrupts
     92 * The Following Are part of a Score603e FPGA.
    14393 */
    144 typedef unsigned short rtems_i8259_masks;
     94#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
     95#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
     96#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
     97#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
     98#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
     99#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
     100#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
     101#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
     102#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
     103#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
     104#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
     105#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
     106#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
     107#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
     108#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
     109#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
    145110
    146 extern  volatile rtems_i8259_masks i8259s_cache;
    147 
    148 /*-------------------------------------------------------------------------+
    149 | Function Prototypes.
    150 +--------------------------------------------------------------------------*/
    151 /*
    152  * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
    153  */
    154 void BSP_i8259s_init(void);
     111#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
     112#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
     113#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
     114#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
     115#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
     116#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
     117#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
     118#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
     119#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
     120#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
     121#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
     122#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
     123#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
     124#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
     125#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
     126#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
    155127
    156128/*
    157  * function to disable a particular irq at 8259 level. After calling
    158  * this function, even if the device asserts the interrupt line it will
    159  * not be propagated further to the processor
    160  *
    161  * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
    162  *          a value < 0 on error.
     129 * The Score FPGA maps all interrupts comming from the PMC card to
     130 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
     131 * read to indicate which interrupt was chained to the FPGA.
    163132 */
    164 int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
     133#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
     134#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
     135#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
     136#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
     137
    165138/*
    166  * function to enable a particular irq at 8259 level. After calling
    167  * this function, if the device asserts the interrupt line it will
    168  * be propagated further to the processor
     139 * IRQ'a read from the PMC card
    169140 */
    170 int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
    171 /*
    172  * function to acknowledge a particular irq at 8259 level. After calling
    173  * this function, if a device asserts an enabled interrupt line it will
    174  * be propagated further to the processor. Mainly usefull for people
    175  * writing raw handlers as this is automagically done for RTEMS managed
    176  * handlers.
    177  */
    178 int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
    179 /*
    180  * function to check if a particular irq is enabled at 8259 level. After calling
    181  */
    182 int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
     141#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
     142#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
     143#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
     144#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
    183145
    184 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
    185 extern void BSP_i8259s_init(void);
    186 
    187 /* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
    188 /* #include <bsp/irq_supp.h> */
     146#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
    189147
    190148#ifdef __cplusplus
    191 };
     149}
    192150#endif
    193151
  • c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c

    r56e12a17 r31a5ec8  
    2323#include <bsp/pci.h>
    2424#include <bsp/residual.h>
    25 #include <bsp/openpic.h>
    2625#include <bsp/irq.h>
    2726#include <bsp.h>
    2827#include <libcpu/raw_exception.h>
    29 #include <bsp/motorola.h>
    3028#include <rtems/bspIo.h>
    3129
    3230#define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
    3331#define SCAN_PCI_PRINT               1
    34 #define TRACE_IRQ_INIT               1
     32#define TRACE_IRQ_INIT               0
    3533
    3634typedef struct {
     
    4139
    4240pci_isa_bridge_device* via_82c586 = 0;
    43 static pci_isa_bridge_device bridge;
    4441
    4542extern unsigned int external_exception_vector_prolog_code_size[];
     
    4845extern void decrementer_exception_vector_prolog_code(void);
    4946
    50 /*
    51  * default on/off function
    52  */
    53 static void nop_func(void){}
    54 /*
    55  * default isOn function
    56  */
    57 static int not_connected(void) {return 0;}
    58 /*
    59  * default possible isOn function
    60  */
    61 static int connected(void) {return 1;}
     47static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) {}
     48static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr){}
     49static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr){}
     50static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
    6251
    6352static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
    6453static rtems_irq_global_settings        initial_config;
     54
    6555static rtems_irq_connect_data           defaultIrq = {
    66   /* vectorIdex,         hdl            , handle        , on            , off           , isOn */
    67   0,                     nop_func       , NULL          , nop_func      , nop_func      , not_connected
    68 };
    69 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
    70   /*
    71    * actual priorities for interrupt :
    72    *    0   means that only current interrupt is masked
    73    *    255 means all other interrupts are masked
    74    */
    75   /*
    76    * ISA interrupts.
    77    * The second entry has a priority of 255 because
    78    * it is the slave pic entry and should always remain
    79    * unmasked.
    80    */
    81   0,0,
    82   255,
    83   0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
    84   /*
    85    * PCI Interrupts
    86    */
    87   8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
    88   /*
    89    * Processor exceptions handled as interrupts
    90    */
    91   0
     56/*name,  hdl                            handle  on                              off                             isOn */
     57  0,     IRQ_Default_rtems_irq_hdl,     NULL,   IRQ_Default_rtems_irq_enable,   IRQ_Default_rtems_irq_disable,  IRQ_Default_rtems_irq_is_enabled
    9258};
    9359
    94 #if defined(mvme2100)
    95 static unsigned char mvme2100_openpic_initpolarities[16] = {
    96     0,  /* Not used - should be disabled */
    97     0,  /* DEC21143 Controller */
    98     0,  /* PMC/PC-MIP Type I Slot 0 */
    99     0,  /* PC-MIP Type I Slot 1 */
    100     0,  /* PC-MIP Type II Slot 0 */
    101     0,  /* PC-MIP Type II Slot 1 */
    102     0,  /* Not used - should be disabled */
    103     0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
    104     0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
    105     0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
    106     0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
    107     0,  /* Not used - should be disabled */
    108     0,  /* Not used - should be disabled */
    109     1,  /* 16550 UART */
    110     0,  /* Front panel Abort Switch */
    111     0,  /* RTC IRQ */
    112 };
    113 
    114 static unsigned char mvme2100_openpic_initsenses[] = {
    115     0,  /* Not used - should be disabled */
    116     1,  /* DEC21143 Controller */
    117     1,  /* PMC/PC-MIP Type I Slot 0 */
    118     1,  /* PC-MIP Type I Slot 1 */
    119     1,  /* PC-MIP Type II Slot 0 */
    120     1,  /* PC-MIP Type II Slot 1 */
    121     0,  /* Not used - should be disabled */
    122     1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
    123     1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
    124     1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
    125     1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
    126     0,  /* Not used - should be disabled */
    127     0,  /* Not used - should be disabled */
    128     1,  /* 16550 UART */
    129     0,  /* Front panel Abort Switch */
    130     1,  /* RTC IRQ */
    131 };
    132 #else
    133 static unsigned char mcp750_openpic_initpolarities[16] = {
    134     1,  /* 8259 cascade */
    135     0,  /* all the rest of them */
    136 };
    137 
    138 static unsigned char mcp750_openpic_initsenses[] = {
    139     1,  /* MCP750_INT_PCB(8259) */
    140     0,  /* MCP750_INT_FALCON_ECC_ERR */
    141     1,  /* MCP750_INT_PCI_ETHERNET */
    142     1,  /* MCP750_INT_PCI_PMC */
    143     1,  /* MCP750_INT_PCI_WATCHDOG_TIMER1 */
    144     1,  /* MCP750_INT_PCI_PRST_SIGNAL */
    145     1,  /* MCP750_INT_PCI_FALL_SIGNAL */
    146     1,  /* MCP750_INT_PCI_DEG_SIGNAL */
    147     1,  /* MCP750_INT_PCI_BUS1_INTA */
    148     1,  /* MCP750_INT_PCI_BUS1_INTB */
    149     1,  /* MCP750_INT_PCI_BUS1_INTC */
    150     1,  /* MCP750_INT_PCI_BUS1_INTD */
    151     1,  /* MCP750_INT_PCI_BUS2_INTA */
    152     1,  /* MCP750_INT_PCI_BUS2_INTB */
    153     1,  /* MCP750_INT_PCI_BUS2_INTC */
    154     1,  /* MCP750_INT_PCI_BUS2_INTD */
    155 };
    156 #endif
    157 
    158 void VIA_isa_bridge_interrupts_setup(void)
    159 {
    160   pci_isa_bridge_device pci_dev;
    161   unsigned int temp;
    162   unsigned char tmp;
    163   unsigned char maxBus;
    164   unsigned found = 0;
    165 
    166   maxBus = pci_bus_count();
    167   pci_dev.function      = 0; /* Assumes the bidge is the first function */
    168 
    169   for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) {
    170 #ifdef SCAN_PCI_PRINT
    171     printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus);
    172 #endif
    173     for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) {
    174 #ifdef SCAN_PCI_PRINT
    175       printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device);
    176 #endif
    177       pci_read_config_dword(pci_dev.bus, pci_dev.device,  pci_dev.function,
    178                                PCI_VENDOR_ID, &temp);
    179 #ifdef SCAN_PCI_PRINT
    180       printk("Vendor/device = %x\n", temp);
    181 #endif
    182       if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16)))
    183          ) {
    184         bridge = pci_dev;
    185         via_82c586 = &bridge;
    186 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    187         /*
    188          * Should print : bus = 0, device = 11, function = 0 on a MCP750.
    189          */
    190         printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n",
    191                via_82c586->bus,
    192                via_82c586->device,
    193                via_82c586->function);
    194 #endif
    195         found = 1;
    196         goto loop_exit;
    197 
    198       }
    199     }
    200   }
    201 loop_exit:
    202   if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n");
    203 
    204   tmp = inb(0x810);
    205   if  ( !(tmp & 0x2)) {
    206 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    207     printk("This is a second generation MCP750 board\n");
    208     printk("We must reprogram the PCI/ISA bridge...\n");
    209 #endif
    210     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    211                          0x47,  &tmp);
    212 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    213     printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
    214 #endif
    215     /*
    216      * Enable 4D0/4D1 ISA interrupt level/edge config registers
    217      */
    218     tmp |= 0x20;
    219     pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    220                           0x47, tmp);
    221     /*
    222      * Now program the ISA interrupt edge/level
    223      */
    224     tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL;
    225     outb(tmp, ISA8259_S_ELCR);
    226     tmp = ELCRM_INT5_LVL;
    227     outb(tmp, ISA8259_M_ELCR);;
    228     /*
    229      * Set the Interrupt inputs to non-inverting level interrupt
    230      */
    231     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    232                             0x54, &tmp);
    233 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    234     printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
    235 #endif
    236     tmp = 0;
    237     pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    238                           0x54, tmp);
    239   }
    240   else {
    241 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    242     printk("This is a first generation MCP750 board\n");
    243     printk("We just show the actual value used by PCI/ISA bridge\n");
    244 #endif
    245     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    246                          0x47,  &tmp);
    247 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    248     printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
    249 #endif
    250     /*
    251      * Show the Interrupt inputs inverting/non-inverting level status
    252      */
    253     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    254                          0x54, &tmp);
    255 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    256     printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
    257 #endif
    258   }
    259 }
     60static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER];
    26061
    26162  /*
     
    26768void BSP_rtems_irq_mng_init(unsigned cpuId)
    26869{
    269 #if !defined(mvme2100)
    270   int known_cpi_isa_bridge = 0;
    271 #endif
    272   rtems_raw_except_connect_data vectorDesc;
    27370  int i;
    27471
     
    27673   * First initialize the Interrupt management hardware
    27774   */
    278 #if defined(mvme2100)
    279 #ifdef TRACE_IRQ_INIT
    280   printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
    281 #endif
    282   openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
    283 #else
    284 #ifdef TRACE_IRQ_INIT
    285   printk("Going to initialize raven interrupt controller (openpic compliant)\n");
    286 #endif
    287   openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
    288 #endif       
    289 
    290 #if !defined(mvme2100)
    291 #ifdef TRACE_IRQ_INIT 
    292   printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
    293 #endif
    294   if ( currentBoard == MESQUITE ) {
    295     VIA_isa_bridge_interrupts_setup();
    296     known_cpi_isa_bridge = 1;
    297   }
    298   if ( currentBoard == MVME_2300 ) {
    299     /* nothing to do for W83C553 bridge */
    300     known_cpi_isa_bridge = 1;
    301   }
    302   if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) {
    303      /* W83C554, don't to anything at the moment.  gregm 11/6/2002 */
    304      known_cpi_isa_bridge = 1;
    305   }
    306 
    307   if (!known_cpi_isa_bridge) {
    308     printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n");
    309     printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n");
    310     printk("currentBoard = %i\n", currentBoard);
    311   }
    312 #ifdef TRACE_IRQ_INIT
    313   printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
    314 #endif
    315   BSP_i8259s_init();
    316 #endif
    31775
    31876  /*
     
    32381     */
    32482    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
     83      irqPrioTable[i]  = 8;
    32584      rtemsIrq[i]      = defaultIrq;
    32685      rtemsIrq[i].name = i;
     86#ifdef BSP_SHARED_HANDLER_SUPPORT
     87      rtemsIrq[i].next_handler = NULL;
     88#endif
    32789    }
     90
    32891    /*
    32992     * Init initial Interrupt management config
     
    342105    }
    343106
    344   /*
    345    * We must connect the raw irq handler for the two
    346    * expected interrupt sources : decrementer and external interrupts.
    347    */
    348     vectorDesc.exceptIndex      =       ASM_DEC_VECTOR;
    349     vectorDesc.hdl.vector       =       ASM_DEC_VECTOR;
    350     vectorDesc.hdl.raw_hdl      =       decrementer_exception_vector_prolog_code;
    351     vectorDesc.hdl.raw_hdl_size =       (unsigned) decrementer_exception_vector_prolog_code_size;
    352     vectorDesc.on               =       nop_func;
    353     vectorDesc.off              =       nop_func;
    354     vectorDesc.isOn             =       connected;
    355     if (!ppc_set_exception (&vectorDesc)) {
    356       BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
    357     }
    358     vectorDesc.exceptIndex      =       ASM_EXT_VECTOR;
    359     vectorDesc.hdl.vector       =       ASM_EXT_VECTOR;
    360     vectorDesc.hdl.raw_hdl      =       external_exception_vector_prolog_code;
    361     vectorDesc.hdl.raw_hdl_size =       (unsigned) external_exception_vector_prolog_code_size;
    362     if (!ppc_set_exception (&vectorDesc)) {
    363       BSP_panic("Unable to initialize RTEMS external raw exception\n");
    364     }
    365107#ifdef TRACE_IRQ_INIT
    366108    printk("RTEMS IRQ management is now operational\n");
  • c/src/lib/libbsp/powerpc/score603e/preinstall.am

    r56e12a17 r31a5ec8  
    8686PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h
    8787
    88 $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    89         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
    90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
    91 
    92 $(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    93         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
    94 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
    95 
    9688$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    9789        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     
    110102PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    111103
    112 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    113         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    114 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    115 
    116 $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    117         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
    118 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
    119 
    120 $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    121         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
    122 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
    123 
    124 $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    125         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    126 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    127 
    128 $(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    129         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
    130 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VME.h
    131 
    132 $(PROJECT_INCLUDE)/bsp/VMEConfig.h: vme/VMEConfig.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    133         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEConfig.h
    134 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEConfig.h
    135 
    136 $(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    137         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h
    138 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/motorola.h
    139 
    140 $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h: ../../shared/vmeUniverse/vmeUniverseDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    141         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h
    142 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h
    143 
    144 $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h: ../../shared/vmeUniverse/bspVmeDmaList.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    145         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h
    146 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h
    147 
    148 $(PROJECT_INCLUDE)/bsp/VMEDMA.h: ../../shared/vmeUniverse/VMEDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    149         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEDMA.h
    150 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEDMA.h
    151 
    152104$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    153105        $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
  • c/src/lib/libbsp/powerpc/score603e/start/start.S

    r56e12a17 r31a5ec8  
    1515 * they apply.
    1616 *
    17  *  $Id$
     17 * $Id$
    1818 */
    1919
  • c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c

    r56e12a17 r31a5ec8  
    11/*  Hwr_init.c
     2 *
     3 *  COPYRIGHT (c) 1989-2009.
     4 *  On-Line Applications Research Corporation (OAR).
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in the file LICENSE in this distribution or at
     8 *  http://www.rtems.com/license/LICENSE.
    29 *
    310 *  $Id$
     
    8390  /* DINK Monitor setsup and uses all 4 BAT registers.  */
    8491  /* The fourth BAT register can be modified to access this area */
    85 
    86   printk("init_PCI:\n");
    8792}
    8893
  • c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c

    r56e12a17 r31a5ec8  
    66 *  before any of these are invoked.
    77 *
    8  *  COPYRIGHT (c) 1989-2007.
     8 *  COPYRIGHT (c) 1989-2009.
    99 *  On-Line Applications Research Corporation (OAR).
    1010 *
    11  *  The license and distribution terms for this file may in
    12  *  the file LICENSE in this distribution or at
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
    1313 *  http://www.rtems.com/license/LICENSE.
    1414 *
    15  *  $Id:
     15 *  $Id$
    1616 */
    1717
     
    2323#include <rtems/bspIo.h>
    2424#include <libcpu/cpuIdent.h>
    25 #define DEBUG 1
     25
     26#define DEBUG 0
    2627
    2728/*
     
    3334 * PCI Bus Frequency
    3435 */
    35 unsigned int BSP_bus_frequency;  /* XXX - Set this based upon the Score board */
     36unsigned int BSP_bus_frequency; 
    3637
    3738/*
    3839 * processor clock frequency
    3940 */
    40 unsigned int BSP_processor_frequency; /* XXX - Set this based upon the Score board */
     41unsigned int BSP_processor_frequency;
    4142
    4243/*
     
    9192  uint32_t         heap_size;
    9293
    93   #if DEBUG
    94     printk("bsp_pretasking_hook: Set Heap\n");
    95   #endif
    96   heap_start = (uint32_t) &end;
    97   if (heap_start & (CPU_ALIGNMENT-1))
    98     heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
    99 
    100   heap_size = Configuration.work_space_start - (void *)&end;
     94  heap_start = (BSP_heap_start + CPU_ALIGNMENT - 1) & ~(CPU_ALIGNMENT-1);
     95  heap_size = (uint32_t) &RAM_END;
     96  heap_size = heap_size - heap_start - Configuration.work_space_size;
    10197  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
     98 
     99
     100  #if DEBUG
     101    printk("bsp_pretasking_hook: Set Heap start 0x%x size 0x%x\n", heap_start, heap_size);
     102  #endif
    102103
    103104  #if DEBUG
     
    122123void bsp_predriver_hook(void)
    123124{
     125  init_PCI();
     126  initialize_universe();
     127
     128  #if DEBUG
     129    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
     130  #endif
     131  initialize_PCI_bridge ();
    124132
    125133#if (HAS_PMC_PSC8)
     
    182190void bsp_postdriver_hook(void)
    183191{
    184   extern void Init_EE_mask_init(void);
    185192  extern void open_dev_console(void);
    186193  #if DEBUG
     
    188195  #endif
    189196  open_dev_console();
    190 
    191   #if DEBUG
    192     printk("bsp_postdriver_hook: Init_EE_mask_init\n");
    193   #endif
    194   Init_EE_mask_init();
    195197  #if DEBUG
    196198    printk("bsp_postdriver_hook: Finished procedure\n");
     
    251253  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    252254  BSP_heap_start = intrStackStart + intrStackSize;
     255  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
     256    intrStackStart, intrStackSize, BSP_heap_start
     257  );
    253258
    254259  /*
     
    260265    intrStackSize
    261266  );
    262   #if DEBUG
    263     printk("bsp_predriver_hook: init_RTC\n");
    264   #endif
    265 
    266 /*   init_RTC(); */
    267   init_PCI();
    268   initialize_universe();
    269 
    270   #if DEBUG
    271     printk("bsp_predriver_hook: initialize_PCI_bridge\n");
    272   #endif
    273   initialize_PCI_bridge ();
    274267
    275268  msr_value = 0x2030;
    276269  _CPU_MSR_SET( msr_value );
    277 
    278270
    279271  _CPU_MSR_SET( msr_value );
     
    284276   *  not malloc'ed.  It is just "pulled from the air".
    285277   */
    286 
    287   #if DEBUG
    288     printk("bsp_start: Calculate Wrokspace\n");
    289   #endif
    290278  work_space_start =
    291279    (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
     280  printk("Work Space Start: 0x%x\n", work_space_start );
    292281
    293282  if ( work_space_start <= (unsigned char *)&end ) {
     
    306295  bsp_clicks_per_usec = 66 / 4;  /* XXX get from linkcmds */
    307296
    308 #if ( PPC_USE_DATA_CACHE )
    309   #if DEBUG
    310     printk("bsp_start: cache_enable\n");
    311   #endif
    312   instruction_cache_enable ();
    313   data_cache_enable ();
    314   #if DEBUG
    315     printk("bsp_start: END PPC_USE_DATA_CACHE\n");
    316   #endif
    317 #endif
    318 
    319   /* Initalize interrupt support */
    320   if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    321     BSP_panic( "Cannot intitialize interrupt support\n");
    322   }
    323 
     297  #if ( PPC_USE_DATA_CACHE )
     298    #if DEBUG
     299      printk("bsp_start: cache_enable\n");
     300    #endif
     301    instruction_cache_enable ();
     302    data_cache_enable ();
     303    #if DEBUG
     304      printk("bsp_start: END PPC_USE_DATA_CACHE\n");
     305    #endif
     306  #endif
     307
     308  /*
     309   * Initalize RTEMS IRQ system
     310   */
     311  #if DEBUG 
     312    printk("bspstart: Call BSP_rtems_irq_mng_init\n");
     313  #endif
     314  BSP_rtems_irq_mng_init(0);
     315 
    324316  #if DEBUG
    325317    printk("bsp_start: end BSPSTART\n");
    326   ShowBATS();
    327   #endif
    328 }
     318    ShowBATS();
     319  #endif
     320}
  • c/src/lib/libbsp/powerpc/score603e/timer/timer.c

    r56e12a17 r31a5ec8  
    88 *  provided in bsp.h
    99 *
    10  *  COPYRIGHT (c) 1989-1997.
     10 *  COPYRIGHT (c) 1989-2009.
    1111 *  On-Line Applications Research Corporation (OAR).
    1212 *
    13  *  The license and distribution terms for this file may in
    14  *  the file LICENSE in this distribution or at
     13 *  The license and distribution terms for this file may be
     14 *  found in the file LICENSE in this distribution or at
    1515 *  http://www.rtems.com/license/LICENSE.
    1616 *
  • c/src/lib/libbsp/powerpc/score603e/tod/tod.c

    r56e12a17 r31a5ec8  
    33 *
    44 *  This part is found on the second generation of this board.
     5 *
     6 *  COPYRIGHT (c) 1989-2009.
     7 *  On-Line Applications Research Corporation (OAR).
    58 *
    69 *  The license and distribution terms for this file may be
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