Changeset 3103d4c in rtems


Ignore:
Timestamp:
Jun 23, 2010, 8:27:57 AM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
8dbb864f
Parents:
b18fd86
Message:

2010-06-23 Sebastian Huber <sebastian.huber@…>

  • make/custom/lpc32xx_mzx_boot_int.cfg, startup/linkcmds.lpc32xx_mzx_boot_int: Removed files.
  • include/boot.h, include/emc.h, include/i2c.h, include/nand-mlc.h, make/custom/lpc32xx_mzx.cfg, make/custom/lpc32xx_mzx_stage_1.cfg, make/custom/lpc32xx_mzx_stage_2.cfg, misc/boot.c, misc/emc.c, misc/i2c.c, misc/nand-mlc.c, misc/nand-mlc-read-blocks.c, misc/nand-mlc-write-blocks.c, misc/restart.c, startup/linkcmds.lpc32xx, startup/linkcmds.lpc32xx_mzx, startup/linkcmds.lpc32xx_mzx_stage_1, startup/linkcmds.lpc32xx_mzx_stage_2: New files.
  • configure.ac, Makefile.am, preinstall.am: Reflect changes above.
  • include/bsp.h, include/lpc32xx.h, irq/irq.c, rtc/rtc-config.c, startup/bspstart.c, startup/bspstarthooks.c, startup/linkcmds.lpc32xx_phycore: Changes throughout.
Location:
c/src/lib/libbsp/arm/lpc32xx
Files:
16 added
11 edited
2 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc32xx/ChangeLog

    rb18fd86 r3103d4c  
     12010-06-23      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * make/custom/lpc32xx_mzx_boot_int.cfg,
     4        startup/linkcmds.lpc32xx_mzx_boot_int: Removed files.
     5        * include/boot.h, include/emc.h, include/i2c.h, include/nand-mlc.h,
     6        make/custom/lpc32xx_mzx.cfg, make/custom/lpc32xx_mzx_stage_1.cfg,
     7        make/custom/lpc32xx_mzx_stage_2.cfg, misc/boot.c, misc/emc.c,
     8        misc/i2c.c, misc/nand-mlc.c, misc/nand-mlc-read-blocks.c,
     9        misc/nand-mlc-write-blocks.c, misc/restart.c,
     10        startup/linkcmds.lpc32xx, startup/linkcmds.lpc32xx_mzx,
     11        startup/linkcmds.lpc32xx_mzx_stage_1,
     12        startup/linkcmds.lpc32xx_mzx_stage_2: New files.
     13        * configure.ac, Makefile.am, preinstall.am: Reflect changes above.
     14        * include/bsp.h, include/lpc32xx.h, irq/irq.c, rtc/rtc-config.c,
     15        startup/bspstart.c, startup/bspstarthooks.c,
     16        startup/linkcmds.lpc32xx_phycore: Changes throughout.
     17
    1182010-05-25      Sebastian Huber <sebastian.huber@embedded-brains.de>
    219
  • c/src/lib/libbsp/arm/lpc32xx/Makefile.am

    rb18fd86 r3103d4c  
    4545include_bsp_HEADERS += include/lpc-clock-config.h
    4646include_bsp_HEADERS += include/lpc-ethernet-config.h
     47include_bsp_HEADERS += include/nand-mlc.h
     48include_bsp_HEADERS += include/boot.h
     49include_bsp_HEADERS += include/i2c.h
     50include_bsp_HEADERS += include/emc.h
    4751
    4852include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache.h \
     
    6064
    6165project_lib_DATA += startup/linkcmds
     66project_lib_DATA += startup/linkcmds.lpc32xx
    6267project_lib_DATA += ../shared/startup/linkcmds.base
    6368
    6469EXTRA_DIST = startup/linkcmds.lpc32xx_phycore \
    65         startup/linkcmds.lpc32xx_mzx_boot_int
     70        startup/linkcmds.lpc32xx_mzx_stage_1 \
     71        startup/linkcmds.lpc32xx_mzx_stage_2 \
     72        startup/linkcmds.lpc32xx_mzx
    6673
    6774###############################################################################
     
    114121        rtc/rtc-config.c
    115122
    116 # Timer
    117 libbsp_a_SOURCES += misc/timer.c
     123# Misc
     124libbsp_a_SOURCES += misc/timer.c \
     125        misc/nand-mlc.c \
     126        misc/nand-mlc-read-blocks.c \
     127        misc/nand-mlc-write-blocks.c \
     128        misc/restart.c \
     129        misc/boot.c \
     130        misc/emc.c \
     131        misc/i2c.c
    118132
    119133# SSP
  • c/src/lib/libbsp/arm/lpc32xx/configure.ac

    rb18fd86 r3103d4c  
    2222AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
    2323
    24 RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[lpc32xx_mzx_boot_int],[1])
     24RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[lpc32xx_mzx_stage_1],[1])
    2525RTEMS_BSPOPTS_SET([BSP_SMALL_MEMORY],[*],[])
    2626RTEMS_BSPOPTS_HELP([BSP_SMALL_MEMORY],[disable testsuite samples with high memory demands])
     
    4141RTEMS_BSPOPTS_HELP([LPC32XX_PERIPH_CLK],[peripheral clock in Hz])
    4242
     43RTEMS_BSPOPTS_SET([LPC32XX_ETHERNET_RMII],[lpc32xx_mzx*][])
    4344RTEMS_BSPOPTS_SET([LPC32XX_ETHERNET_RMII],[*],[1])
    4445RTEMS_BSPOPTS_HELP([LPC32XX_ETHERNET_RMII],[enable RMII for Ethernet])
     
    6869RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs])
    6970
    70 RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_mzx_boot_int],[1])
    7171RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[*],[])
    7272RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_MMU],[disable MMU])
    7373
     74RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[lpc32xx_mzx*],[1])
    7475RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[*],[])
    7576RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[disable cache for read-write data sections])
    7677
     78RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_ONLY_PROTECTION],[lpc32xx_mzx*],[1])
    7779RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_ONLY_PROTECTION],[*],[])
    7880RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_READ_ONLY_PROTECTION],[disable MMU protection of read-only sections])
  • c/src/lib/libbsp/arm/lpc32xx/include/bsp.h

    rb18fd86 r3103d4c  
    88
    99/*
    10  * Copyright (c) 2009
     10 * Copyright (c) 2009, 2010
    1111 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
     
    3030
    3131#include <bsp/lpc32xx.h>
    32 #include <bsp/lpc-timer.h>
    3332
    3433#ifdef __cplusplus
     
    9291void *lpc32xx_idle(uintptr_t ignored);
    9392
    94 #define LPC32XX_STANDARD_TIMER ((volatile lpc_timer *) LPC32XX_BASE_TIMER_1)
     93#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
    9594
    9695static inline unsigned lpc32xx_timer(void)
     
    101100}
    102101
    103 #define BSP_CONSOLE_UART_BASE 0x40090000
     102static inline void lpc32xx_micro_seconds_delay(unsigned us)
     103{
     104  unsigned start = lpc32xx_timer();
     105  unsigned end = start + us * (LPC32XX_PERIPH_CLK / 1000000);
     106  unsigned now = 0;
     107
     108  do {
     109    now = lpc32xx_timer();
     110  } while (now < end);
     111}
     112
     113void lpc32xx_restart(void *addr);
     114
     115#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
     116
     117/**
     118 * @brief Begin of magic zero area.
     119 *
     120 * A read from this area returns zero.  Writes have no effect.
     121 */
     122extern uint32_t lpc32xx_magic_zero_begin [];
     123
     124/**
     125 * @brief End of magic zero area.
     126 *
     127 * A read from this area returns zero.  Writes have no effect.
     128 */
     129extern uint32_t lpc32xx_magic_zero_end [];
     130
     131/**
     132 * @brief Size of magic zero area.
     133 *
     134 * A read from this area returns zero.  Writes have no effect.
     135 */
     136extern uint32_t lpc32xx_magic_zero_size [];
    104137
    105138/** @} */
  • c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h

    rb18fd86 r3103d4c  
    88
    99/*
    10  * Copyright (c) 2009
     10 * Copyright (c) 2009, 2010
    1111 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
     
    2626
    2727#include <bsp/utility.h>
     28#include <bsp/lpc-timer.h>
    2829
    2930/**
     
    165166#define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8)
    166167#define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4)
    167 #define LPC32XX_POS0_IRAM_CTRl (*(volatile uint32_t *) 0x40004110)
    168 #define LPC32XX_POS1_IRAM_CTRl (*(volatile uint32_t *) 0x40004114)
    169 
    170 /** @} */
    171 
    172 /**
    173  * @name GPIO Registers
    174  *
    175  * @{
    176  */
    177 
    178 #define LPC32XX_P0_INP_STATE (*(volatile uint32_t *) 0x40028040)
    179 #define LPC32XX_P0_OUTP_SET (*(volatile uint32_t *) 0x40028044)
    180 #define LPC32XX_P0_OUTP_CLR (*(volatile uint32_t *) 0x40028048)
    181 #define LPC32XX_P0_DIR_SET (*(volatile uint32_t *) 0x40028050)
    182 #define LPC32XX_P0_DIR_CLR (*(volatile uint32_t *) 0x40028054)
    183 #define LPC32XX_P0_DIR_STATE (*(volatile uint32_t *) 0x40028058)
    184 #define LPC32XX_P0_OUTP_STATE (*(volatile uint32_t *) 0x4002804c)
    185 #define LPC32XX_P1_INP_STATE (*(volatile uint32_t *) 0x40028060)
    186 #define LPC32XX_P1_OUTP_SET (*(volatile uint32_t *) 0x40028064)
    187 #define LPC32XX_P1_OUTP_CLR (*(volatile uint32_t *) 0x40028068)
    188 #define LPC32XX_P1_DIR_SET (*(volatile uint32_t *) 0x40028070)
    189 #define LPC32XX_P1_DIR_CLR (*(volatile uint32_t *) 0x40028074)
    190 #define LPC32XX_P1_DIR_STATE (*(volatile uint32_t *) 0x40028078)
    191 #define LPC32XX_P1_OUTP_STATE (*(volatile uint32_t *) 0x4002806c)
    192 #define LPC32XX_P2_INP_STATE (*(volatile uint32_t *) 0x4002801c)
    193 #define LPC32XX_P2_OUTP_SET (*(volatile uint32_t *) 0x40028020)
    194 #define LPC32XX_P2_OUTP_CLR (*(volatile uint32_t *) 0x40028024)
    195 #define LPC32XX_P2_DIR_SET (*(volatile uint32_t *) 0x40028010)
    196 #define LPC32XX_P2_DIR_CLR (*(volatile uint32_t *) 0x40028014)
    197 #define LPC32XX_P2_DIR_STATE (*(volatile uint32_t *) 0x40028018)
    198 #define LPC32XX_P3_INP_STATE (*(volatile uint32_t *) 0x40028000)
    199 #define LPC32XX_P3_OUTP_SET (*(volatile uint32_t *) 0x40028004)
    200 #define LPC32XX_P3_OUTP_CLR (*(volatile uint32_t *) 0x40028008)
    201 #define LPC32XX_P3_OUTP_STATE (*(volatile uint32_t *) 0x4002800c)
     168#define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110)
     169#define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114)
     170#define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068)
    202171
    203172/** @} */
     
    251220/** @} */
    252221
     222#define LPC32XX_RESERVED(a, b, s) (((b) - (a) - sizeof(s)) / 4)
     223
     224typedef struct {
     225} lpc32xx_nand_slc;
     226
     227typedef struct {
     228} lpc32xx_ssp;
     229
     230typedef struct {
     231} lpc32xx_spi;
     232
     233typedef struct {
     234} lpc32xx_i2s;
     235
     236typedef struct {
     237} lpc32xx_sd_card;
     238
     239typedef struct {
     240} lpc32xx_dma;
     241
     242typedef struct {
     243} lpc32xx_usb;
     244
     245typedef struct {
     246} lpc32xx_lcd;
     247
     248typedef struct {
     249} lpc32xx_etb;
     250
     251typedef struct {
     252} lpc32xx_syscon;
     253
     254typedef struct {
     255} lpc32xx_uart_ctrl;
     256
     257typedef struct {
     258} lpc32xx_uart;
     259
     260typedef struct {
     261} lpc32xx_ms_timer;
     262
     263typedef struct {
     264} lpc32xx_hs_timer;
     265
     266typedef struct {
     267} lpc32xx_wdg_timer;
     268
     269typedef struct {
     270} lpc32xx_debug;
     271
     272typedef struct {
     273} lpc32xx_adc;
     274
     275typedef struct {
     276} lpc32xx_keyscan;
     277
     278typedef struct {
     279} lpc32xx_pwm;
     280
     281typedef struct {
     282} lpc32xx_mcpwm;
     283
     284typedef struct {
     285} lpc32xx_eth;
     286
     287typedef struct {
     288  uint32_t er;
     289  uint32_t rsr;
     290  uint32_t sr;
     291  uint32_t apr;
     292  uint32_t atr;
     293  uint32_t itr;
     294} lpc32xx_irq;
     295
     296typedef struct {
     297  uint32_t p3_inp_state;
     298  uint32_t p3_outp_set;
     299  uint32_t p3_outp_clr;
     300  uint32_t p3_outp_state;
     301  uint32_t p2_dir_set;
     302  uint32_t p2_dir_clr;
     303  uint32_t p2_dir_state;
     304  uint32_t p2_inp_state;
     305  uint32_t p2_outp_set;
     306  uint32_t p2_outp_clr;
     307  uint32_t reserved_0 [6];
     308  uint32_t p0_inp_state;
     309  uint32_t p0_outp_set;
     310  uint32_t p0_outp_clr;
     311  uint32_t p0_outp_state;
     312  uint32_t p0_dir_set;
     313  uint32_t p0_dir_clr;
     314  uint32_t p0_dir_state;
     315  uint32_t reserved_1 [1];
     316  uint32_t p1_inp_state;
     317  uint32_t p1_outp_set;
     318  uint32_t p1_outp_clr;
     319  uint32_t p1_outp_state;
     320  uint32_t p1_dir_set;
     321  uint32_t p1_dir_clr;
     322  uint32_t p1_dir_state;
     323} lpc32xx_gpio;
     324
     325typedef struct {
     326  uint32_t rx_or_tx;
     327  uint32_t stat;
     328  uint32_t ctrl;
     329  uint32_t clk_hi;
     330  uint32_t clk_lo;
     331  uint32_t adr;
     332  uint32_t rxfl;
     333  uint32_t txfl;
     334  uint32_t rxb;
     335  uint32_t txb;
     336  uint32_t s_tx;
     337  uint32_t s_txfl;
     338} lpc32xx_i2c;
     339
     340typedef struct {
     341  uint32_t ucount;
     342  uint32_t dcount;
     343  uint32_t match0;
     344  uint32_t match1;
     345  uint32_t ctrl;
     346  uint32_t intstat;
     347  uint32_t key;
     348  uint32_t sram [32];
     349} lpc32xx_rtc;
     350
     351#define EMC_DYN_CHIP_COUNT 2
     352
     353#define EMC_STATIC_CHIP_COUNT 4
     354
     355typedef struct {
     356  uint32_t config;
     357  uint32_t rascas;
     358  uint32_t reserved_0 [6];
     359} lpc32xx_emc_dynamic;
     360
     361typedef struct {
     362  uint32_t config;
     363  uint32_t waitwen;
     364  uint32_t waitoen;
     365  uint32_t waitrd;
     366  uint32_t waitpage;
     367  uint32_t waitwr;
     368  uint32_t waitturn;
     369  uint32_t reserved_0 [1];
     370} lpc32xx_emc_static;
     371
     372typedef struct {
     373  uint32_t control;
     374  uint32_t status;
     375  uint32_t timeout;
     376  uint32_t reserved_0 [5];
     377} lpc32xx_emc_ahb;
     378
     379typedef struct {
     380  uint32_t control;
     381  uint32_t status;
     382  uint32_t config;
     383  uint32_t reserved_0 [5];
     384  uint32_t dynamiccontrol;
     385  uint32_t dynamicrefresh;
     386  uint32_t dynamicreadconfig;
     387  uint32_t reserved_1;
     388  uint32_t dynamictrp;
     389  uint32_t dynamictras;
     390  uint32_t dynamictsrex;
     391  uint32_t reserved_2 [2];
     392  uint32_t dynamictwr;
     393  uint32_t dynamictrc;
     394  uint32_t dynamictrfc;
     395  uint32_t dynamictxsr;
     396  uint32_t dynamictrrd;
     397  uint32_t dynamictmrd;
     398  uint32_t dynamictcdlr;
     399  uint32_t reserved_3 [8];
     400  uint32_t staticextendedwait;
     401  uint32_t reserved_4 [31];
     402  lpc32xx_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
     403  uint32_t reserved_5 [48];
     404  lpc32xx_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
     405  uint32_t reserved_6 [96];
     406  lpc32xx_emc_ahb ahb [5];
     407} lpc32xx_emc;
     408
     409typedef struct {
     410  union {
     411    uint32_t w32;
     412    uint16_t w16;
     413    uint8_t w8;
     414  } buff;
     415  uint32_t reserved_0 [8191];
     416  union {
     417    uint32_t w32;
     418    uint16_t w16;
     419    uint8_t w8;
     420  } data;
     421  uint32_t reserved_1 [8191];
     422  uint32_t cmd;
     423  uint32_t addr;
     424  uint32_t ecc_enc;
     425  uint32_t ecc_dec;
     426  uint32_t ecc_auto_enc;
     427  uint32_t ecc_auto_dec;
     428  uint32_t rpr;
     429  uint32_t wpr;
     430  uint32_t rubp;
     431  uint32_t robp;
     432  uint32_t sw_wp_add_low;
     433  uint32_t sw_wp_add_hig;
     434  uint32_t icr;
     435  uint32_t time;
     436  uint32_t irq_mr;
     437  uint32_t irq_sr;
     438  uint32_t lock_pr;
     439  uint32_t isr;
     440  uint32_t ceh;
     441} lpc32xx_nand_mlc;
     442
     443typedef struct {
     444  lpc32xx_nand_slc nand_slc;
     445  uint32_t reserved_0 [LPC32XX_RESERVED(0x20020000, 0x20084000, lpc32xx_nand_slc)];
     446  lpc32xx_ssp ssp_0;
     447  uint32_t reserved_1 [LPC32XX_RESERVED(0x20084000, 0x20088000, lpc32xx_ssp)];
     448  lpc32xx_spi spi_1;
     449  uint32_t reserved_2 [LPC32XX_RESERVED(0x20088000, 0x2008c000, lpc32xx_spi)];
     450  lpc32xx_ssp ssp_1;
     451  uint32_t reserved_3 [LPC32XX_RESERVED(0x2008c000, 0x20090000, lpc32xx_ssp)];
     452  lpc32xx_spi spi_2;
     453  uint32_t reserved_4 [LPC32XX_RESERVED(0x20090000, 0x20094000, lpc32xx_spi)];
     454  lpc32xx_i2s i2s_0;
     455  uint32_t reserved_5 [LPC32XX_RESERVED(0x20094000, 0x20098000, lpc32xx_i2s)];
     456  lpc32xx_sd_card sd_card;
     457  uint32_t reserved_6 [LPC32XX_RESERVED(0x20098000, 0x2009c000, lpc32xx_sd_card)];
     458  lpc32xx_i2s i2s_1;
     459  uint32_t reserved_7 [LPC32XX_RESERVED(0x2009c000, 0x200a8000, lpc32xx_i2s)];
     460  lpc32xx_nand_mlc nand_mlc;
     461  uint32_t reserved_8 [LPC32XX_RESERVED(0x200a8000, 0x31000000, lpc32xx_nand_mlc)];
     462  lpc32xx_dma dma;
     463  uint32_t reserved_9 [LPC32XX_RESERVED(0x31000000, 0x31020000, lpc32xx_dma)];
     464  lpc32xx_usb usb;
     465  uint32_t reserved_10 [LPC32XX_RESERVED(0x31020000, 0x31040000, lpc32xx_usb)];
     466  lpc32xx_lcd lcd;
     467  uint32_t reserved_11 [LPC32XX_RESERVED(0x31040000, 0x31060000, lpc32xx_lcd)];
     468  lpc32xx_eth eth;
     469  uint32_t reserved_12 [LPC32XX_RESERVED(0x31060000, 0x31080000, lpc32xx_eth)];
     470  lpc32xx_emc emc;
     471  uint32_t reserved_13 [LPC32XX_RESERVED(0x31080000, 0x310c0000, lpc32xx_emc)];
     472  lpc32xx_etb etb;
     473  uint32_t reserved_14 [LPC32XX_RESERVED(0x310c0000, 0x40004000, lpc32xx_etb)];
     474  lpc32xx_syscon syscon;
     475  uint32_t reserved_15 [LPC32XX_RESERVED(0x40004000, 0x40008000, lpc32xx_syscon)];
     476  lpc32xx_irq mic;
     477  uint32_t reserved_16 [LPC32XX_RESERVED(0x40008000, 0x4000c000, lpc32xx_irq)];
     478  lpc32xx_irq sic_1;
     479  uint32_t reserved_17 [LPC32XX_RESERVED(0x4000c000, 0x40010000, lpc32xx_irq)];
     480  lpc32xx_irq sic_2;
     481  uint32_t reserved_18 [LPC32XX_RESERVED(0x40010000, 0x40014000, lpc32xx_irq)];
     482  lpc32xx_uart uart_1;
     483  uint32_t reserved_19 [LPC32XX_RESERVED(0x40014000, 0x40018000, lpc32xx_uart)];
     484  lpc32xx_uart uart_2;
     485  uint32_t reserved_20 [LPC32XX_RESERVED(0x40018000, 0x4001c000, lpc32xx_uart)];
     486  lpc32xx_uart uart_7;
     487  uint32_t reserved_21 [LPC32XX_RESERVED(0x4001c000, 0x40024000, lpc32xx_uart)];
     488  lpc32xx_rtc rtc;
     489  uint32_t reserved_22 [LPC32XX_RESERVED(0x40024000, 0x40028000, lpc32xx_rtc)];
     490  lpc32xx_gpio gpio;
     491  uint32_t reserved_23 [LPC32XX_RESERVED(0x40028000, 0x4002c000, lpc32xx_gpio)];
     492  lpc_timer timer_4;
     493  uint32_t reserved_24 [LPC32XX_RESERVED(0x4002c000, 0x40030000, lpc_timer)];
     494  lpc_timer timer_5;
     495  uint32_t reserved_25 [LPC32XX_RESERVED(0x40030000, 0x40034000, lpc_timer)];
     496  lpc32xx_ms_timer ms_timer;
     497  uint32_t reserved_26 [LPC32XX_RESERVED(0x40034000, 0x40038000, lpc32xx_ms_timer)];
     498  lpc32xx_hs_timer hs_timer;
     499  uint32_t reserved_27 [LPC32XX_RESERVED(0x40038000, 0x4003c000, lpc32xx_hs_timer)];
     500  lpc32xx_wdg_timer wdg_timer;
     501  uint32_t reserved_28 [LPC32XX_RESERVED(0x4003c000, 0x40040000, lpc32xx_wdg_timer)];
     502  lpc32xx_debug debug;
     503  uint32_t reserved_29 [LPC32XX_RESERVED(0x40040000, 0x40044000, lpc32xx_debug)];
     504  lpc_timer timer_0;
     505  uint32_t reserved_30 [LPC32XX_RESERVED(0x40044000, 0x40048000, lpc_timer)];
     506  lpc32xx_adc adc;
     507  uint32_t reserved_31 [LPC32XX_RESERVED(0x40048000, 0x4004c000, lpc32xx_adc)];
     508  lpc_timer timer_1;
     509  uint32_t reserved_32 [LPC32XX_RESERVED(0x4004c000, 0x40050000, lpc_timer)];
     510  lpc32xx_keyscan keyscan;
     511  uint32_t reserved_33 [LPC32XX_RESERVED(0x40050000, 0x40054000, lpc32xx_keyscan)];
     512  lpc32xx_uart_ctrl uart_ctrl;
     513  uint32_t reserved_34 [LPC32XX_RESERVED(0x40054000, 0x40058000, lpc32xx_uart_ctrl)];
     514  lpc_timer timer_2;
     515  uint32_t reserved_35 [LPC32XX_RESERVED(0x40058000, 0x4005c000, lpc_timer)];
     516  lpc32xx_pwm pwm_1_and_pwm_2;
     517  uint32_t reserved_36 [LPC32XX_RESERVED(0x4005c000, 0x40060000, lpc32xx_pwm)];
     518  lpc_timer timer3;
     519  uint32_t reserved_37 [LPC32XX_RESERVED(0x40060000, 0x40080000, lpc_timer)];
     520  lpc32xx_uart uart_3;
     521  uint32_t reserved_38 [LPC32XX_RESERVED(0x40080000, 0x40088000, lpc32xx_uart)];
     522  lpc32xx_uart uart_4;
     523  uint32_t reserved_39 [LPC32XX_RESERVED(0x40088000, 0x40090000, lpc32xx_uart)];
     524  lpc32xx_uart uart_5;
     525  uint32_t reserved_40 [LPC32XX_RESERVED(0x40090000, 0x40098000, lpc32xx_uart)];
     526  lpc32xx_uart uart_6;
     527  uint32_t reserved_41 [LPC32XX_RESERVED(0x40098000, 0x400a0000, lpc32xx_uart)];
     528  lpc32xx_i2c i2c_1;
     529  uint32_t reserved_42 [LPC32XX_RESERVED(0x400a0000, 0x400a8000, lpc32xx_i2c)];
     530  lpc32xx_i2c i2c_2;
     531  uint32_t reserved_43 [LPC32XX_RESERVED(0x400a8000, 0x400e8000, lpc32xx_i2c)];
     532  lpc32xx_mcpwm mcpwm;
     533} lpc32xx_registers;
     534
     535extern volatile lpc32xx_registers lpc32xx;
     536
    253537/** @} */
    254538
  • c/src/lib/libbsp/arm/lpc32xx/irq/irq.c

    rb18fd86 r3103d4c  
    4343} lpc32xx_irq_fields;
    4444
    45 typedef struct {
    46   uint32_t er;
    47   uint32_t rsr;
    48   uint32_t sr;
    49   uint32_t apr;
    50   uint32_t atr;
    51   uint32_t itr;
    52 } lpc32xx_irq_controller;
    53 
    54 static volatile lpc32xx_irq_controller *const lpc32xx_mic = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_MIC;
    55 
    56 static volatile lpc32xx_irq_controller *const lpc32xx_sic_1 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_1;
    57 
    58 static volatile lpc32xx_irq_controller *const lpc32xx_sic_2 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_2;
    59 
    6045static uint8_t lpc32xx_irq_priority_table [LPC32XX_IRQ_COUNT];
    6146
     
    8166  LPC32XX_IRQ_BIT_OPS_DEFINE; \
    8267  unsigned module_offset = module << 14; \
    83   volatile uint32_t *reg = \
    84     (volatile uint32_t *) (LPC32XX_BASE_MIC + module_offset + register_offset)
     68  volatile uint32_t *reg = (volatile uint32_t *) \
     69    ((volatile char *) &lpc32xx.mic + module_offset + register_offset)
    8570
    8671#define LPC32XX_IRQ_OFFSET_ER 0U
     
    235220void bsp_interrupt_dispatch(void)
    236221{
    237   uint32_t status = lpc32xx_mic->sr & LPC32XX_MIC_STATUS_MASK;
    238   uint32_t er_mic = lpc32xx_mic->er;
    239   uint32_t er_sic_1 = lpc32xx_sic_1->er;
    240   uint32_t er_sic_2 = lpc32xx_sic_2->er;
     222  uint32_t status = lpc32xx.mic.sr & LPC32XX_MIC_STATUS_MASK;
     223  uint32_t er_mic = lpc32xx.mic.er;
     224  uint32_t er_sic_1 = lpc32xx.sic_1.er;
     225  uint32_t er_sic_2 = lpc32xx.sic_2.er;
    241226  uint32_t psr = 0;
    242227  lpc32xx_irq_fields *masks = NULL;
     
    247232    vector = lpc32xx_irq_get_index(status);
    248233  } else {
    249     status = lpc32xx_sic_1->sr;
     234    status = lpc32xx.sic_1.sr;
    250235    if (status != 0) {
    251236      vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_1;
    252237    } else {
    253       status = lpc32xx_sic_2->sr;
     238      status = lpc32xx.sic_2.sr;
    254239      if (status != 0) {
    255240        vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_2;
     
    264249  masks = &lpc32xx_irq_priority_masks [priority];
    265250
    266   lpc32xx_mic->er = er_mic & masks->field.mic;
    267   lpc32xx_sic_1->er = er_sic_1 & masks->field.sic_1;
    268   lpc32xx_sic_2->er = er_sic_2 & masks->field.sic_2;
     251  lpc32xx.mic.er = er_mic & masks->field.mic;
     252  lpc32xx.sic_1.er = er_sic_1 & masks->field.sic_1;
     253  lpc32xx.sic_2.er = er_sic_2 & masks->field.sic_2;
    269254
    270255  psr = arm_status_irq_enable();
     
    274259  arm_status_restore(psr);
    275260
    276   lpc32xx_mic->er = er_mic & lpc32xx_irq_enable.field.mic;
    277   lpc32xx_sic_1->er = er_sic_1 & lpc32xx_irq_enable.field.sic_1;
    278   lpc32xx_sic_2->er = er_sic_2 & lpc32xx_irq_enable.field.sic_2;
     261  lpc32xx.mic.er = er_mic & lpc32xx_irq_enable.field.mic;
     262  lpc32xx.sic_1.er = er_sic_1 & lpc32xx_irq_enable.field.sic_1;
     263  lpc32xx.sic_2.er = er_sic_2 & lpc32xx_irq_enable.field.sic_2;
    279264}
    280265
     
    309294{
    310295  if ((unsigned) exception < MAX_EXCEPTIONS) {
    311     #ifndef LPC32XX_DISABLE_MMU
    312       uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS;
    313     #else
    314       uint32_t *table = (uint32_t *) bsp_section_start_begin + MAX_EXCEPTIONS;
    315     #endif
     296    uint32_t *table = (uint32_t *) bsp_vector_table_begin + MAX_EXCEPTIONS;
    316297
    317298    table [exception] = (uint32_t) handler;
     
    342323  lpc32xx_irq_enable.field.sic_1 = 0x0;
    343324  lpc32xx_irq_enable.field.mic = 0xc0000003;
    344   lpc32xx_sic_1->er = 0x0;
    345   lpc32xx_sic_2->er = 0x0;
    346   lpc32xx_mic->er = 0xc0000003;
     325  lpc32xx.sic_1.er = 0x0;
     326  lpc32xx.sic_2.er = 0x0;
     327  lpc32xx.mic.er = 0xc0000003;
    347328
    348329  /* Set interrupt types to IRQ */
    349   lpc32xx_mic->itr = 0x0;
    350   lpc32xx_sic_1->itr = 0x0;
    351   lpc32xx_sic_2->itr = 0x0;
     330  lpc32xx.mic.itr = 0x0;
     331  lpc32xx.sic_1.itr = 0x0;
     332  lpc32xx.sic_2.itr = 0x0;
    352333
    353334  /* Set interrupt activation polarities */
    354   lpc32xx_mic->apr = 0x3ff0efe0;
    355   lpc32xx_sic_1->apr = 0xfbd27184;
    356   lpc32xx_sic_2->apr = 0x801810c0;
     335  lpc32xx.mic.apr = 0x3ff0efe0;
     336  lpc32xx.sic_1.apr = 0xfbd27184;
     337  lpc32xx.sic_2.apr = 0x801810c0;
    357338
    358339  /* Set interrupt activation types */
    359   lpc32xx_mic->atr = 0x0;
    360   lpc32xx_sic_1->atr = 0x26000;
    361   lpc32xx_sic_2->atr = 0x0;
     340  lpc32xx.mic.atr = 0x0;
     341  lpc32xx.sic_1.atr = 0x26000;
     342  lpc32xx.sic_2.atr = 0x0;
    362343
    363344  lpc32xx_set_exception_handler(ARM_EXCEPTION_IRQ, arm_exc_interrupt);
  • c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx.cfg

    rb18fd86 r3103d4c  
    11#
    2 #  Config file for boot loader.
     2#  Config file for MZX application.
    33#
    44#  $Id$
  • c/src/lib/libbsp/arm/lpc32xx/preinstall.am

    rb18fd86 r3103d4c  
    123123PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
    124124
     125$(PROJECT_INCLUDE)/bsp/nand-mlc.h: include/nand-mlc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     126        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/nand-mlc.h
     127PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/nand-mlc.h
     128
     129$(PROJECT_INCLUDE)/bsp/boot.h: include/boot.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     130        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/boot.h
     131PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/boot.h
     132
     133$(PROJECT_INCLUDE)/bsp/i2c.h: include/i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     134        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2c.h
     135PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h
     136
     137$(PROJECT_INCLUDE)/bsp/emc.h: include/emc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     138        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/emc.h
     139PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/emc.h
     140
    125141$(PROJECT_INCLUDE)/libcpu/cache.h: ../../../libcpu/arm/shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    126142        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h
     
    139155TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
    140156
     157$(PROJECT_LIB)/linkcmds.lpc32xx: startup/linkcmds.lpc32xx $(PROJECT_LIB)/$(dirstamp)
     158        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc32xx
     159TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc32xx
     160
    141161$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
    142162        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
  • c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c

    rb18fd86 r3103d4c  
    3939#define LPC32XX_RTC_CTRL_MATCH_0_INTR (1U << 0)
    4040
    41 typedef struct {
    42   uint32_t ucount;
    43   uint32_t dcount;
    44   uint32_t match0;
    45   uint32_t match1;
    46   uint32_t ctrl;
    47   uint32_t intstat;
    48   uint32_t key;
    49   uint32_t sram [32];
    50 } lpc32xx_rtc_registers;
    51 
    52 static volatile lpc32xx_rtc_registers *const lpc32xx_rtc =
    53   (volatile lpc32xx_rtc_registers *) LPC32XX_BASE_RTC;
    54 
    5541static void lpc32xx_rtc_set(uint32_t val)
    5642{
    5743  unsigned i = LPC32XX_ARM_CLK / LPC32XX_OSCILLATOR_RTC;
    5844
    59   lpc32xx_rtc->ctrl |= LPC32XX_RTC_CTRL_STOP;
    60   lpc32xx_rtc->ucount = val;
    61   lpc32xx_rtc->dcount = LPC32XX_RTC_COUNTER_DELTA - val;
    62   lpc32xx_rtc->ctrl &= ~LPC32XX_RTC_CTRL_STOP;
     45  lpc32xx.rtc.ctrl |= LPC32XX_RTC_CTRL_STOP;
     46  lpc32xx.rtc.ucount = val;
     47  lpc32xx.rtc.dcount = LPC32XX_RTC_COUNTER_DELTA - val;
     48  lpc32xx.rtc.ctrl &= ~LPC32XX_RTC_CTRL_STOP;
    6349
    6450  /* It needs some time before we can read the values back */
     
    7157static void lpc32xx_rtc_reset(void)
    7258{
    73   lpc32xx_rtc->ctrl = LPC32XX_RTC_CTRL_RESET;
    74   lpc32xx_rtc->ctrl = 0;
    75   lpc32xx_rtc->key = LPC32XX_RTC_KEY;
     59  lpc32xx.rtc.ctrl = LPC32XX_RTC_CTRL_RESET;
     60  lpc32xx.rtc.ctrl = 0;
     61  lpc32xx.rtc.key = LPC32XX_RTC_KEY;
    7662  lpc32xx_rtc_set(0);
    7763}
     
    8470  uint32_t down_second = 0;
    8571
    86   if (lpc32xx_rtc->key != LPC32XX_RTC_KEY) {
     72  if (lpc32xx.rtc.key != LPC32XX_RTC_KEY) {
    8773    lpc32xx_rtc_reset();
    8874  }
    8975
    9076  do {
    91     up_first = lpc32xx_rtc->ucount;
    92     down_first = lpc32xx_rtc->dcount;
    93     up_second = lpc32xx_rtc->ucount;
    94     down_second = lpc32xx_rtc->dcount;
     77    up_first = lpc32xx.rtc.ucount;
     78    down_first = lpc32xx.rtc.dcount;
     79    up_second = lpc32xx.rtc.ucount;
     80    down_second = lpc32xx.rtc.dcount;
    9581  } while (up_first != up_second || down_first != down_second);
    9682
     
    10389{
    10490  struct timeval now = {
    105     .tv_sec = lpc32xx_rtc->ucount,
     91    .tv_sec = lpc32xx.rtc.ucount,
    10692    .tv_usec = 0
    10793  };
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c

    rb18fd86 r3103d4c  
    2828#include <bsp/lpc32xx.h>
    2929
    30 static void lpc32xx_timer_initialize(void)
    31 {
    32   volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
    33 
    34   LPC32XX_TIMCLK_CTRL1 = (1U << 2) | (1U << 3);
    35 
    36   timer->tcr = LPC_TIMER_TCR_RST;
    37   timer->ctcr = 0x0;
    38   timer->pr = 0x0;
    39   timer->ir = 0xff;
    40   timer->mcr = 0x0;
    41   timer->ccr = 0x0;
    42   timer->tcr = LPC_TIMER_TCR_EN;
    43 }
    44 
    4530void bsp_start(void)
    4631{
     
    5338    (uintptr_t) bsp_section_stack_size
    5439  );
    55 
    56   lpc32xx_timer_initialize();
    5740}
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c

    rb18fd86 r3103d4c  
    4343#endif
    4444
    45 static void BSP_START_SECTION lpc32xx_clear_bss(void)
     45LINKER_SYMBOL(lpc32xx_translation_table_base);
     46
     47static void BSP_START_SECTION clear_bss(void)
    4648{
    4749  const int *end = (const int *) bsp_section_bss_end;
     
    116118      .end = 0x40100000U,
    117119      .flags = LPC32XX_MMU_READ_WRITE
     120    }, {
     121      .begin = (uint32_t) lpc32xx_magic_zero_begin,
     122      .end = (uint32_t) lpc32xx_magic_zero_end,
     123      .flags = LPC32XX_MMU_READ_WRITE_DATA
    118124    }
    119125  };
    120126
    121   static void BSP_START_SECTION lpc32xx_mmu_set_entries(
     127  static void BSP_START_SECTION set_translation_table_entries(
    122128    uint32_t *ttb,
    123129    const lpc32xx_mmu_config *config
     
    137143
    138144  static void BSP_START_SECTION
    139     lpc32xx_setup_translation_table_and_enable_mmu(uint32_t ctrl)
     145    setup_translation_table_and_enable_mmu(uint32_t ctrl)
    140146  {
    141147    uint32_t const dac =
    142148      ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
    143     uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
     149    uint32_t *const ttb = (uint32_t *) lpc32xx_translation_table_base;
    144150    size_t const config_entry_count =
    145151      sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
     
    155161
    156162    for (i = 0; i < config_entry_count; ++i) {
    157       lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
     163      set_translation_table_entries(ttb, &lpc32xx_mmu_config_table [i]);
    158164    }
    159165
     
    164170#endif
    165171
    166 static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
     172static void BSP_START_SECTION setup_mmu_and_cache(void)
    167173{
    168174  uint32_t ctrl = 0;
     
    179185
    180186  #ifndef LPC32XX_DISABLE_MMU
    181     lpc32xx_setup_translation_table_and_enable_mmu(ctrl);
     187    setup_translation_table_and_enable_mmu(ctrl);
    182188  #endif
    183189}
     
    187193#endif
    188194
    189 static void BSP_START_SECTION lpc32xx_pll_setup(void)
     195static void BSP_START_SECTION setup_pll(void)
    190196{
    191197  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
     
    208214void BSP_START_SECTION bsp_start_hook_0(void)
    209215{
    210   lpc32xx_pll_setup();
    211   lpc32xx_mmu_and_cache_setup();
    212 }
    213 
    214 static void BSP_START_SECTION bsp_start_config_uarts(void)
     216  setup_pll();
     217  setup_mmu_and_cache();
     218}
     219
     220static void BSP_START_SECTION setup_uarts(void)
    215221{
    216222  uint32_t uartclk_ctrl = 0;
     
    247253}
    248254
     255static void BSP_START_SECTION setup_timer(void)
     256{
     257  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
     258
     259  LPC32XX_TIMCLK_CTRL1 = (1U << 2) | (1U << 3);
     260
     261  timer->tcr = LPC_TIMER_TCR_RST;
     262  timer->ctcr = 0x0;
     263  timer->pr = 0x0;
     264  timer->ir = 0xff;
     265  timer->mcr = 0x0;
     266  timer->ccr = 0x0;
     267  timer->tcr = LPC_TIMER_TCR_EN;
     268}
     269
    249270void BSP_START_SECTION bsp_start_hook_1(void)
    250271{
    251   bsp_start_config_uarts();
     272  setup_uarts();
     273  setup_timer();
    252274
    253275  /* Copy .text section */
     
    284306
    285307  /* Clear .bss section */
    286   lpc32xx_clear_bss();
     308  clear_bss();
    287309
    288310  /* At this point we can use objects outside the .start section */
  • c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_stage_1

    rb18fd86 r3103d4c  
    22 * @file
    33 *
    4  * @ingroup lpc32xx_linker_boot
     4 * @ingroup lpc32xx_linker_mzx_stage_1
    55 *
    66 * @brief Memory map.
     
    88
    99/**
    10  * @defgroup lpc32xx_linker_boot Boot Memory Map
     10 * @defgroup lpc32xx_linker_mzx_stage_1 MZX Stage-1 Program Memory Map
    1111 *
    1212 * @ingroup bsp_linker
    1313 *
    14  * @brief Boot memory map.
     14 * @brief MZX stage-1 program memory map.
    1515 *
    1616 * <table>
    1717 *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
    18  *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
     18 *   <tr><td>RAM_INT</td><td>0x08000000</td><td>232k</td></tr>
     19 *   <tr><td>RAM_MMU</td><td>0x0803a000</td><td>16k</td></tr>
     20 *   <tr><td>RAM_VEC</td><td>0x0803d000</td><td>8k</td></tr>
    1921 * </table>
    2022 *
     
    3436
    3537MEMORY {
    36         RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k
     38        RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 232k
     39        RAM_VEC (AIW) : ORIGIN = 0x0803a000, LENGTH = 8k
     40        RAM_MMU (AIW) : ORIGIN = 0x0803c000, LENGTH = 16k
    3741        NIRVANA : ORIGIN = 0, LENGTH = 0
    3842}
    3943
    4044REGION_ALIAS ("REGION_START", RAM_INT);
    41 REGION_ALIAS ("REGION_VECTOR", RAM_INT);
     45REGION_ALIAS ("REGION_VECTOR", RAM_VEC);
    4246REGION_ALIAS ("REGION_TEXT", RAM_INT);
    4347REGION_ALIAS ("REGION_TEXT_LOAD", RAM_INT);
     
    5256REGION_ALIAS ("REGION_STACK", RAM_INT);
    5357
    54 bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
    55 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
     58bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 7296;
    5659
    57 INCLUDE linkcmds.base
     60bsp_vector_table_in_start_section = 1;
     61
     62INCLUDE linkcmds.lpc32xx
  • c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore

    rb18fd86 r3103d4c  
    1717 *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
    1818 *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
    19  *   <tr><td>RAM_EXT</td><td>0x80000000</td><td>64M</td></tr>
     19 *   <tr><td>RAM_MMU</td><td>0x80000000</td><td>16k</td></tr>
     20 *   <tr><td>RAM_EXT</td><td>0x80004000</td><td>64M - 16k</td></tr>
    2021 *   <tr><td>ROM_EXT</td><td>0xe0000000</td><td>2M</td></tr>
    2122 * </table>
     
    3738MEMORY {
    3839        RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k
    39         RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 64M - 16k /* SDRAM on DYCS0 */
     40        RAM_MMU (AIW) : ORIGIN = 0x80000000, LENGTH = 16k /* SDRAM on DYCS0 */
     41        RAM_EXT (AIW) : ORIGIN = 0x80004000, LENGTH = 64M - 16k /* SDRAM on DYCS0 */
    4042        ROM_EXT (RX) : ORIGIN = 0xe0000000, LENGTH = 2M /* NOR flash on CS0 */
    4143        NIRVANA : ORIGIN = 0, LENGTH = 0
     
    6163bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1M;
    6264
    63 INCLUDE linkcmds.base
     65INCLUDE linkcmds.lpc32xx
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