Changeset 30b1016 in rtems


Ignore:
Timestamp:
Mar 30, 2004, 11:49:33 AM (16 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
ddeb7693
Parents:
c346f33d
Message:

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, rtems/powerpc/registers.h: Convert to using c99 fixed size types.
Location:
cpukit/score/cpu/powerpc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/ChangeLog

    rc346f33d r30b1016  
     12004-03-30      Ralf Corsepius <ralf_corsepius@rtems.org>
     2
     3        * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h,
     4        rtems/powerpc/registers.h: Convert to using c99 fixed size types.
     5
    162004-03-29      Ralf Corsepius <ralf_corsepius@rtems.org>
    27
  • cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h

    rc346f33d r30b1016  
    311311
    312312typedef struct {
    313     unsigned32 gpr1;    /* Stack pointer for all */
    314     unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
    315     unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
    316     unsigned32 gpr14;   /* Non volatile for all */
    317     unsigned32 gpr15;   /* Non volatile for all */
    318     unsigned32 gpr16;   /* Non volatile for all */
    319     unsigned32 gpr17;   /* Non volatile for all */
    320     unsigned32 gpr18;   /* Non volatile for all */
    321     unsigned32 gpr19;   /* Non volatile for all */
    322     unsigned32 gpr20;   /* Non volatile for all */
    323     unsigned32 gpr21;   /* Non volatile for all */
    324     unsigned32 gpr22;   /* Non volatile for all */
    325     unsigned32 gpr23;   /* Non volatile for all */
    326     unsigned32 gpr24;   /* Non volatile for all */
    327     unsigned32 gpr25;   /* Non volatile for all */
    328     unsigned32 gpr26;   /* Non volatile for all */
    329     unsigned32 gpr27;   /* Non volatile for all */
    330     unsigned32 gpr28;   /* Non volatile for all */
    331     unsigned32 gpr29;   /* Non volatile for all */
    332     unsigned32 gpr30;   /* Non volatile for all */
    333     unsigned32 gpr31;   /* Non volatile for all */
    334     unsigned32 cr;      /* PART of the CR is non volatile for all */
    335     unsigned32 pc;      /* Program counter/Link register */
    336     unsigned32 msr;     /* Initial interrupt level */
     313    uint32_t  gpr1;    /* Stack pointer for all */
     314    uint32_t  gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
     315    uint32_t  gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
     316    uint32_t  gpr14;   /* Non volatile for all */
     317    uint32_t  gpr15;   /* Non volatile for all */
     318    uint32_t  gpr16;   /* Non volatile for all */
     319    uint32_t  gpr17;   /* Non volatile for all */
     320    uint32_t  gpr18;   /* Non volatile for all */
     321    uint32_t  gpr19;   /* Non volatile for all */
     322    uint32_t  gpr20;   /* Non volatile for all */
     323    uint32_t  gpr21;   /* Non volatile for all */
     324    uint32_t  gpr22;   /* Non volatile for all */
     325    uint32_t  gpr23;   /* Non volatile for all */
     326    uint32_t  gpr24;   /* Non volatile for all */
     327    uint32_t  gpr25;   /* Non volatile for all */
     328    uint32_t  gpr26;   /* Non volatile for all */
     329    uint32_t  gpr27;   /* Non volatile for all */
     330    uint32_t  gpr28;   /* Non volatile for all */
     331    uint32_t  gpr29;   /* Non volatile for all */
     332    uint32_t  gpr30;   /* Non volatile for all */
     333    uint32_t  gpr31;   /* Non volatile for all */
     334    uint32_t  cr;      /* PART of the CR is non volatile for all */
     335    uint32_t  pc;      /* Program counter/Link register */
     336    uint32_t  msr;     /* Initial interrupt level */
    337337} Context_Control;
    338338
     
    354354
    355355typedef struct CPU_Interrupt_frame {
    356     unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
    357     unsigned32 calleeLr;        /* link register used by callees: SVR4/EABI */
     356    uint32_t  stacklink;       /* Ensure this is a real frame (also reg1 save) */
     357    uint32_t  calleeLr;        /* link register used by callees: SVR4/EABI */
    358358  /* This is what is left out of the primary contexts */
    359     unsigned32 gpr0;
    360     unsigned32 gpr2;            /* play safe */
    361     unsigned32 gpr3;
    362     unsigned32 gpr4;
    363     unsigned32 gpr5;
    364     unsigned32 gpr6;
    365     unsigned32 gpr7;
    366     unsigned32 gpr8;
    367     unsigned32 gpr9;
    368     unsigned32 gpr10;
    369     unsigned32 gpr11;
    370     unsigned32 gpr12;
    371     unsigned32 gpr13;   /* Play safe */
    372     unsigned32 gpr28;   /* For internal use by the IRQ handler */
    373     unsigned32 gpr29;   /* For internal use by the IRQ handler */
    374     unsigned32 gpr30;   /* For internal use by the IRQ handler */
    375     unsigned32 gpr31;   /* For internal use by the IRQ handler */
    376     unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
    377     unsigned32 ctr;
    378     unsigned32 xer;
    379     unsigned32 lr;
    380     unsigned32 pc;
    381     unsigned32 msr;
    382     unsigned32 pad[3];
     359    uint32_t  gpr0;
     360    uint32_t  gpr2;            /* play safe */
     361    uint32_t  gpr3;
     362    uint32_t  gpr4;
     363    uint32_t  gpr5;
     364    uint32_t  gpr6;
     365    uint32_t  gpr7;
     366    uint32_t  gpr8;
     367    uint32_t  gpr9;
     368    uint32_t  gpr10;
     369    uint32_t  gpr11;
     370    uint32_t  gpr12;
     371    uint32_t  gpr13;   /* Play safe */
     372    uint32_t  gpr28;   /* For internal use by the IRQ handler */
     373    uint32_t  gpr29;   /* For internal use by the IRQ handler */
     374    uint32_t  gpr30;   /* For internal use by the IRQ handler */
     375    uint32_t  gpr31;   /* For internal use by the IRQ handler */
     376    uint32_t  cr;      /* Bits of this are volatile, so no-one may save */
     377    uint32_t  ctr;
     378    uint32_t  xer;
     379    uint32_t  lr;
     380    uint32_t  pc;
     381    uint32_t  msr;
     382    uint32_t  pad[3];
    383383} CPU_Interrupt_frame;
    384384 
     
    394394  void       (*idle_task)( void );
    395395  boolean      do_zero_of_workspace;
    396   unsigned32   idle_task_stack_size;
    397   unsigned32   interrupt_stack_size;
    398   unsigned32   extra_mpci_receive_server_stack;
    399   void *     (*stack_allocate_hook)( unsigned32 );
     396  uint32_t     idle_task_stack_size;
     397  uint32_t     interrupt_stack_size;
     398  uint32_t     extra_mpci_receive_server_stack;
     399  void *     (*stack_allocate_hook)( uint32_t  );
    400400  void       (*stack_free_hook)( void* );
    401401  /* end of fields required on all CPUs */
    402402
    403   unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
     403  uint32_t     clicks_per_usec;        /* Timer clicks per microsecond */
    404404  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
    405405
    406406#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
    407   unsigned32   serial_per_sec;         /* Serial clocks per second */
     407  uint32_t     serial_per_sec;         /* Serial clocks per second */
    408408  boolean      serial_external_clock;
    409409  boolean      serial_xon_xoff;
    410410  boolean      serial_cts_rts;
    411   unsigned32   serial_rate;
    412   unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
    413   unsigned32   timer_least_valid;      /* Least valid number from timer      */
     411  uint32_t     serial_rate;
     412  uint32_t     timer_average_overhead; /* Average overhead of timer in ticks */
     413  uint32_t     timer_least_valid;      /* Least valid number from timer      */
    414414  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
    415415#endif
    416416
    417417#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
    418   unsigned32   clock_speed;            /* Speed of CPU in Hz */
     418  uint32_t     clock_speed;            /* Speed of CPU in Hz */
    419419#endif
    420420}   rtems_cpu_table;
     
    489489 
    490490SCORE_EXTERN struct {
    491   unsigned32 *Disable_level;
     491  uint32_t  *Disable_level;
    492492  void *Stack;
    493493  volatile boolean *Switch_necessary;
     
    612612#ifndef ASM
    613613 
    614 static inline unsigned32 _CPU_ISR_Get_level( void )
     614static inline uint32_t  _CPU_ISR_Get_level( void )
    615615{
    616616  register unsigned int msr;
     
    620620}
    621621
    622 static inline void _CPU_ISR_Set_level( unsigned32 level )
     622static inline void _CPU_ISR_Set_level( uint32_t  level )
    623623{
    624624  register unsigned int msr;
     
    659659void _CPU_Context_Initialize(
    660660  Context_Control  *the_context,
    661   unsigned32       *stack_base,
    662   unsigned32        size,
    663   unsigned32        new_level,
     661  uint32_t         *stack_base,
     662  uint32_t          size,
     663  uint32_t          new_level,
    664664  void             *entry_point,
    665665  boolean           is_fp
     
    818818/* variables */
    819819
    820 extern const unsigned32 _CPU_msrs[4];
     820extern const uint32_t  _CPU_msrs[4];
    821821
    822822/* functions */
     
    899899
    900900void _CPU_Fatal_error(
    901   unsigned32 _error
     901  uint32_t  _error
    902902);
    903903
     
    926926)
    927927{
    928   unsigned32 swapped;
     928  uint32_t  swapped;
    929929 
    930930  asm volatile("rlwimi %0,%1,8,24,31;"
  • cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h

    rc346f33d r30b1016  
    331331
    332332typedef struct {
    333     unsigned32 gpr1;    /* Stack pointer for all */
    334     unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
    335     unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
    336     unsigned32 gpr14;   /* Non volatile for all */
    337     unsigned32 gpr15;   /* Non volatile for all */
    338     unsigned32 gpr16;   /* Non volatile for all */
    339     unsigned32 gpr17;   /* Non volatile for all */
    340     unsigned32 gpr18;   /* Non volatile for all */
    341     unsigned32 gpr19;   /* Non volatile for all */
    342     unsigned32 gpr20;   /* Non volatile for all */
    343     unsigned32 gpr21;   /* Non volatile for all */
    344     unsigned32 gpr22;   /* Non volatile for all */
    345     unsigned32 gpr23;   /* Non volatile for all */
    346     unsigned32 gpr24;   /* Non volatile for all */
    347     unsigned32 gpr25;   /* Non volatile for all */
    348     unsigned32 gpr26;   /* Non volatile for all */
    349     unsigned32 gpr27;   /* Non volatile for all */
    350     unsigned32 gpr28;   /* Non volatile for all */
    351     unsigned32 gpr29;   /* Non volatile for all */
    352     unsigned32 gpr30;   /* Non volatile for all */
    353     unsigned32 gpr31;   /* Non volatile for all */
    354     unsigned32 cr;      /* PART of the CR is non volatile for all */
    355     unsigned32 pc;      /* Program counter/Link register */
    356     unsigned32 msr;     /* Initial interrupt level */
     333    uint32_t  gpr1;    /* Stack pointer for all */
     334    uint32_t  gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
     335    uint32_t  gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
     336    uint32_t  gpr14;   /* Non volatile for all */
     337    uint32_t  gpr15;   /* Non volatile for all */
     338    uint32_t  gpr16;   /* Non volatile for all */
     339    uint32_t  gpr17;   /* Non volatile for all */
     340    uint32_t  gpr18;   /* Non volatile for all */
     341    uint32_t  gpr19;   /* Non volatile for all */
     342    uint32_t  gpr20;   /* Non volatile for all */
     343    uint32_t  gpr21;   /* Non volatile for all */
     344    uint32_t  gpr22;   /* Non volatile for all */
     345    uint32_t  gpr23;   /* Non volatile for all */
     346    uint32_t  gpr24;   /* Non volatile for all */
     347    uint32_t  gpr25;   /* Non volatile for all */
     348    uint32_t  gpr26;   /* Non volatile for all */
     349    uint32_t  gpr27;   /* Non volatile for all */
     350    uint32_t  gpr28;   /* Non volatile for all */
     351    uint32_t  gpr29;   /* Non volatile for all */
     352    uint32_t  gpr30;   /* Non volatile for all */
     353    uint32_t  gpr31;   /* Non volatile for all */
     354    uint32_t  cr;      /* PART of the CR is non volatile for all */
     355    uint32_t  pc;      /* Program counter/Link register */
     356    uint32_t  msr;     /* Initial interrupt level */
    357357} Context_Control;
    358358
     
    374374
    375375typedef struct CPU_Interrupt_frame {
    376     unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
     376    uint32_t  stacklink;       /* Ensure this is a real frame (also reg1 save) */
    377377#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
    378     unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
     378    uint32_t  dummy[13];       /* Used by callees: PowerOpen ABI */
    379379#else
    380     unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
     380    uint32_t  dummy[1];        /* Used by callees: SVR4/EABI */
    381381#endif
    382382    /* This is what is left out of the primary contexts */
    383     unsigned32 gpr0;
    384     unsigned32 gpr2;            /* play safe */
    385     unsigned32 gpr3;
    386     unsigned32 gpr4;
    387     unsigned32 gpr5;
    388     unsigned32 gpr6;
    389     unsigned32 gpr7;
    390     unsigned32 gpr8;
    391     unsigned32 gpr9;
    392     unsigned32 gpr10;
    393     unsigned32 gpr11;
    394     unsigned32 gpr12;
    395     unsigned32 gpr13;   /* Play safe */
    396     unsigned32 gpr28;   /* For internal use by the IRQ handler */
    397     unsigned32 gpr29;   /* For internal use by the IRQ handler */
    398     unsigned32 gpr30;   /* For internal use by the IRQ handler */
    399     unsigned32 gpr31;   /* For internal use by the IRQ handler */
    400     unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
    401     unsigned32 ctr;
    402     unsigned32 xer;
    403     unsigned32 lr;
    404     unsigned32 pc;
    405     unsigned32 msr;
    406     unsigned32 pad[3];
     383    uint32_t  gpr0;
     384    uint32_t  gpr2;            /* play safe */
     385    uint32_t  gpr3;
     386    uint32_t  gpr4;
     387    uint32_t  gpr5;
     388    uint32_t  gpr6;
     389    uint32_t  gpr7;
     390    uint32_t  gpr8;
     391    uint32_t  gpr9;
     392    uint32_t  gpr10;
     393    uint32_t  gpr11;
     394    uint32_t  gpr12;
     395    uint32_t  gpr13;   /* Play safe */
     396    uint32_t  gpr28;   /* For internal use by the IRQ handler */
     397    uint32_t  gpr29;   /* For internal use by the IRQ handler */
     398    uint32_t  gpr30;   /* For internal use by the IRQ handler */
     399    uint32_t  gpr31;   /* For internal use by the IRQ handler */
     400    uint32_t  cr;      /* Bits of this are volatile, so no-one may save */
     401    uint32_t  ctr;
     402    uint32_t  xer;
     403    uint32_t  lr;
     404    uint32_t  pc;
     405    uint32_t  msr;
     406    uint32_t  pad[3];
    407407} CPU_Interrupt_frame;
    408408
     
    419419  void       (*idle_task)( void );
    420420  boolean      do_zero_of_workspace;
    421   unsigned32   idle_task_stack_size;
    422   unsigned32   interrupt_stack_size;
    423   unsigned32   extra_mpci_receive_server_stack;
    424   void *     (*stack_allocate_hook)( unsigned32 );
     421  uint32_t     idle_task_stack_size;
     422  uint32_t     interrupt_stack_size;
     423  uint32_t     extra_mpci_receive_server_stack;
     424  void *     (*stack_allocate_hook)( uint32_t  );
    425425  void       (*stack_free_hook)( void* );
    426426  /* end of fields required on all CPUs */
    427427
    428   unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
    429   void       (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
     428  uint32_t     clicks_per_usec;        /* Timer clicks per microsecond */
     429  void       (*spurious_handler)(uint32_t  vector, CPU_Interrupt_frame *);
    430430  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
    431431
    432432#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
    433   unsigned32   serial_per_sec;         /* Serial clocks per second */
     433  uint32_t     serial_per_sec;         /* Serial clocks per second */
    434434  boolean      serial_external_clock;
    435435  boolean      serial_xon_xoff;
    436436  boolean      serial_cts_rts;
    437   unsigned32   serial_rate;
    438   unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
    439   unsigned32   timer_least_valid;      /* Least valid number from timer      */
     437  uint32_t     serial_rate;
     438  uint32_t     timer_average_overhead; /* Average overhead of timer in ticks */
     439  uint32_t     timer_least_valid;      /* Least valid number from timer      */
    440440  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
    441441#endif
    442442
    443443#if (defined(mpc860) || defined(mpc821))
    444   unsigned32   clock_speed;            /* Speed of CPU in Hz */
     444  uint32_t     clock_speed;            /* Speed of CPU in Hz */
    445445#endif
    446446}   rtems_cpu_table;
     
    508508 
    509509typedef struct {
    510   unsigned32   stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
    511   unsigned32   stw_r0;                        /* stw   %r0, IP_0(%r1)       */
    512   unsigned32   li_r0_IRQ;                     /* li    %r0, _IRQ            */
    513   unsigned32   b_Handler;                     /* b     PROC (_ISR_Handler)  */
     510  uint32_t     stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
     511  uint32_t     stw_r0;                        /* stw   %r0, IP_0(%r1)       */
     512  uint32_t     li_r0_IRQ;                     /* li    %r0, _IRQ            */
     513  uint32_t     b_Handler;                     /* b     PROC (_ISR_Handler)  */
    514514} CPU_Trap_table_entry;
    515515
     
    557557
    558558SCORE_EXTERN struct {
    559   unsigned32 volatile* Nest_level;
    560   unsigned32 volatile* Disable_level;
     559  uint32_t  volatile* Nest_level;
     560  uint32_t  volatile* Disable_level;
    561561  void *Vector_table;
    562562  void *Stack;
    563563#if (PPC_ABI == PPC_ABI_POWEROPEN)
    564   unsigned32 Dispatch_r2;
     564  uint32_t  Dispatch_r2;
    565565#else
    566   unsigned32 Default_r2;
     566  uint32_t  Default_r2;
    567567#if (PPC_ABI != PPC_ABI_GCC27)
    568   unsigned32 Default_r13;
     568  uint32_t  Default_r13;
    569569#endif
    570570#endif
     
    572572  boolean *Signal;
    573573
    574   unsigned32 msr_initial;
     574  uint32_t  msr_initial;
    575575} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
    576576
     
    764764 */
    765765
    766 unsigned32 _CPU_ISR_Calculate_level(
    767   unsigned32 new_level
     766uint32_t  _CPU_ISR_Calculate_level(
     767  uint32_t  new_level
    768768);
    769769
    770770void _CPU_ISR_Set_level(
    771   unsigned32 new_level
     771  uint32_t  new_level
    772772);
    773773 
    774 unsigned32 _CPU_ISR_Get_level( void );
     774uint32_t  _CPU_ISR_Get_level( void );
    775775
    776776void _CPU_ISR_install_raw_handler(
    777   unsigned32  vector,
     777  uint32_t    vector,
    778778  proc_ptr    new_handler,
    779779  proc_ptr   *old_handler
     
    792792#define rtems_bsp_delay( _microseconds ) \
    793793  do { \
    794     unsigned32 start, ticks, now; \
     794    uint32_t  start, ticks, now; \
    795795    CPU_Get_timebase_low( start ) ; \
    796796    ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \
     
    802802#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
    803803  do { \
    804     unsigned32 start, now; \
     804    uint32_t  start, now; \
    805805    CPU_Get_timebase_low( start ); \
    806806    do \
     
    833833void _CPU_Context_Initialize(
    834834  Context_Control  *the_context,
    835   unsigned32       *stack_base,
    836   unsigned32        size,
    837   unsigned32        new_level,
     835  uint32_t         *stack_base,
     836  uint32_t          size,
     837  uint32_t          new_level,
    838838  void             *entry_point,
    839839  boolean           is_fp
     
    990990/* variables */
    991991
    992 extern const unsigned32 _CPU_msrs[4];
     992extern const uint32_t  _CPU_msrs[4];
    993993
    994994/* functions */
     
    10121012
    10131013void _CPU_ISR_install_vector(
    1014   unsigned32  vector,
     1014  uint32_t    vector,
    10151015  proc_ptr    new_handler,
    10161016  proc_ptr   *old_handler
     
    10731073
    10741074void _CPU_Fatal_error(
    1075   unsigned32 _error
     1075  uint32_t  _error
    10761076);
    10771077
     
    11001100)
    11011101{
    1102   unsigned32 swapped;
     1102  uint32_t  swapped;
    11031103 
    11041104  asm volatile("rlwimi %0,%1,8,24,31;"
     
    11271127 */
    11281128
    1129 static inline unsigned64 PPC_Get_timebase_register( void )
     1129static inline uint64_t  PPC_Get_timebase_register( void )
    11301130{
    1131   unsigned32 tbr_low;
    1132   unsigned32 tbr_high;
    1133   unsigned32 tbr_high_old;
    1134   unsigned64 tbr;
     1131  uint32_t  tbr_low;
     1132  uint32_t  tbr_high;
     1133  uint32_t  tbr_high_old;
     1134  uint64_t  tbr;
    11351135
    11361136  do {
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    rc346f33d r30b1016  
    279279#define rtems_bsp_delay( _microseconds ) \
    280280  do { \
    281     unsigned32 start, ticks, now; \
     281    uint32_t  start, ticks, now; \
    282282    CPU_Get_timebase_low( start ) ; \
    283283    ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
     
    289289#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
    290290  do { \
    291     unsigned32 start, now; \
     291    uint32_t  start, now; \
    292292    CPU_Get_timebase_low( start ); \
    293293    do \
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