Changeset 30b1016 in rtems
- Timestamp:
- 03/30/04 11:49:33 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- ddeb7693
- Parents:
- c346f33d
- Location:
- cpukit/score/cpu/powerpc
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/powerpc/ChangeLog
rc346f33d r30b1016 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, 4 rtems/powerpc/registers.h: Convert to using c99 fixed size types. 5 1 6 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 7 -
cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
rc346f33d r30b1016 311 311 312 312 typedef struct { 313 u nsigned32gpr1; /* Stack pointer for all */314 u nsigned32gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */315 u nsigned32gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */316 u nsigned32gpr14; /* Non volatile for all */317 u nsigned32gpr15; /* Non volatile for all */318 u nsigned32gpr16; /* Non volatile for all */319 u nsigned32gpr17; /* Non volatile for all */320 u nsigned32gpr18; /* Non volatile for all */321 u nsigned32gpr19; /* Non volatile for all */322 u nsigned32gpr20; /* Non volatile for all */323 u nsigned32gpr21; /* Non volatile for all */324 u nsigned32gpr22; /* Non volatile for all */325 u nsigned32gpr23; /* Non volatile for all */326 u nsigned32gpr24; /* Non volatile for all */327 u nsigned32gpr25; /* Non volatile for all */328 u nsigned32gpr26; /* Non volatile for all */329 u nsigned32gpr27; /* Non volatile for all */330 u nsigned32gpr28; /* Non volatile for all */331 u nsigned32gpr29; /* Non volatile for all */332 u nsigned32gpr30; /* Non volatile for all */333 u nsigned32gpr31; /* Non volatile for all */334 u nsigned32cr; /* PART of the CR is non volatile for all */335 u nsigned32pc; /* Program counter/Link register */336 u nsigned32msr; /* Initial interrupt level */313 uint32_t gpr1; /* Stack pointer for all */ 314 uint32_t gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ 315 uint32_t gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ 316 uint32_t gpr14; /* Non volatile for all */ 317 uint32_t gpr15; /* Non volatile for all */ 318 uint32_t gpr16; /* Non volatile for all */ 319 uint32_t gpr17; /* Non volatile for all */ 320 uint32_t gpr18; /* Non volatile for all */ 321 uint32_t gpr19; /* Non volatile for all */ 322 uint32_t gpr20; /* Non volatile for all */ 323 uint32_t gpr21; /* Non volatile for all */ 324 uint32_t gpr22; /* Non volatile for all */ 325 uint32_t gpr23; /* Non volatile for all */ 326 uint32_t gpr24; /* Non volatile for all */ 327 uint32_t gpr25; /* Non volatile for all */ 328 uint32_t gpr26; /* Non volatile for all */ 329 uint32_t gpr27; /* Non volatile for all */ 330 uint32_t gpr28; /* Non volatile for all */ 331 uint32_t gpr29; /* Non volatile for all */ 332 uint32_t gpr30; /* Non volatile for all */ 333 uint32_t gpr31; /* Non volatile for all */ 334 uint32_t cr; /* PART of the CR is non volatile for all */ 335 uint32_t pc; /* Program counter/Link register */ 336 uint32_t msr; /* Initial interrupt level */ 337 337 } Context_Control; 338 338 … … 354 354 355 355 typedef struct CPU_Interrupt_frame { 356 u nsigned32stacklink; /* Ensure this is a real frame (also reg1 save) */357 u nsigned32calleeLr; /* link register used by callees: SVR4/EABI */356 uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ 357 uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ 358 358 /* This is what is left out of the primary contexts */ 359 u nsigned32gpr0;360 u nsigned32gpr2; /* play safe */361 u nsigned32gpr3;362 u nsigned32gpr4;363 u nsigned32gpr5;364 u nsigned32gpr6;365 u nsigned32gpr7;366 u nsigned32gpr8;367 u nsigned32gpr9;368 u nsigned32gpr10;369 u nsigned32gpr11;370 u nsigned32gpr12;371 u nsigned32gpr13; /* Play safe */372 u nsigned32gpr28; /* For internal use by the IRQ handler */373 u nsigned32gpr29; /* For internal use by the IRQ handler */374 u nsigned32gpr30; /* For internal use by the IRQ handler */375 u nsigned32gpr31; /* For internal use by the IRQ handler */376 u nsigned32cr; /* Bits of this are volatile, so no-one may save */377 u nsigned32ctr;378 u nsigned32xer;379 u nsigned32lr;380 u nsigned32pc;381 u nsigned32msr;382 u nsigned32pad[3];359 uint32_t gpr0; 360 uint32_t gpr2; /* play safe */ 361 uint32_t gpr3; 362 uint32_t gpr4; 363 uint32_t gpr5; 364 uint32_t gpr6; 365 uint32_t gpr7; 366 uint32_t gpr8; 367 uint32_t gpr9; 368 uint32_t gpr10; 369 uint32_t gpr11; 370 uint32_t gpr12; 371 uint32_t gpr13; /* Play safe */ 372 uint32_t gpr28; /* For internal use by the IRQ handler */ 373 uint32_t gpr29; /* For internal use by the IRQ handler */ 374 uint32_t gpr30; /* For internal use by the IRQ handler */ 375 uint32_t gpr31; /* For internal use by the IRQ handler */ 376 uint32_t cr; /* Bits of this are volatile, so no-one may save */ 377 uint32_t ctr; 378 uint32_t xer; 379 uint32_t lr; 380 uint32_t pc; 381 uint32_t msr; 382 uint32_t pad[3]; 383 383 } CPU_Interrupt_frame; 384 384 … … 394 394 void (*idle_task)( void ); 395 395 boolean do_zero_of_workspace; 396 u nsigned32idle_task_stack_size;397 u nsigned32interrupt_stack_size;398 u nsigned32extra_mpci_receive_server_stack;399 void * (*stack_allocate_hook)( u nsigned32);396 uint32_t idle_task_stack_size; 397 uint32_t interrupt_stack_size; 398 uint32_t extra_mpci_receive_server_stack; 399 void * (*stack_allocate_hook)( uint32_t ); 400 400 void (*stack_free_hook)( void* ); 401 401 /* end of fields required on all CPUs */ 402 402 403 u nsigned32clicks_per_usec; /* Timer clicks per microsecond */403 uint32_t clicks_per_usec; /* Timer clicks per microsecond */ 404 404 boolean exceptions_in_RAM; /* TRUE if in RAM */ 405 405 406 406 #if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260)) 407 u nsigned32serial_per_sec; /* Serial clocks per second */407 uint32_t serial_per_sec; /* Serial clocks per second */ 408 408 boolean serial_external_clock; 409 409 boolean serial_xon_xoff; 410 410 boolean serial_cts_rts; 411 u nsigned32serial_rate;412 u nsigned32timer_average_overhead; /* Average overhead of timer in ticks */413 u nsigned32timer_least_valid; /* Least valid number from timer */411 uint32_t serial_rate; 412 uint32_t timer_average_overhead; /* Average overhead of timer in ticks */ 413 uint32_t timer_least_valid; /* Least valid number from timer */ 414 414 boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ 415 415 #endif 416 416 417 417 #if (defined(mpc860) || defined(mpc821) || defined(mpc8260)) 418 u nsigned32clock_speed; /* Speed of CPU in Hz */418 uint32_t clock_speed; /* Speed of CPU in Hz */ 419 419 #endif 420 420 } rtems_cpu_table; … … 489 489 490 490 SCORE_EXTERN struct { 491 u nsigned32*Disable_level;491 uint32_t *Disable_level; 492 492 void *Stack; 493 493 volatile boolean *Switch_necessary; … … 612 612 #ifndef ASM 613 613 614 static inline u nsigned32_CPU_ISR_Get_level( void )614 static inline uint32_t _CPU_ISR_Get_level( void ) 615 615 { 616 616 register unsigned int msr; … … 620 620 } 621 621 622 static inline void _CPU_ISR_Set_level( u nsigned32level )622 static inline void _CPU_ISR_Set_level( uint32_t level ) 623 623 { 624 624 register unsigned int msr; … … 659 659 void _CPU_Context_Initialize( 660 660 Context_Control *the_context, 661 u nsigned32*stack_base,662 u nsigned32size,663 u nsigned32new_level,661 uint32_t *stack_base, 662 uint32_t size, 663 uint32_t new_level, 664 664 void *entry_point, 665 665 boolean is_fp … … 818 818 /* variables */ 819 819 820 extern const u nsigned32_CPU_msrs[4];820 extern const uint32_t _CPU_msrs[4]; 821 821 822 822 /* functions */ … … 899 899 900 900 void _CPU_Fatal_error( 901 u nsigned32_error901 uint32_t _error 902 902 ); 903 903 … … 926 926 ) 927 927 { 928 u nsigned32swapped;928 uint32_t swapped; 929 929 930 930 asm volatile("rlwimi %0,%1,8,24,31;" -
cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h
rc346f33d r30b1016 331 331 332 332 typedef struct { 333 u nsigned32gpr1; /* Stack pointer for all */334 u nsigned32gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */335 u nsigned32gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */336 u nsigned32gpr14; /* Non volatile for all */337 u nsigned32gpr15; /* Non volatile for all */338 u nsigned32gpr16; /* Non volatile for all */339 u nsigned32gpr17; /* Non volatile for all */340 u nsigned32gpr18; /* Non volatile for all */341 u nsigned32gpr19; /* Non volatile for all */342 u nsigned32gpr20; /* Non volatile for all */343 u nsigned32gpr21; /* Non volatile for all */344 u nsigned32gpr22; /* Non volatile for all */345 u nsigned32gpr23; /* Non volatile for all */346 u nsigned32gpr24; /* Non volatile for all */347 u nsigned32gpr25; /* Non volatile for all */348 u nsigned32gpr26; /* Non volatile for all */349 u nsigned32gpr27; /* Non volatile for all */350 u nsigned32gpr28; /* Non volatile for all */351 u nsigned32gpr29; /* Non volatile for all */352 u nsigned32gpr30; /* Non volatile for all */353 u nsigned32gpr31; /* Non volatile for all */354 u nsigned32cr; /* PART of the CR is non volatile for all */355 u nsigned32pc; /* Program counter/Link register */356 u nsigned32msr; /* Initial interrupt level */333 uint32_t gpr1; /* Stack pointer for all */ 334 uint32_t gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ 335 uint32_t gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ 336 uint32_t gpr14; /* Non volatile for all */ 337 uint32_t gpr15; /* Non volatile for all */ 338 uint32_t gpr16; /* Non volatile for all */ 339 uint32_t gpr17; /* Non volatile for all */ 340 uint32_t gpr18; /* Non volatile for all */ 341 uint32_t gpr19; /* Non volatile for all */ 342 uint32_t gpr20; /* Non volatile for all */ 343 uint32_t gpr21; /* Non volatile for all */ 344 uint32_t gpr22; /* Non volatile for all */ 345 uint32_t gpr23; /* Non volatile for all */ 346 uint32_t gpr24; /* Non volatile for all */ 347 uint32_t gpr25; /* Non volatile for all */ 348 uint32_t gpr26; /* Non volatile for all */ 349 uint32_t gpr27; /* Non volatile for all */ 350 uint32_t gpr28; /* Non volatile for all */ 351 uint32_t gpr29; /* Non volatile for all */ 352 uint32_t gpr30; /* Non volatile for all */ 353 uint32_t gpr31; /* Non volatile for all */ 354 uint32_t cr; /* PART of the CR is non volatile for all */ 355 uint32_t pc; /* Program counter/Link register */ 356 uint32_t msr; /* Initial interrupt level */ 357 357 } Context_Control; 358 358 … … 374 374 375 375 typedef struct CPU_Interrupt_frame { 376 u nsigned32stacklink; /* Ensure this is a real frame (also reg1 save) */376 uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ 377 377 #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) 378 u nsigned32dummy[13]; /* Used by callees: PowerOpen ABI */378 uint32_t dummy[13]; /* Used by callees: PowerOpen ABI */ 379 379 #else 380 u nsigned32dummy[1]; /* Used by callees: SVR4/EABI */380 uint32_t dummy[1]; /* Used by callees: SVR4/EABI */ 381 381 #endif 382 382 /* This is what is left out of the primary contexts */ 383 u nsigned32gpr0;384 u nsigned32gpr2; /* play safe */385 u nsigned32gpr3;386 u nsigned32gpr4;387 u nsigned32gpr5;388 u nsigned32gpr6;389 u nsigned32gpr7;390 u nsigned32gpr8;391 u nsigned32gpr9;392 u nsigned32gpr10;393 u nsigned32gpr11;394 u nsigned32gpr12;395 u nsigned32gpr13; /* Play safe */396 u nsigned32gpr28; /* For internal use by the IRQ handler */397 u nsigned32gpr29; /* For internal use by the IRQ handler */398 u nsigned32gpr30; /* For internal use by the IRQ handler */399 u nsigned32gpr31; /* For internal use by the IRQ handler */400 u nsigned32cr; /* Bits of this are volatile, so no-one may save */401 u nsigned32ctr;402 u nsigned32xer;403 u nsigned32lr;404 u nsigned32pc;405 u nsigned32msr;406 u nsigned32pad[3];383 uint32_t gpr0; 384 uint32_t gpr2; /* play safe */ 385 uint32_t gpr3; 386 uint32_t gpr4; 387 uint32_t gpr5; 388 uint32_t gpr6; 389 uint32_t gpr7; 390 uint32_t gpr8; 391 uint32_t gpr9; 392 uint32_t gpr10; 393 uint32_t gpr11; 394 uint32_t gpr12; 395 uint32_t gpr13; /* Play safe */ 396 uint32_t gpr28; /* For internal use by the IRQ handler */ 397 uint32_t gpr29; /* For internal use by the IRQ handler */ 398 uint32_t gpr30; /* For internal use by the IRQ handler */ 399 uint32_t gpr31; /* For internal use by the IRQ handler */ 400 uint32_t cr; /* Bits of this are volatile, so no-one may save */ 401 uint32_t ctr; 402 uint32_t xer; 403 uint32_t lr; 404 uint32_t pc; 405 uint32_t msr; 406 uint32_t pad[3]; 407 407 } CPU_Interrupt_frame; 408 408 … … 419 419 void (*idle_task)( void ); 420 420 boolean do_zero_of_workspace; 421 u nsigned32idle_task_stack_size;422 u nsigned32interrupt_stack_size;423 u nsigned32extra_mpci_receive_server_stack;424 void * (*stack_allocate_hook)( u nsigned32);421 uint32_t idle_task_stack_size; 422 uint32_t interrupt_stack_size; 423 uint32_t extra_mpci_receive_server_stack; 424 void * (*stack_allocate_hook)( uint32_t ); 425 425 void (*stack_free_hook)( void* ); 426 426 /* end of fields required on all CPUs */ 427 427 428 u nsigned32clicks_per_usec; /* Timer clicks per microsecond */429 void (*spurious_handler)(u nsigned32vector, CPU_Interrupt_frame *);428 uint32_t clicks_per_usec; /* Timer clicks per microsecond */ 429 void (*spurious_handler)(uint32_t vector, CPU_Interrupt_frame *); 430 430 boolean exceptions_in_RAM; /* TRUE if in RAM */ 431 431 432 432 #if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821)) 433 u nsigned32serial_per_sec; /* Serial clocks per second */433 uint32_t serial_per_sec; /* Serial clocks per second */ 434 434 boolean serial_external_clock; 435 435 boolean serial_xon_xoff; 436 436 boolean serial_cts_rts; 437 u nsigned32serial_rate;438 u nsigned32timer_average_overhead; /* Average overhead of timer in ticks */439 u nsigned32timer_least_valid; /* Least valid number from timer */437 uint32_t serial_rate; 438 uint32_t timer_average_overhead; /* Average overhead of timer in ticks */ 439 uint32_t timer_least_valid; /* Least valid number from timer */ 440 440 boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ 441 441 #endif 442 442 443 443 #if (defined(mpc860) || defined(mpc821)) 444 u nsigned32clock_speed; /* Speed of CPU in Hz */444 uint32_t clock_speed; /* Speed of CPU in Hz */ 445 445 #endif 446 446 } rtems_cpu_table; … … 508 508 509 509 typedef struct { 510 u nsigned32stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/511 u nsigned32stw_r0; /* stw %r0, IP_0(%r1) */512 u nsigned32li_r0_IRQ; /* li %r0, _IRQ */513 u nsigned32b_Handler; /* b PROC (_ISR_Handler) */510 uint32_t stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/ 511 uint32_t stw_r0; /* stw %r0, IP_0(%r1) */ 512 uint32_t li_r0_IRQ; /* li %r0, _IRQ */ 513 uint32_t b_Handler; /* b PROC (_ISR_Handler) */ 514 514 } CPU_Trap_table_entry; 515 515 … … 557 557 558 558 SCORE_EXTERN struct { 559 u nsigned32volatile* Nest_level;560 u nsigned32volatile* Disable_level;559 uint32_t volatile* Nest_level; 560 uint32_t volatile* Disable_level; 561 561 void *Vector_table; 562 562 void *Stack; 563 563 #if (PPC_ABI == PPC_ABI_POWEROPEN) 564 u nsigned32Dispatch_r2;564 uint32_t Dispatch_r2; 565 565 #else 566 u nsigned32Default_r2;566 uint32_t Default_r2; 567 567 #if (PPC_ABI != PPC_ABI_GCC27) 568 u nsigned32Default_r13;568 uint32_t Default_r13; 569 569 #endif 570 570 #endif … … 572 572 boolean *Signal; 573 573 574 u nsigned32msr_initial;574 uint32_t msr_initial; 575 575 } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; 576 576 … … 764 764 */ 765 765 766 u nsigned32_CPU_ISR_Calculate_level(767 u nsigned32new_level766 uint32_t _CPU_ISR_Calculate_level( 767 uint32_t new_level 768 768 ); 769 769 770 770 void _CPU_ISR_Set_level( 771 u nsigned32new_level771 uint32_t new_level 772 772 ); 773 773 774 u nsigned32_CPU_ISR_Get_level( void );774 uint32_t _CPU_ISR_Get_level( void ); 775 775 776 776 void _CPU_ISR_install_raw_handler( 777 u nsigned32vector,777 uint32_t vector, 778 778 proc_ptr new_handler, 779 779 proc_ptr *old_handler … … 792 792 #define rtems_bsp_delay( _microseconds ) \ 793 793 do { \ 794 u nsigned32start, ticks, now; \794 uint32_t start, ticks, now; \ 795 795 CPU_Get_timebase_low( start ) ; \ 796 796 ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \ … … 802 802 #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ 803 803 do { \ 804 u nsigned32start, now; \804 uint32_t start, now; \ 805 805 CPU_Get_timebase_low( start ); \ 806 806 do \ … … 833 833 void _CPU_Context_Initialize( 834 834 Context_Control *the_context, 835 u nsigned32*stack_base,836 u nsigned32size,837 u nsigned32new_level,835 uint32_t *stack_base, 836 uint32_t size, 837 uint32_t new_level, 838 838 void *entry_point, 839 839 boolean is_fp … … 990 990 /* variables */ 991 991 992 extern const u nsigned32_CPU_msrs[4];992 extern const uint32_t _CPU_msrs[4]; 993 993 994 994 /* functions */ … … 1012 1012 1013 1013 void _CPU_ISR_install_vector( 1014 u nsigned32vector,1014 uint32_t vector, 1015 1015 proc_ptr new_handler, 1016 1016 proc_ptr *old_handler … … 1073 1073 1074 1074 void _CPU_Fatal_error( 1075 u nsigned32_error1075 uint32_t _error 1076 1076 ); 1077 1077 … … 1100 1100 ) 1101 1101 { 1102 u nsigned32swapped;1102 uint32_t swapped; 1103 1103 1104 1104 asm volatile("rlwimi %0,%1,8,24,31;" … … 1127 1127 */ 1128 1128 1129 static inline u nsigned64PPC_Get_timebase_register( void )1129 static inline uint64_t PPC_Get_timebase_register( void ) 1130 1130 { 1131 u nsigned32tbr_low;1132 u nsigned32tbr_high;1133 u nsigned32tbr_high_old;1134 u nsigned64tbr;1131 uint32_t tbr_low; 1132 uint32_t tbr_high; 1133 uint32_t tbr_high_old; 1134 uint64_t tbr; 1135 1135 1136 1136 do { -
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
rc346f33d r30b1016 279 279 #define rtems_bsp_delay( _microseconds ) \ 280 280 do { \ 281 u nsigned32start, ticks, now; \281 uint32_t start, ticks, now; \ 282 282 CPU_Get_timebase_low( start ) ; \ 283 283 ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \ … … 289 289 #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ 290 290 do { \ 291 u nsigned32start, now; \291 uint32_t start, now; \ 292 292 CPU_Get_timebase_low( start ); \ 293 293 do \
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