Changeset 2ffbc4d in rtems


Ignore:
Timestamp:
May 8, 2019, 11:02:47 AM (2 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
271b8a6
Parents:
d49ff3e
git-author:
Sebastian Huber <sebastian.huber@…> (05/08/19 11:02:47)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/08/19 11:05:26)
Message:

bsp/lpc24xx: Flexible LPC24XX_EMC_MT48LC4M16A2 cfg

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/lpc24xx/start/start-config-emc-dynamic.c

    rd49ff3e r2ffbc4d  
    88
    99/*
    10  * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011, 2019 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    2525
    2626/*
    27  * FIXME: The NXP example code uses different values for the follwing two
     27 * FIXME: The NXP example code uses different values for the following two
    2828 * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
    2929 * how these values are determined.  The values from the NXP example code do
     
    4747
    4848    /* Precharge command period 20 ns */
    49     .trp = 1,
     49    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
    5050
    5151    /* Active to precharge command period 44 ns */
    52     .tras = 3,
    53 
    54     /* FIXME */
    55     .tsrex = 5,
    56 
    57     /* FIXME */
    58     .tapr = 2,
     52    .tras = LPC24XX_PS_TO_EMCCLK(44000, 1),
     53
     54    /*
     55     * UM: "devices without this parameter you use the same value as tXSR"
     56     *
     57     * The tXSR is 75 ns.
     58     */
     59    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
     60
     61    /*
     62     * Forum: "tAPR, not in datasheet, if fail, use tRCD val"
     63     *
     64     * The tRCD is 20 ns */
     65    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
    5966
    6067    /* Data-in to active command period tWR + tRP */
    61     .tdal = 4,
    62 
    63     /* Write recovery time 15 ns */
    64     .twr = 1,
     68    .tdal = LPC24XX_PS_TO_EMCCLK(15000 + 20000, 0),
     69
     70    /* Write recovery time 15 ns or 1 CLK + 7.5ns */
     71    .twr = LPC24XX_PS_TO_EMCCLK(15000, 1),
    6572
    6673    /* Active to active command period 66 ns */
    67     .trc = 4,
     74    .trc = LPC24XX_PS_TO_EMCCLK(66000, 1),
    6875
    6976    /* Auto refresh period 66 ns */
    70     .trfc = 4,
     77    .trfc = LPC24XX_PS_TO_EMCCLK(66000, 1),
    7178
    7279    /* Exit self refresh to active command period 75 ns */
    73     .txsr = 5,
     80    .txsr = LPC24XX_PS_TO_EMCCLK(75000, 1),
    7481
    7582    /* Active bank a to active bank b command period 15 ns */
    76     .trrd = 1,
     83    .trrd = LPC24XX_PS_TO_EMCCLK(15000, 1),
    7784
    7885    /* Load mode register to active or refresh command period 2 tCK */
    79     .tmrd = 1
     86    .tmrd = 1 /* + 1 */
    8087  }
    8188#elif defined(LPC24XX_EMC_IS42S32800D7)
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