Changeset 2fd427c in rtems for cpukit/score/cpu/no_cpu


Ignore:
Timestamp:
Jun 5, 2008, 2:30:07 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
d9857c8
Parents:
8c444f9a
Message:

2008-06-05 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting parameter to indicate that the port uses the Simple Vectored Interrupt model or the Programmable Interrupt Controller Model. The PIC model is implemented primarily in the BSP and it is responsible for all memory allocation.
Location:
cpukit/score/cpu/no_cpu
Files:
2 edited

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Unmodified
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  • cpukit/score/cpu/no_cpu/ChangeLog

    r8c444f9a r2fd427c  
     12008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
     4        parameter to indicate that the port uses the Simple Vectored
     5        Interrupt model or the Programmable Interrupt Controller Model. The
     6        PIC model is implemented primarily in the BSP and it is responsible
     7        for all memory allocation.
     8
    192008-01-29      Joel Sherrill <joel.sherrill@oarcorp.com>
    210
  • cpukit/score/cpu/no_cpu/rtems/score/cpu.h

    r8c444f9a r2fd427c  
    119119 */
    120120#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
     121
     122/**
     123 *  Does the CPU follow the simple vectored interrupt model?
     124 *
     125 *  If TRUE, then RTEMS allocates the vector table it internally manages.
     126 *  If FALSE, then the BSP is assumed to allocate and manage the vector
     127 *  table
     128 *
     129 *  Port Specific Information:
     130 *
     131 *  XXX document implementation including references if appropriate
     132 */
     133#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    121134
    122135/**
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