Changeset 2fbe159e in rtems


Ignore:
Timestamp:
Sep 19, 2008, 3:49:28 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
8074c0b1
Parents:
c1dcda5d
Message:

2008-09-19 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, startup/bspstart.c: Split out bspstart contents. Move cache code to libcpu.
  • startup/bspgetcpuclockspeed.c: New file.
Location:
c/src/lib/libbsp/m68k/mcf5235
Files:
1 added
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/mcf5235/ChangeLog

    rc1dcda5d r2fbe159e  
     12008-09-19      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * Makefile.am, startup/bspstart.c: Split out bspstart contents. Move
     4        cache code to libcpu.
     5        * startup/bspgetcpuclockspeed.c: New file.
     6
    172008-09-18      Joel Sherrill <joel.sherrill@oarcorp.com>
    28
  • c/src/lib/libbsp/m68k/mcf5235/Makefile.am

    rc1dcda5d r2fbe159e  
    2929startup_SOURCES = startup/bspclean.c ../../shared/bsppredriverhook.c \
    3030    ../../shared/bsplibc.c ../../shared/bsppost.c \
    31     ../../shared/bsppretaskinghook.c ../../shared/bspgetworkarea.c \
    32     startup/init5235.c startup/bspstart.c ../../shared/bootcard.c \
    33     ../../shared/sbrk.c ../../m68k/shared/setvec.c \
     31    startup/bspgetcpuclockspeed.c ../../shared/bsppretaskinghook.c \
     32    ../../shared/bspgetworkarea.c startup/init5235.c startup/bspstart.c \
     33    ../../shared/bootcard.c ../../shared/sbrk.c ../../m68k/shared/setvec.c \
    3434    ../../shared/gnatinstallhandler.c
    3535clock_SOURCES = clock/clock.c
     
    5252libbsp_a_LIBADD = \
    5353    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     54    ../../../libcpu/@RTEMS_CPU@/mcf5235/cachepd.rel \
    5455    ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
    5556if HAS_NETWORKING
  • c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c

    rc1dcda5d r2fbe159e  
    11/*
    2  *  BSP startup
    3  *
    4  *  This routine starts the application.  It includes application,
    5  *  board, and monitor specific initialization and configuration.
    6  *  The generic CPU dependent initialization has been performed
    7  *  before this routine is invoked.
    8  *
    9  *  Author:
    10  *    David Fiddes, D.J@fiddes.surfaid.org
    11  *    http://www.calm.hw.ac.uk/davidf/coldfire/
    12  *
    13  *  COPYRIGHT (c) 1989-1998.
     2 *  COPYRIGHT (c) 1989-2008.
    143 *  On-Line Applications Research Corporation (OAR).
    154 *
     
    2514 
    2615/*
    27  * Cacheable areas
    28  */
    29 #define SDRAM_BASE      0
    30 #define SDRAM_SIZE      (16*1024*1024)
    31 
    32 /*
    33  * CPU-space access
    34  */
    35 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
    36 #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
    37 #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
    38 
    39 /*
    4016 * Read/write copy of common cache
    4117 *   Split I/D cache
     
    4521 *   Default cache mode is *disabled* (cache only ACRx areas)
    4622 */
    47 static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
    48                               MCF5XXX_CACR_DBWE |
    49                               MCF5XXX_CACR_DCM;
    50 /*
    51  * Cannot be frozen
    52  */
    53 void _CPU_cache_freeze_data(void) {}
    54 void _CPU_cache_unfreeze_data(void) {}
    55 void _CPU_cache_freeze_instruction(void) {}
    56 void _CPU_cache_unfreeze_instruction(void) {}
     23uint32_t cacr_mode = MCF5XXX_CACR_CENB | MCF5XXX_CACR_DBWE | MCF5XXX_CACR_DCM;
    5724
    5825/*
    59  * Write-through data cache -- flushes are unnecessary
     26 * Cacheable areas
    6027 */
    61 void _CPU_cache_flush_1_data_line(const void *d_addr) {}
    62 void _CPU_cache_flush_entire_data(void) {}
    63 
    64 void _CPU_cache_enable_instruction(void)
    65 {
    66     rtems_interrupt_level level;
    67 
    68     rtems_interrupt_disable(level);
    69     cacr_mode &= ~MCF5XXX_CACR_DIDI;
    70     m68k_set_cacr(cacr_mode);
    71     rtems_interrupt_enable(level);
    72 }
    73 
    74 void _CPU_cache_disable_instruction(void)
    75 {
    76     rtems_interrupt_level level;
    77 
    78     rtems_interrupt_disable(level);
    79     cacr_mode |= MCF5XXX_CACR_DIDI;
    80     m68k_set_cacr(cacr_mode);
    81     rtems_interrupt_enable(level);
    82 }
    83 
    84 void _CPU_cache_invalidate_entire_instruction(void)
    85 {
    86     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
    87 }
    88 
    89 void _CPU_cache_invalidate_1_instruction_line(const void *addr)
    90 {
    91     /*
    92      * Top half of cache is I-space
    93      */
    94     addr = (void *)((int)addr | 0x400);
    95     asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
    96 }
    97 
    98 void _CPU_cache_enable_data(void)
    99 {
    100     rtems_interrupt_level level;
    101 
    102     rtems_interrupt_disable(level);
    103     cacr_mode &= ~MCF5XXX_CACR_DISD;
    104     m68k_set_cacr(cacr_mode);
    105     rtems_interrupt_enable(level);
    106 }
    107 
    108 void _CPU_cache_disable_data(void)
    109 {
    110     rtems_interrupt_level level;
    111 
    112     rtems_interrupt_disable(level);
    113     cacr_mode |= MCF5XXX_CACR_DISD;
    114     m68k_set_cacr(cacr_mode);
    115     rtems_interrupt_enable(level);
    116 }
    117 
    118 void _CPU_cache_invalidate_entire_data(void)
    119 {
    120     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
    121 }
    122 
    123 void _CPU_cache_invalidate_1_data_line(const void *addr)
    124 {
    125     /*
    126      * Bottom half of cache is D-space
    127      */
    128     addr = (void *)((int)addr & ~0x400);
    129     asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
    130 }
     28extern char RamBase[];
     29extern char RamSize[];
    13130
    13231/*
     
    14746   * Cache SDRAM
    14847   */
    149   m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
    150                 MCF5XXX_ACR_AM(SDRAM_SIZE-1) |
    151                 MCF5XXX_ACR_EN                |
    152                 MCF5XXX_ACR_BWE               |
     48  m68k_set_acr0(MCF5XXX_ACR_AB((uintptr_t)RamBase)   |
     49                MCF5XXX_ACR_AM((uintptr_t)RamSize-1) |
     50                MCF5XXX_ACR_EN                       |
     51                MCF5XXX_ACR_BWE                      |
    15352                MCF5XXX_ACR_SM_IGNORE);
    15453
     
    15857  m68k_set_cacr(cacr_mode);
    15958}
    160 
    161 extern char _CPUClockSpeed[];
    162 
    163 uint32_t get_CPU_clock_speed(void)
    164 {
    165   return( (uint32_t)_CPUClockSpeed);
    166 }
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