Changeset 2f6ee01 in rtems


Ignore:
Timestamp:
07/05/22 18:35:28 (3 months ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
6e74ceb
Parents:
22015c0
git-author:
Kinsey Moore <kinsey.moore@…> (07/05/22 18:35:28)
git-committer:
Joel Sherrill <joel@…> (07/06/22 15:22:08)
Message:

bsps/aarch64: Use MMU pages appropriately

There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.

Files:
5 edited

Legend:

Unmodified
Added
Removed
  • bsps/aarch64/include/bsp/aarch64-mmu.h

    r22015c0 r2f6ee01  
    146146{
    147147  /* First page table is already in use as TTB0 */
    148   static uintptr_t *current_page_table =
    149     (uintptr_t *) bsp_translation_table_base;
     148  static uintptr_t current_page_table =
     149    (uintptr_t) bsp_translation_table_base;
    150150
    151151  current_page_table += MMU_PAGE_SIZE;
  • spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml

    r22015c0 r2f6ee01  
    3030
    3131  MEMORY {
    32     RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
    33     NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
    34     RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
     32    RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
     33    NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
     34    RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
    3535  }
    3636
  • spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml

    r22015c0 r2f6ee01  
    3030
    3131  MEMORY {
    32     RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
    33     NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
    34     RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
     32    RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
     33    NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
     34    RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
    3535  }
    3636
  • spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml

    r22015c0 r2f6ee01  
    3131
    3232  MEMORY {
    33     RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
    34     NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
    35     RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
     33    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
     34    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
     35    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
    3636  }
    3737
  • spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml

    r22015c0 r2f6ee01  
    3131
    3232  MEMORY {
    33     RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
    34     NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
    35     RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
     33    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
     34    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
     35    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
    3636  }
    3737
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