Changeset 2f5435a4 in rtems


Ignore:
Timestamp:
Mar 25, 2010, 8:26:00 PM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
1f4db180
Parents:
89bb075
Message:

add support for mpc551x based GW_LCFM system

Location:
c/src/lib
Files:
4 added
11 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog

    r89bb075 r2f5435a4  
     12010-03-25      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * Makefile.am, confiugre.ac, include/bsp.h, startup/bspstart.c,
     4        startup/start.S:
     5        add support for GW_LCFM mpc551x based system
     6
    172009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am

    r89bb075 r2f5435a4  
    5959
    6060# tests
    61 libbsp_a_SOURCES += ../../shared/timerstub.c
     61libbsp_a_SOURCES += tests/tests.c startup/sd-card-init.c
    6262
    63 # tests
    64 libbsp_a_SOURCES += tests/tests.c startup/sd-card-init.c
     63# bsp_i2c
     64libbsp_a_SOURCES += i2c/i2c_init.c
    6565
    6666# Network
     
    7979    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/misc.rel \
    8080    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq.rel \
     81    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/siu.rel \
    8182    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/edma.rel \
    8283    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/emios.rel \
     
    8485    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/esci.rel \
    8586    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    86     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel
    87 
     87    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     88    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel
    8889if HAS_NETWORKING
    8990libbsp_a_LIBADD += network.rel
  • c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac

    r89bb075 r2f5435a4  
    2929 Termios support is independent of the choice of UART I/O mode.])
    3030
    31 RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[*],[MPC55XX_ESCI_A_MINOR])
     31RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[GWLCFM],[MPC55XX_ESCI_A_MINOR])
     32RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[*]     ,[MPC55XX_ESCI_A_MINOR])
    3233RTEMS_BSPOPTS_HELP([CONSOLE_MINOR],
    3334[Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR.  Determines which
    3435 device will be registered as /dev/console.])
    3536
    36 RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[*],[0])
     37RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[GWLCFM],[1])
     38RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[*]     ,[0])
    3739RTEMS_BSPOPTS_HELP([UARTS_IO_MODE],
    3840[Define to 1 if you want interrupt-driven I/O for the SCI ports.])
    3941
    40 RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*],[MPC55XX_ESCI_B_MINOR])
     42RTEMS_BSPOPTS_SET([PRINTK_MINOR],[GWLCFM],[MPC55XX_ESCI_A_MINOR])
     43RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*]     ,[MPC55XX_ESCI_B_MINOR])
    4144RTEMS_BSPOPTS_HELP([PRINTK_MINOR],
    4245[Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR.  Determines which
     
    4447 I/O.  Don't open the printk port from RTEMS unless also using polled I/O
    4548 for the SCI ports.])
     49
     50RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[GWLCFM],[40000000])
     51RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[*]     ,[8000000])
     52RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_REF_CLOCK],
     53[Must be defined to be the external reference clock (in Hz)
     54 for clock generation])
     55
     56RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[GWLCFM],[66000000])
     57RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[*]     ,[128000000])
     58RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_REF_CLOCK],
     59[Must be defined to be the PLL output clock (in Hz) for clock generation])
     60
     61RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[GWLCFM],[10])
     62RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[*]     ,[1])
     63RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_PREDIV],
     64[Must be defined to be the PLL predivider factor for clock generation])
     65
     66RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[GWLCFM],[99])
     67RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[*]     ,[12])
     68RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_MFD],
     69[Must be defined to be the PLL multiplication factor for clock generation])
     70
     71RTEMS_BSPOPTS_SET([MPC55XX_CHIP_DERIVATE],[*]         ,[5554])
     72RTEMS_BSPOPTS_SET([MPC55XX_CHIP_DERIVATE],[MPC5566EVB],[5566])
     73RTEMS_BSPOPTS_SET([MPC55XX_CHIP_DERIVATE],[GWLCFM]    ,[5516])
     74RTEMS_BSPOPTS_HELP([MPC55XX_CHIP_DERIVATE],
     75[specifies the chip derivate in use (e.g. 5554 for MPC5554)])
    4676
    4777AC_CONFIG_FILES([Makefile
  • c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h

    r89bb075 r2f5435a4  
    4444extern uint32_t bsp_clicks_per_usec;
    4545
     46/** @brief Convert Decrementer ticks to microseconds */
     47#define BSP_Convert_decrementer( _value ) \
     48  (((unsigned long long) (_value)) / ((unsigned long long)bsp_clicks_per_usec))
     49
    4650rtems_status_code mpc55xx_sd_card_init( bool mount);
    4751
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c

    r89bb075 r2f5435a4  
    2222#include <mpc55xx/regs.h>
    2323#include <mpc55xx/edma.h>
     24#include <mpc55xx/emios.h>
     25#include <mpc55xx/siu.h>
    2426
    2527#include <rtems.h>
     
    9193}
    9294
    93 static void mpc55xx_ebi_init()
     95#if ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517))
     96/*
     97 * define init values for FMPLL ESYNCRx
     98 * (used in start.S/fmpll.S)
     99 */
     100#define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
     101#define EMFD_VAL    (MPC55XX_FMPLL_MFD-16)
     102#define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
     103#define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
     104#define ERFD_VAL    ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
     105
     106const struct fmpll_syncr_vals_t {
     107  union ESYNCR2_tag esyncr2_temp;
     108  union ESYNCR2_tag esyncr2_final;
     109  union ESYNCR1_tag esyncr1_final;
     110} fmpll_syncr_vals =
     111  {
     112    { /* esyncr2_temp */
     113      .B.LOCEN=0,
     114      .B.LOLRE=0,
     115      .B.LOCRE=0,
     116      .B.LOLIRQ=0,
     117      .B.LOCIRQ=0,
     118      .B.ERATE=0,
     119      .B.DEPTH=0,
     120      .B.ERFD=ERFD_VAL+2 /* reduce output clock during init */
     121    },
     122    { /* esyncr2_final */
     123      .B.LOCEN=0,
     124      .B.LOLRE=0,
     125      .B.LOCRE=0,
     126      .B.LOLIRQ=0,
     127      .B.LOCIRQ=0,
     128      .B.ERATE=0,
     129      .B.DEPTH=0,
     130      .B.ERFD=ERFD_VAL /* nominal output clock after init */
     131    },
     132    { /* esyncr1_final */
     133      .B.CLKCFG=7,
     134      .B.EPREDIV=EPREDIV_VAL,
     135      .B.EMFD=EMFD_VAL
     136    }
     137  };
     138
     139#else /* ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517)) */
     140
     141const struct fmpll_syncr_vals_t {
     142  union SYNCR_tag syncr_temp;
     143  union SYNCR_tag syncr_final;
     144} fmpll_syncr_vals =
     145  {
     146    { /* syncr_temp */
     147      .B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
     148      .B.MFD=MPC55XX_FMPLL_MFD,
     149      .B.RFD=2,
     150      .B.LOCEN=1
     151    },
     152    { /* syncr_final */
     153      .B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
     154      .B.MFD=MPC55XX_FMPLL_MFD,
     155      .B.RFD=0,
     156      .B.LOCEN=1
     157    }
     158  };
     159
     160#endif /* ((MPC55XX_CHIP_DERIVATE>=5510) && (MPC55XX_CHIP_DERIVATE<=5517)) */
     161
     162#if defined(GWLCFM)
     163static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
     164  {  0,16,{.B.PA = 1,           .B.WPE = 0}}, /* PA[ 0..15] analog input */
     165  { 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */
     166  { 20, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 5.. 6] CAN_ERR/USBFLGC in*/
     167  { 22, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 7    ] FR_A_EN out */
     168  { 23, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 8..10] IRQ/FR_A_ERR/USB_RDYin */
     169  { 27, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[11..11] FR_STBN out */
     170
     171  { 32, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 0.. 1] FR_A_TX/TXEN out */
     172  { 34, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 2.. 2] FR_A_RX in */
     173  { 35, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 3.. 4] INIT_ERR/ISB_IRQ in */
     174  { 37, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 5.. 6] PWRO1/2_ON out */
     175  { 39, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 7.. 7] FR_B_RX in */
     176  { 40, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 8.. 9] FR_B_TX/TXEN out */
     177  { 42, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[10    ] FR_B_EN out */
     178  { 43, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[11    ] FOR_STATUS in */
     179  { 44, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[12    ] FR_B_ERRN  in */
     180  { 45, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[13    ] HS_CAN_STBN out */
     181  { 46, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[14    ] HS_CAN_ERR in */
     182  { 47, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[15    ] HS_CAN_EN out */
     183
     184  { 48, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 0    ] HS_CAN_TX out */
     185  { 49, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 1    ] HS_CAN_RX in  */
     186  { 50, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 2.. 3] PWRO1/2_OC in */
     187  { 52, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 4    ] LS_CAN_TX out */
     188  { 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5    ] LS_CAN_RX in  */
     189  { 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6    ] HS_CAN_TX out */
     190  { 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7    ] HS_CAN_RX in  */
     191  { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
     192  /* PD[ 8    ] I2C_SCL in/out */
     193  { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
     194  /* PD[ 9    ] I2C_SDA in/out */
     195  { 58, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10..13] LS_CAN_EN/LED out*/
     196  { 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B    in */
     197
     198  { 64, 3,{.B.PA = 3,.B.IBE = 1,.B.WPE = 0}}, /* PE[ 0.. 2] MLBCLK/SI/DI  in */
     199  { 67, 2,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 3.. 4] MLBSO/DO      out*/
     200  { 69, 1,{.B.PA = 3,.B.IBE = 1,.B.WPE = 0}}, /* PE[ 5.. 5] MLBSLOT       in */
     201  { 70, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 6.. 6] CLKOUT        out*/
     202  { 80, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PF[ 0.. 0] RD_WR         out*/
     203  { 81, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PF[ 1.. 1] (nc)          in */
     204  { 82,14,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PF[ 2..14] ADDR/CS/...   out*/
     205  { 96,16,{.B.PA = 1,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
     206  /* PG[ 0..15] AD16..31   in/out*/
     207
     208  {112, 3,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 0.. 2] LED_EXT1-3.   out*/
     209  {115, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 3.. 3] CS2_ETH       out*/
     210  {116, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 4.. 5] FR/HC_TERM    out*/
     211  {118, 1,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 6.. 6] LIN_Tx        out*/
     212  {119, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PH[ 7.. 7] LIN_Rx        in */
     213  {120, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 8..11] LIN_SLP,RST   out*/
     214
     215  {0,0}
     216};
     217
     218#else /* MPC55xxEVB */
     219
     220static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
     221  {  0, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS  [0]      */
     222  {  3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS  [3]      */
     223  {  4,24,{.B.PA = 1,.B.DSC = 1                  }}, /* ADDR [8 : 31] */
     224  { 28,16,{.B.PA = 1,.B.DSC = 1                  }}, /* DATA [0 : 15] */
     225  { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
     226                                                        !WE, !OE, !TS */
     227  { 89, 2,{.B.PA = 1                             }}, /* ESCI_B        */
     228
     229  {0,0}
     230};
     231#endif /* GWLCFM */
     232
     233static void mpc55xx_ebi_init(void)
    94234{
    95235        struct EBI_CS_tag cs = { .BR = MPC55XX_ZERO_FLAGS, .OR = MPC55XX_ZERO_FLAGS };
    96         union SIU_PCR_tag pcr = MPC55XX_ZERO_FLAGS;
    97236        struct MMU_tag mmu = MMU_DEFAULT;
    98         int i = 0;
    99 
    100         /* ADDR [8 : 31] */
    101         for (i = 4; i < 4 + 24; ++i) {
    102                 SIU.PCR [i].R = 0x440;
    103         }
    104 
    105         /* DATA [0 : 15] */
    106         for (i = 28; i < 28 + 16; ++i) {
    107                 SIU.PCR [i].R = 0x440;
    108         }
    109 
    110         /* RD_!WR */
    111         SIU.PCR [62].R = 0x443;
    112 
    113         /* !BDIP */
    114         SIU.PCR [63].R = 0x443;
    115 
    116         /* !WE [0 : 3] */
    117         for (i = 64; i < 64 + 4; ++i) {
    118                 SIU.PCR [i].R = 0x443;
    119         }
    120 
    121         /* !OE */
    122         SIU.PCR [68].R = 0x443;
    123 
    124         /* !TS */
    125         SIU.PCR [69].R = 0x443;
    126 
     237       
     238        /*
     239         * init I/O pins to proper state
     240         */
     241        mpc55xx_siu_pcr_init(&SIU,
     242                             siu_pcr_list);
    127243        /* External SRAM (2 wait states, 512kB, 4 word burst) */
    128244
     
    140256
    141257        EBI.CS [0] = cs;
    142 
    143         /* !CS [0] */
    144         SIU.PCR [0].R = 0x443;
    145258
    146259        /* External Ethernet Controller (3 wait states, 64kB) */
     
    179292
    180293        EBI.CS [3] = cs;
    181 
    182         /* !CS [3] */
    183         SIU.PCR [3].R = 0x443;
    184294}
    185295
     
    193303        ppc_cpu_revision_t myCpuRevision;
    194304
    195         uint32_t interrupt_stack_start = bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE;
     305        uintptr_t interrupt_stack_start = (uintptr_t)bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE;
    196306        uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE;
    197 
    198         /* ESCI pad configuration */
    199         SIU.PCR [89].R = 0x400;
    200         SIU.PCR [90].R = 0x400;
    201307
    202308        RTEMS_DEBUG_PRINT( "BSP start ...\n");
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S

    r89bb075 r2f5435a4  
    1919 */
    2020
    21 #warning Call to boot_card has changed and needs checking.
    22 #warning The call is "void boot_card(const char* cmdline);"
    23 #warning You need to pass a NULL.
    24 #warning Please check and remove these warnings.
    25 
    2621/**
    2722 * @defgroup mpc55xx_asm Assembler files
     
    3530.section ".entry", "ax"
    3631PUBLIC_VAR (start)
    37 start:
     32.globl  fmpll_syncr_vals
     33bam_rchw:
    3834/*
    3935 * BAM
     
    4137
    4238        /* BAM: RCHW */
    43         .int 0x5a0000
     39        .int 0x005a0000
    4440
    4541        /* BAM: Address of start instruction */
     
    4945 * Enable time base
    5046 */
    51 
     47start: 
    5248        li r0, 0
    5349        mtspr TBWU, r0
     
    6157 */
    6258
     59        LWI r3,fmpll_syncr_vals
    6360        bl SYM (mpc55xx_fmpll_reset_config)
    6461
     
    123120
    124121/*
    125  * Zero RAM
     122 * Zero RAM (needed to get proper ECC)
    126123 */
    127124
  • c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c

    r89bb075 r2f5435a4  
    159159}
    160160
    161 rtems_status_code mpc55xx_edma_init()
     161rtems_status_code mpc55xx_edma_init(void)
    162162{
    163163        rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    171171
    172172        /* Clear TCDs */
    173         memset( &EDMA.TCD [0], 0, sizeof( EDMA.TCD));
     173        memset( (void *)&EDMA.TCD [0], 0, sizeof( EDMA.TCD));
    174174
    175175        /* Error interrupt handlers */
  • c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c

    r89bb075 r2f5435a4  
    254254 * @brief Writes @a n characters from @a out to port @a minor.
    255255 *
    256  * @return Returns 0 on success or -1 otherwise.
    257  */
    258 static int mpc55xx_esci_termios_poll_write( int minor, const char *out, int n)
    259 {
    260         mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
    261         int i = 0;
     256 * @return Returns number of chars sent on success or -1 otherwise.
     257 */
     258static int mpc55xx_esci_termios_poll_write( int minor, const char *out,
     259                                            size_t n)
     260{
     261        mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
     262        size_t i = 0;
    262263
    263264        /* Check minor number */
     
    271272        }
    272273
    273         return 0;
     274        return n;
    274275}
    275276
     
    277278 * @brief Writes one character from @a out to port @a minor.
    278279 *
    279  * @return Returns always 0.
     280 * @return (always 0).
    280281 *
    281282 * @note The buffer @a out has to provide at least one character.
    282283 * This function assumes that the transmit data register is empty.
    283284 */
    284 static int mpc55xx_esci_termios_write( int minor, const char *out, int n)
     285static int mpc55xx_esci_termios_write( int minor, const char *out, size_t n)
    285286{
    286287        mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
     
    532533{
    533534        rtems_status_code sc = RTEMS_SUCCESSFUL;
    534         int rv = 0;
    535535        mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
    536536
  • c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h

    r89bb075 r2f5435a4  
    2525 * Register addresses
    2626 */
     27#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     28
     29#define FMPLL_SYNSR   0xFFFF0004
     30#define FMPLL_ESYNCR1 0xFFFF0008
     31#define FMPLL_ESYNCR2 0xFFFF000C
     32#define FLASH_BIUCR   0xFFFF801C
     33#define SIU_ECCR      0xFFFE8984
     34#define SIU_SRCR      0xFFFE8010
     35
     36#else /* ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
    2737
    2838#define FMPLL_SYNCR 0xC3F80000
     
    3242#define SIU_SRCR 0xC3F90010
    3343
     44#endif /*((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))*/
    3445/*
    3546 * Special purpose registers
  • c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h

    r89bb075 r2f5435a4  
    77 *
    88 * This file is based on the mpc5566.h header file provided by Freescale Semiconductor, INC.
     9 * with some added fields/structures/definitions for MPC5510
    910 */
     11
     12/* to get the chip derivate... */
     13#include <bspopts.h>
    1014
    1115/*
     
    345349/****************************************************************************/
    346350    struct FMPLL_tag {
    347         union {
     351        union SYNCR_tag {
    348352            uint32_t R;
    349353            struct {
     
    363367                uint32_t EXP:10;
    364368            } B;
    365         } SYNCR;
     369        } SYNCR; /* not present on MPC551x */
    366370
    367371        union {
     
    381385            } B;
    382386        } SYNSR;
     387
     388        union ESYNCR1_tag {
     389            uint32_t R;
     390            struct  {
     391                uint32_t:1;
     392                uint32_t CLKCFG:3;
     393                uint32_t:8;
     394                uint32_t EPREDIV:4;
     395                uint32_t :8;
     396                uint32_t EMFD:8;
     397            } B;
     398        } ESYNCR1; /* present on MPC551x */
     399
     400        union ESYNCR2_tag{
     401            uint32_t R;
     402            struct {
     403                uint32_t:8;
     404                uint32_t LOCEN:1;
     405                uint32_t LOLRE:1;
     406                uint32_t LOCRE:1;
     407                uint32_t LOLIRQ:1;
     408                uint32_t LOCIRQ:1;
     409                uint32_t:1;
     410                uint32_t ERATE:2;
     411                uint32_t:5;
     412                uint32_t DEPTH:3;
     413                uint32_t:2;
     414                uint32_t ERFD:6;
     415            } B;
     416        } ESYNCR2; /* present on MPC551x */
    383417
    384418    };
     
    43544388    };
    43554389
     4390#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     4391/* Define memories */
     4392
     4393#define SRAM_START  0x40000000
     4394#define SRAM_SIZE      0x14000
     4395#define SRAM_END    (SRAM_START+SRAM_SIZE-1)
     4396
     4397#define FLASH_START 0x00000000
     4398#define FLASH_SIZE    0x180000
     4399#define FLASH_END   (FLASH_START+FLASH_SIZE-1)
     4400
     4401/* Define instances of modules */
     4402#define EDMA      (*(volatile struct EDMA_tag *)      0xFFF44000)
     4403#define INTC      (*(volatile struct INTC_tag *)      0xFFF48000)
     4404
     4405#define EQADC     (*(volatile struct EQADC_tag *)     0xFFF80000)
     4406#define SOFTMLB   (*(volatile struct SOFTMLB_tag *)   0xFFF84000)
     4407#define I2C_A     (*(volatile struct I2C_tag *)       0xFFF88000)
     4408
     4409#define DSPI_A    (*(volatile struct DSPI_tag *)      0xFFF90000)
     4410#define DSPI_B    (*(volatile struct DSPI_tag *)      0xFFF94000)
     4411#define DSPI_C    (*(volatile struct DSPI_tag *)      0xFFF98000)
     4412#define DSPI_D    (*(volatile struct DSPI_tag *)      0xFFF9C000)
     4413
     4414#define ESCI_A    (*(volatile struct ESCI_tag *)      0xFFFA0000)
     4415#define ESCI_B    (*(volatile struct ESCI_tag *)      0xFFFA4000)
     4416#define ESCI_C    (*(volatile struct ESCI_tag *)      0xFFFA8000)
     4417#define ESCI_D    (*(volatile struct ESCI_tag *)      0xFFFAC000)
     4418#define ESCI_E    (*(volatile struct ESCI_tag *)      0xFFFB0000)
     4419#define ESCI_F    (*(volatile struct ESCI_tag *)      0xFFFB4000)
     4420#define ESCI_G    (*(volatile struct ESCI_tag *)      0xFFFB8000)
     4421#define ESCI_H    (*(volatile struct ESCI_tag *)      0xFFFBC000)
     4422
     4423#define CAN_A     (*(volatile struct FLEXCAN2_tag *)  0xFFFC0000)
     4424#define CAN_B     (*(volatile struct FLEXCAN2_tag *)  0xFFFC4000)
     4425#define CAN_C     (*(volatile struct FLEXCAN2_tag *)  0xFFFC8000)
     4426#define CAN_D     (*(volatile struct FLEXCAN2_tag *)  0xFFFCC000)
     4427#define CAN_D     (*(volatile struct FLEXCAN2_tag *)  0xFFFD0000)
     4428#define CAN_D     (*(volatile struct FLEXCAN2_tag *)  0xFFFD4000)
     4429
     4430#define EMIOS     (*(volatile struct EMIOS_tag *)     0xFFFE4000)
     4431#define SIU       (*(volatile struct SIU_tag *)       0xFFFE8000)
     4432#define CRP       (*(volatile struct CRP_tag *)       0xFFFEC000)
     4433
     4434#define FMPLL     (*(volatile struct FMPLL_tag *)     0xFFFF0000)
     4435#define EBI       (*(volatile struct EBI_tag *)       0xFFFF4000)
     4436#define FLASH     (*(volatile struct FLASH_tag *)     0xFFFF8000)
     4437
     4438#else /* ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517)) */
    43564439/* Define memories */
    43574440
    43584441#define SRAM_START  0x40000000
    43594442#define SRAM_SIZE      0x20000
    4360 #define SRAM_END    0x4001FFFF
     4443#define SRAM_END    (SRAM_START+SRAM_SIZE-1)
    43614444
    43624445#define FLASH_START         0x0
     
    44014484
    44024485#define FEC     (*(volatile struct FEC_tag *)  0xFFF4C000)
     4486#endif
    44034487
    44044488#define MPC55XX_ZERO_FLAGS { .R = 0 }
  • c/src/lib/libcpu/powerpc/mpc55xx/misc/fmpll.S

    r89bb075 r2f5435a4  
    2121#include <libcpu/powerpc-utility.h>
    2222#include <mpc55xx/reg-defs.h>
    23 
     23#include <bspopts.h>
     24       
    2425.section ".text"
    2526
     
    2728.equ FMPLL_TIMEOUT, 6000
    2829
    29 /* Reference clock */
    30 .equ FMPLL_REF_CLOCK, 8000000
    31 
    32 /* Settings for FMPLL from 12 MHz up to 128 MHz with 8 MHz reference frequency */
    33 .equ FMPLL_128_8_SYNCR_SETTING_0, (FMPLL_SYNCR_PREDIV_0 | FMPLL_SYNCR_MFD_12 | FMPLL_SYNCR_RFD_2 | FMPLL_SYNCR_LOCEN)
    34 .equ FMPLL_128_8_SYNCR_SETTING_1, (FMPLL_SYNCR_PREDIV_0 | FMPLL_SYNCR_MFD_12 | FMPLL_SYNCR_RFD_0 | FMPLL_SYNCR_LOCEN)
    35 
    3630.macro DO_SETTING setting
    37         LWI r5, FMPLL_128_8_SYNCR_SETTING_\setting
     31        lwz r5, \setting
    3832        stw r5, 0(r4)
    3933        msync
     
    4943GLOBAL_FUNCTION mpc55xx_fmpll_reset_config
    5044        /* Save link register */
    51         mflr r3
     45        mflr r9
     46
     47#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     48        /*
     49         * for MPC5510: pass in ptr to array with:
     50         * off 0:  temp setting for ESYNCR2
     51         * off 4: final setting for ESYNCR2
     52         * off 8: final setting for ESYNCR1
     53         */
     54        LA r4, FMPLL_ESYNCR2
     55
     56        DO_SETTING 0(r3)
     57
     58        lwz r5, 8(r3)
     59        stw r5, (FMPLL_ESYNCR1-FMPLL_ESYNCR2)(r4)       
     60        msync
     61
     62        DO_SETTING 4(r3)
     63
     64#else
     65        /*
     66         * for MPC5566: pass in ptr to array with:
     67         * off 0:  temp setting for SYNCR
     68         * off 4: final setting for SYNCR
     69         */
    5270
    5371        LA r4, FMPLL_SYNCR
    5472
    55         DO_SETTING 0
    56         DO_SETTING 1
    57 
     73        DO_SETTING 0(r3)
     74        DO_SETTING 4(r3)
     75#endif
    5876        /* Enable loss-of-clock and loss-of-lock IRQs */
    5977        lwz r5, 0(r4)
     
    6785
    6886        /* Restore link register and return */
    69         mtlr r3
     87        mtlr r9
    7088        blr
    7189
     
    89107        b mpc55xx_system_reset
    90108fmpll_continue:
    91         lwz r8, 0(r6)
    92         and. r8, r8, r7
     109        lwz r5, 0(r6)
     110        and. r5, r5, r7
    93111        beq fmpll_not_locked
    94112
     
    100118 */
    101119GLOBAL_FUNCTION mpc55xx_get_system_clock
     120#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
     121        LA r4, FMPLL_ESYNCR1
     122        lwz r3, 0(r4)
     123        /* EPREDIV */
     124        rlwinm r5, r3,16, 28, 31
     125
     126        /* MFD */
     127        rlwinm r6, r3,32, 24, 31
     128
     129        LA r4, FMPLL_ESYNCR2
     130        lwz r3, 0(r4)
     131        /* ERFD */
     132        rlwinm r7, r3,32, 26, 31
     133
     134        LWI r8, MPC55XX_FMPLL_REF_CLOCK
     135        addi r5, r5, 1
     136        addi r6, r6,16
     137        addi r7, r7, 1
     138        mullw r6, r6, r8
     139        divw r3, r6, r5
     140        divw r3, r3, r7
     141       
     142#else
    102143        LA r4, FMPLL_SYNCR
    103144        lwz r3, 0(r4)
     
    111152        /* RFD */
    112153        rlwinm r7, r3, 13, 29, 31
    113 
    114154        /* Calculate system clock (Table 11-10 [MPC5567 Microcontroller Reference Manual]) */
    115         LWI r8, FMPLL_REF_CLOCK
     155        LWI r8, MPC55XX_FMPLL_REF_CLOCK
    116156        addi r5, r5, 1
    117157        addi r6, r6, 4
     
    119159        sraw r6, r6, r7
    120160        divw r3, r6, r5
     161#endif
    121162
    122163        blr
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