Changeset 2e7ed911 in rtems
- Timestamp:
- 05/22/01 23:20:14 (22 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d26dce2
- Parents:
- a355e3ea
- Location:
- c/src/lib/libcpu/mips
- Files:
-
- 1 deleted
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/mips/ChangeLog
ra355e3ea r2e7ed911 1 2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov> 2 3 * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. 4 * mongoosev/duart/mg5uart.c, mongoosev/duart/mg5uart.h, 5 mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, 6 shared/interrupts/maxvectors.c: Now works. Significant rework 7 of exceptions and interrupt vectoring to clean things up. 8 * shared/interrupts/vectorexceptions.c: Removed. 9 1 10 2001-05-07 Joel Sherrill <joel@OARcorp.com> 2 11 -
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
ra355e3ea r2e7ed911 46 46 /* #define MG5UART_STATIC static */ 47 47 48 49 48 50 #define MG5UART_SETREG( _base, _register, _value ) \ 49 51 MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) … … 51 53 #define MG5UART_GETREG( _base, _register ) \ 52 54 MONGOOSEV_READ_REGISTER( _base, _register ) 55 53 56 54 57 /* … … 74 77 */ 75 78 76 MG5UART_STATIC int mg5uart_set_attributes( 79 MG5UART_STATIC int mg5uart_set_attributes( 77 80 int minor, 78 81 const struct termios *t … … 81 84 unsigned32 pMG5UART_port; 82 85 unsigned32 pMG5UART; 83 unsigned int cmd;84 unsigned intbaudcmd;85 unsigned int portshift;86 unsigned32 cmd, cmdSave; 87 unsigned32 baudcmd; 88 unsigned32 shift; 86 89 rtems_interrupt_level Irql; 87 90 … … 104 107 */ 105 108 106 cmd = MONGOOSEV_UART_CMD_ TX_ENABLE | MONGOOSEV_UART_CMD_TX_ENABLE;109 cmd = MONGOOSEV_UART_CMD_RX_ENABLE | MONGOOSEV_UART_CMD_TX_ENABLE; 107 110 108 111 /* … … 126 129 if (t->c_cflag & CSIZE) { 127 130 switch (t->c_cflag & CSIZE) { 128 case CS5: 129 case CS6: 130 case CS7: 131 case CS5: 132 case CS6: 133 case CS7: 131 134 return -1; 132 135 break; … … 134 137 /* Mongoose-V only supports CS8 */ 135 138 break; 136 139 137 140 } 138 141 } /* else default to CS8 */ … … 141 144 * Stop Bits 142 145 */ 143 146 144 147 #if 0 145 148 if (t->c_cflag & CSTOPB) { … … 160 163 161 164 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 162 portshift = MONGOOSEV_UART0_CMD_SHIFT;165 shift = MONGOOSEV_UART0_CMD_SHIFT; 163 166 else 164 portshift = MONGOOSEV_UART1_CMD_SHIFT; 167 shift = MONGOOSEV_UART1_CMD_SHIFT; 168 169 165 170 166 171 rtems_interrupt_disable(Irql); 167 MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmd << portshift ); 168 MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); 172 173 cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); 174 175 MG5UART_SETREG( pMG5UART, 176 MG5UART_COMMAND_REGISTER, 177 (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); 178 179 MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); 180 169 181 rtems_interrupt_enable(Irql); 170 182 return 0; … … 185 197 unsigned int pMG5UART; 186 198 unsigned int pMG5UART_port; 187 199 188 200 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; 189 201 pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2; … … 192 204 193 205 for (port=0 ; port<Console_Port_Count ; port++ ) { 194 if ( Console_Port_Tbl[port].ulCtrlPort1 == pMG5UART && 206 if ( Console_Port_Tbl[port].ulCtrlPort1 == pMG5UART && 195 207 Console_Port_Tbl[port].ulCtrlPort2 != pMG5UART_port ) { 196 208 pmg5uartContext->mate = port; … … 209 221 MG5UART_STATIC void mg5uart_init(int minor) 210 222 { 211 unsigned32 pMG5UART_port; 212 unsigned32 pMG5UART; 223 unsigned32 pMG5UART_port; 224 unsigned32 pMG5UART; 225 unsigned32 cmdSave; 226 unsigned32 shift; 227 213 228 mg5uart_context *pmg5uartContext; 214 229 … … 222 237 pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2; 223 238 224 /* 225 * Reset everything and leave this port disabled. 226 */ 227 228 MG5UART_SETREG( pMG5UART, 0, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS ); 239 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 240 shift = MONGOOSEV_UART0_CMD_SHIFT; 241 else 242 shift = MONGOOSEV_UART1_CMD_SHIFT; 243 244 /* 245 * Disable the uart and leave this port disabled. 246 */ 247 248 cmdSave = MG5UART_GETREG(pMG5UART, MG5UART_COMMAND_REGISTER) & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift); 249 250 MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmdSave ); 229 251 230 252 /* 231 253 * Disable interrupts on RX and TX for this port 232 254 */ 233 234 255 mg5uart_enable_interrupts( minor, MG5UART_DISABLE_ALL ); 235 256 } … … 249 270 ) 250 271 { 251 unsigned32 pMG5UART; 252 unsigned32 pMG5UART_port; 253 unsigned int vector; 254 unsigned int cmd; 255 unsigned int baudcmd; 256 unsigned int portshift; 272 unsigned32 pMG5UART; 273 unsigned32 pMG5UART_port; 274 unsigned32 vector; 275 unsigned32 cmd, cmdSave; 276 unsigned32 baudcmd; 277 unsigned32 shift; 278 257 279 rtems_interrupt_level Irql; 258 280 … … 261 283 vector = Console_Port_Tbl[minor].ulIntVector; 262 284 285 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 286 shift = MONGOOSEV_UART0_CMD_SHIFT; 287 else 288 shift = MONGOOSEV_UART1_CMD_SHIFT; 289 290 263 291 /* XXX default baud rate could be from configuration table */ 264 292 … … 267 295 /* 268 296 * Set the DUART channel to a default useable state 269 * B 9600, 8Nx since there is no stop bit control.297 * B19200, 8Nx since there is no stop bit control. 270 298 */ 271 299 272 300 cmd = MONGOOSEV_UART_CMD_TX_ENABLE | MONGOOSEV_UART_CMD_RX_ENABLE; 273 301 274 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 )275 portshift = MONGOOSEV_UART0_CMD_SHIFT;276 else277 portshift = MONGOOSEV_UART1_CMD_SHIFT;278 279 302 rtems_interrupt_disable(Irql); 280 MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmd << portshift ); 281 MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); 303 304 cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); 305 306 MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); 307 308 MG5UART_SETREG( pMG5UART, 309 MG5UART_COMMAND_REGISTER, 310 cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); 311 282 312 rtems_interrupt_enable(Irql); 283 313 … … 297 327 ) 298 328 { 299 unsigned32 pMG5UART; 300 unsigned32 pMG5UART_port; 301 unsigned int cmd; 302 unsigned int portshift; 329 unsigned32 pMG5UART; 330 unsigned32 pMG5UART_port; 331 unsigned32 cmd, cmdSave; 332 unsigned32 shift; 333 rtems_interrupt_level Irql; 303 334 304 335 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; … … 314 345 315 346 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 316 portshift = MONGOOSEV_UART0_CMD_SHIFT;347 shift = MONGOOSEV_UART0_CMD_SHIFT; 317 348 else 318 portshift = MONGOOSEV_UART1_CMD_SHIFT; 319 320 MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmd << portshift ); 349 shift = MONGOOSEV_UART1_CMD_SHIFT; 350 351 352 rtems_interrupt_disable(Irql); 353 cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); 354 355 MG5UART_SETREG( pMG5UART, 356 MG5UART_COMMAND_REGISTER, 357 (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); 358 rtems_interrupt_enable(Irql); 321 359 322 360 return(RTEMS_SUCCESSFUL); 323 361 } 324 362 325 /* 363 364 365 366 /* 326 367 * mg5uart_write_polled 327 368 * … … 330 371 331 372 MG5UART_STATIC void mg5uart_write_polled( 332 int minor, 373 int minor, 333 374 char c 334 375 ) … … 351 392 * wait for transmitter holding register to be empty 352 393 */ 353 timeout = 1000; 354 status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER); 355 while ( 1 ) { 394 timeout = 2000; 395 396 while( --timeout ) 397 { 356 398 status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; 357 358 if ( (status & (MONGOOSEV_UART_TX_READY|MONGOOSEV_UART_TX_EMPTY_0)) == 359 (MONGOOSEV_UART_TX_READY|MONGOOSEV_UART_TX_EMPTY_0) ) 399 400 /* 401 if ( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) == 402 (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY) ) 360 403 break; 404 */ 405 406 if( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) ) 407 break; 361 408 362 409 /* … … 365 412 366 413 #if 0 367 if(_System_state_Is_up(_System_state_Get())) { 414 if(_System_state_Is_up(_System_state_Get())) 415 { 368 416 rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); 369 417 } 370 418 #endif 371 if(!--timeout) {372 break;373 }374 419 } 375 420 … … 380 425 MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c); 381 426 } 427 428 429 382 430 383 431 /* … … 389 437 * 390 438 * NOTE: Yes .. this is ugly but it provides 5 interrupt source 391 * wrappers which are nearly functionally identical. 439 * wrappers which are nearly functionally identical. 392 440 */ 393 441 … … 402 450 ) \ 403 451 { \ 404 int minor; \ 452 int minor; \ 453 extern void mips_default_isr(int vector); \ 405 454 \ 406 455 for(minor=0 ; minor<Console_Port_Count ; minor++) { \ … … 408 457 vector == Console_Port_Tbl[minor].ulIntVector + _OFFSET ) { \ 409 458 mg5uart_process_isr_ ## _TYPE (minor); \ 459 return; \ 410 460 } \ 411 461 } \ 462 mips_default_isr( vector ); \ 412 463 } 413 464 … … 417 468 __ISR(tx_ready, MG5UART_IRQ_TX_READY) 418 469 __ISR(rx_ready, MG5UART_IRQ_RX_READY) 419 420 421 MG5UART_STATIC void mg5uart_process_isr_rx_frame_error( 422 int minor 470 471 472 473 474 475 MG5UART_STATIC void mg5uart_process_isr_rx_error( 476 int minor, 477 unsigned32 mask 423 478 ) 424 479 { … … 436 491 437 492 MG5UART_SETREG( 438 pMG5UART, 439 MG5UART_STATUS_REGISTER, 440 MONGOOSEV_UART_RX_FRAME_ERROR << shift 441 ); 493 pMG5UART, 494 MG5UART_STATUS_REGISTER, 495 mask << shift ); 496 } 497 498 499 MG5UART_STATIC void mg5uart_process_isr_rx_frame_error( 500 int minor 501 ) 502 { 503 mg5uart_process_isr_rx_error( minor, MONGOOSEV_UART_RX_FRAME_ERROR ); 442 504 } 443 505 … … 446 508 ) 447 509 { 448 unsigned32 pMG5UART; 449 int shift; 450 451 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; 452 453 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 454 shift = MONGOOSEV_UART0_IRQ_SHIFT; 455 else 456 shift = MONGOOSEV_UART1_IRQ_SHIFT; 457 458 /* now clear the error */ 459 460 MG5UART_SETREG( 461 pMG5UART, 462 MG5UART_STATUS_REGISTER, 463 MONGOOSEV_UART_RX_OVERRUN_ERROR << shift 464 ); 465 } 510 mg5uart_process_isr_rx_error( minor, MONGOOSEV_UART_RX_OVERRUN_ERROR ); 511 } 512 513 514 515 516 517 518 466 519 467 520 MG5UART_STATIC void mg5uart_process_tx_isr( 468 int minor, 469 unsigned32 source_mask 470 ); 521 int minor, 522 unsigned32 source 523 ) 524 { 525 unsigned32 pMG5UART; 526 int shift; 527 528 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; 529 530 mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); 531 532 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 533 shift = MONGOOSEV_UART0_IRQ_SHIFT; 534 else 535 shift = MONGOOSEV_UART1_IRQ_SHIFT; 536 537 MG5UART_SETREG( 538 pMG5UART, 539 MG5UART_STATUS_REGISTER, 540 source << shift ); 541 542 if( rtems_termios_dequeue_characters( Console_Port_Data[minor].termios_data, 1) ) 543 { 544 mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL); 545 return; 546 } 547 548 /* 549 * There are no more characters to transmit. The tx interrupts are be cleared 550 * by writing data to the uart, so just disable the tx interrupt sources. 551 */ 552 553 Console_Port_Data[minor].bActive = FALSE; 554 555 /* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */ 556 } 557 558 471 559 472 560 MG5UART_STATIC void mg5uart_process_isr_tx_empty( … … 474 562 ) 475 563 { 476 mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_EMPTY );564 /* mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_EMPTY ); */ 477 565 } 478 566 … … 481 569 ) 482 570 { 483 mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_READY ); 484 } 485 486 MG5UART_STATIC void mg5uart_process_tx_isr( 487 int minor, 488 unsigned32 source_mask 489 ) 490 { 491 unsigned32 pMG5UART; 492 int shift; 493 494 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; 495 496 if (!rtems_termios_dequeue_characters( 497 Console_Port_Data[minor].termios_data, 1)) 498 return; 499 500 501 /* 502 * There are no more characters to transmit so clear the interrupt 503 * source and disable TX interrupts. 504 */ 505 506 Console_Port_Data[minor].bActive = FALSE; 507 508 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 509 shift = MONGOOSEV_UART0_IRQ_SHIFT; 510 else 511 shift = MONGOOSEV_UART1_IRQ_SHIFT; 512 513 /* now clear the interrupt source */ 514 515 MG5UART_SETREG( 516 pMG5UART, 517 MG5UART_STATUS_REGISTER, 518 source_mask << shift 519 ); 520 521 mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); 522 523 } 571 mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_READY ); 572 } 573 574 575 576 524 577 525 578 MG5UART_STATIC void mg5uart_process_isr_rx_ready( … … 532 585 pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2; 533 586 587 /* reading the RX buffer automatically resets the interrupt flag */ 588 534 589 c = (unsigned char) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER); 590 535 591 rtems_termios_enqueue_raw_characters( 536 Console_Port_Data[minor].termios_data, 537 &c, 538 1 539 ); 540 541 /* reading the RX buffer automatically resets the error */ 542 } 592 Console_Port_Data[minor].termios_data, 593 &c, 1 ); 594 } 595 596 597 598 599 543 600 544 601 /* … … 566 623 } 567 624 568 /* 625 626 627 628 629 /* 569 630 * mg5uart_write_support_int 570 631 * … … 573 634 574 635 MG5UART_STATIC int mg5uart_write_support_int( 575 int minor, 576 const char *buf, 636 int minor, 637 const char *buf, 577 638 int len 578 639 ) … … 589 650 590 651 if ( !len ) 591 return 0;652 return 0; 592 653 593 654 /* … … 596 657 597 658 rtems_interrupt_disable(Irql); 598 if ( Console_Port_Data[minor].bActive == FALSE ) { 599 Console_Port_Data[minor].bActive = TRUE; 600 mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL); 601 } 602 MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf); 659 660 MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf); 661 662 if( Console_Port_Data[minor].bActive == FALSE ) 663 { 664 Console_Port_Data[minor].bActive = TRUE; 665 mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL); 666 } 667 603 668 rtems_interrupt_enable(Irql); 604 605 669 return 1; 606 670 } 607 671 608 /* 672 673 674 675 /* 609 676 * mg5uart_write_support_polled 610 677 * … … 614 681 615 682 MG5UART_STATIC int mg5uart_write_support_polled( 616 int minor, 617 const char *buf, 683 int minor, 684 const char *buf, 618 685 int len 619 686 ) … … 624 691 * poll each byte in the string out of the port. 625 692 */ 626 while (nwrite < len) { 627 /* 628 * transmit character 629 */ 693 while (nwrite < len) 694 { 630 695 mg5uart_write_polled(minor, *buf++); 631 696 nwrite++; … … 638 703 } 639 704 640 /* 641 * mg5uart_inbyte_nonblocking_polled 705 /* 706 * mg5uart_inbyte_nonblocking_polled 642 707 * 643 708 * Console Termios polling input entry point. 644 709 */ 645 710 646 MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled( 647 int minor 711 MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled( 712 int minor 648 713 ) 649 714 { … … 651 716 unsigned32 pMG5UART_port; 652 717 unsigned32 status; 653 intshift;718 unsigned32 tmp,shift; 654 719 655 720 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; … … 661 726 shift = MONGOOSEV_UART1_IRQ_SHIFT; 662 727 728 /* reset overrrun or framing errors */ 663 729 status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; 664 if ( status & MONGOOSEV_UART_RX_READY ) { 665 return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER); 666 } else { 667 return -1; 730 731 if( (tmp = (status & 0x3)) ) 732 { 733 MG5UART_SETREG(pMG5UART, MG5UART_STATUS_REGISTER, (tmp << shift) ); 734 status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; 735 } 736 737 if ( status & MONGOOSEV_UART_RX_READY ) 738 { 739 return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER); 740 } 741 else 742 { 743 return -1; 668 744 } 669 745 } … … 686 762 if (!baud_requested) 687 763 baud_requested = B9600; /* default to 9600 baud */ 688 764 689 765 baud_requested = termios_baud_to_number( baud_requested ); 690 766 … … 695 771 /* 696 772 * Formula is Code = round(ClockFrequency / Baud - 1). 773 * 774 * Since this is integer math, we will divide by twice the baud and 775 * check the remaining odd bit. 697 776 */ 698 777 … … 703 782 * That is 100 cycles which is not a lot of instructions. It is 704 783 * reasonable to think that the Mongoose-V could not keep 705 * up with C < 200.784 * up with C < 100. 706 785 */ 707 786 … … 714 793 715 794 *code = (tmp_code << 16) | tmp_code; 795 716 796 return 0; 717 797 } 798 799 800 718 801 719 802 /* … … 729 812 { 730 813 unsigned32 pMG5UART; 731 unsigned32 shifted_mask; 732 unsigned32 shifted_bits; 814 unsigned32 maskSave; 815 unsigned32 shift; 816 rtems_interrupt_level Irql; 733 817 734 818 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; … … 738 822 */ 739 823 740 shifted_bits = MONGOOSEV_UART_ALL_IRQ_BITS; 741 shifted_mask = mask; 742 743 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) { 744 shifted_bits <<= MONGOOSEV_UART0_IRQ_SHIFT; 745 shifted_mask <<= MONGOOSEV_UART0_IRQ_SHIFT; 746 } else { 747 shifted_bits <<= MONGOOSEV_UART1_IRQ_SHIFT; 748 shifted_mask <<= MONGOOSEV_UART1_IRQ_SHIFT; 749 } 750 751 MONGOOSEV_ATOMIC_MASK( 752 MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 753 shifted_bits, 754 shifted_mask 755 ); 756 } 824 if ( Console_Port_Tbl[minor].ulDataPort == MG5UART_UART0 ) 825 shift = MONGOOSEV_UART0_IRQ_SHIFT; 826 else 827 shift = MONGOOSEV_UART1_IRQ_SHIFT; 828 829 830 rtems_interrupt_disable(Irql); 831 832 maskSave = MG5UART_GETREG( pMG5UART, MG5UART_INTERRUPT_MASK_REGISTER ); 833 834 MG5UART_SETREG( 835 pMG5UART, 836 MG5UART_INTERRUPT_MASK_REGISTER, 837 (maskSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (mask << shift) ); 838 839 rtems_interrupt_enable(Irql); 840 } 841 842 757 843 758 844 /* … … 786 872 }; 787 873 874 -
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h
ra355e3ea r2e7ed911 35 35 36 36 /* shared registers from peripheral base (i.e. from ulCtrlPort1) */ 37 #define MG5UART_COMMAND_REGISTER 0x00 37 /* 38 #define MG5UART_COMMAND_REGISTER 0 39 #define MG5UART_STATUS_REGISTER 1 40 #define MG5UART_INTERRUPT_CAUSE_REGISTER 2 41 #define MG5UART_INTERRUPT_MASK_REGISTER 3 42 */ 43 44 #define MG5UART_COMMAND_REGISTER 0 38 45 #define MG5UART_STATUS_REGISTER 0x04 39 46 #define MG5UART_INTERRUPT_CAUSE_REGISTER 0x08 40 #define MG5UART_INTERRUPT_MASK_REGISTER 0x0 c47 #define MG5UART_INTERRUPT_MASK_REGISTER 0x0C 41 48 42 49 /* port specific registers from uart base (i.e. from ulCtrlPort2) */ 43 #define MG5UART_RX_BUFFER 0x0044 #define MG5UART_TX_BUFFER 0x0445 #define MG5UART_BAUD_RATE 0x0850 #define MG5UART_RX_BUFFER 0 51 #define MG5UART_TX_BUFFER 4 52 #define MG5UART_BAUD_RATE 8 46 53 47 54 /* … … 50 57 51 58 #define MG5UART_ENABLE_ALL_EXCEPT_TX MONGOOSEV_UART_ALL_RX_STATUS_BITS 52 #define MG5UART_ENABLE_ALL (MONGOOSEV_UART_ALL_STATUS_BITS) 59 60 /* all rx ints on, but only tx ready. no need to also int on tx empty */ 61 #define MG5UART_ENABLE_ALL (MONGOOSEV_UART_ALL_STATUS_BITS & ~MONGOOSEV_UART_TX_EMPTY) 62 53 63 #define MG5UART_DISABLE_ALL 0x0000 54 64 -
c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
ra355e3ea r2e7ed911 19 19 */ 20 20 21 21 22 #define MONGOOSEV_READ( _base ) \ 22 *((volatile unsigned32 *)(_base))23 ( *((volatile unsigned32 *)(_base)) ) 23 24 24 25 #define MONGOOSEV_WRITE( _base, _value ) \ 25 *((volatile unsigned32 *)(_base)) = (_value)26 ( *((volatile unsigned32 *)(_base)) = (_value) ) 26 27 27 28 #define MONGOOSEV_READ_REGISTER( _base, _register ) \ 28 *((volatile unsigned32 *)((_base) + (_register)))29 ( *((volatile unsigned32 *)((_base) + (_register))) ) 29 30 30 31 #define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \ 31 *((volatile unsigned32 *)((_base) + (_register))) = (_value)32 33 #define MONGOOSEV_ATOMIC_MASK( _addr, _mask, _new ) \ 34 do { \ 35 rtems_interrupt_level Irql; \ 36 rtems_unsigned32 tmp; \ 37 \ 38 rtems_interrupt_disable(Irql); \39 tmp = *((volatile unsigned32 *)(_addr)) & ~(_mask); \40 *((volatile unsigned32 *)(_addr)) = tmp | (_new); \ 41 rtems_interrupt_enable(Irql); \ 42 } while (0) 32 ( *((volatile unsigned32 *)((_base) + (_register))) = (_value) ) 33 34 35 36 37 38 /* 39 * Macros to read/write the Mongoose FPU control register. 40 */ 41 42 43 43 44 44 45 /* … … 62 63 #define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 0xFFFE018C 63 64 64 #define MONGOOSEV_PFICR MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER 65 #define MONGOOSEV_PFIMR MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 66 67 #define mongoosev_set_in_pficr( _mask, _bits ) \ 68 MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFICR, _mask, _bits ) 69 #define mongoosev_clear_in_pficr( _mask, _bits ) \ 70 MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFICR, _mask, ~(_bits) ) 71 72 #define mongoosev_set_in_pfimr( _mask, _bits ) \ 73 MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFIMR, _mask, _bits ) 74 #define mongoosev_clear_in_pfimr( _mask, _bits ) \ 75 MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFIMR, _mask, ~(_bits) ) 65 #define MONGOOSEV_WATCHDOG 0xBE000000 76 66 77 67 /* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */ 78 #define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 79 #define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 80 #define MONGOOSEV_UART_CMD_LOOPBACK_RXTX 81 82 #define MONGOOSEV_UART_CMD_ TX_ENABLE0x00183 #define MONGOOSEV_UART_CMD_ TX_DISABLE0x00084 #define MONGOOSEV_UART_CMD_ RX_ENABLE0x00285 #define MONGOOSEV_UART_CMD_ RX_DISABLE0x00086 #define MONGOOSEV_UART_CMD_TX_READY 87 #define MONGOOSEV_UART_CMD_PARITY_ENABLE 88 #define MONGOOSEV_UART_CMD_PARITY_DISABLE 89 #define MONGOOSEV_UART_CMD_PARITY_EVEN 0x80090 #define MONGOOSEV_UART_CMD_PARITY_ODD 68 #define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 0x0001 69 #define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 0x0002 70 #define MONGOOSEV_UART_CMD_LOOPBACK_RXTX 0x0004 71 72 #define MONGOOSEV_UART_CMD_RX_ENABLE 0x001 73 #define MONGOOSEV_UART_CMD_RX_DISABLE 0x000 74 #define MONGOOSEV_UART_CMD_TX_ENABLE 0x002 75 #define MONGOOSEV_UART_CMD_TX_DISABLE 0x000 76 #define MONGOOSEV_UART_CMD_TX_READY 0x004 77 #define MONGOOSEV_UART_CMD_PARITY_ENABLE 0x008 78 #define MONGOOSEV_UART_CMD_PARITY_DISABLE 0x000 79 #define MONGOOSEV_UART_CMD_PARITY_EVEN 0x010 80 #define MONGOOSEV_UART_CMD_PARITY_ODD 0x000 91 81 92 82 #define MONGOOSEV_UART0_CMD_SHIFT 5 … … 130 120 #define MONGOOSEV_UART_RX_READY 0x0010 131 121 132 #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x00 03122 #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013 133 123 #define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F 134 #define MONGOOSEV_UART_ALL_IRQ_BITS 0x001F135 124 136 125 /* … … 174 163 #define MONGOOSEV_EDAC_SERR_BIT 0x80000000 175 164 #define MONGOOSEV_EDAC_MERR_BIT 0x40000000 165 #define MONGOOSEV_MAVN_WRITE_ACCESS 0x00800000 166 #define MONGOOSEV_MAVN_READ_ACCESS 0x00400000 176 167 /* 29 - 24 reserved */ 168 #define MONGOOSEV_UART_1_RX_READY 0x00200000 169 #define MONGOOSEV_UART_1_TX_READY 0x00100000 170 #define MONGOOSEV_UART_1_TX_EMPTY 0x00080000 171 #define MONGOOSEV_UART_1_RX_OVERRUN 0x00040000 172 #define MONGOOSEV_UART_1_FRAME_ERROR 0x00020000 173 #define MONGOOSEV_RESERVED_16 0x00010000 177 174 #define MONGOOSEV_UART_0_RX_READY 0x00008000 178 175 #define MONGOOSEV_UART_0_TX_READY 0x00004000 … … 180 177 #define MONGOOSEV_UART_0_RX_OVERRUN 0x00001000 181 178 #define MONGOOSEV_UART_0_FRAME_ERROR 0x00000800 182 #define MONGOOSEV_UART_0_RESERVED 0x00000400 183 #define MONGOOSEV_UART_1_RX_READY 0x00200000 184 #define MONGOOSEV_UART_1_TX_READY 0x00100000 185 #define MONGOOSEV_UART_1_TX_EMPTY 0x00080000 186 #define MONGOOSEV_UART_1_RX_OVERRUN 0x00040000 187 #define MONGOOSEV_UART_1_FRAME_ERROR 0x00020000 188 #define MONGOOSEV_UART_1_RESERVED 0x00010000 189 #define MONGOOSEV_MAVN_WRITE_ACCESS 0x00400000 190 #define MONGOOSEV_MAVN_READ_ACCESS 0x00800000 179 #define MONGOOSEV_RESERVED_10 0x00000400 191 180 #define MONGOOSEV_EXTERN_INT_9 0x00000200 192 181 #define MONGOOSEV_EXTERN_INT_8 0x00000100 … … 265 254 #define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1 266 255 #define MONGOOSEV_IRQ_INT2 2 267 #define MONGOOSEV_IRQ_INT4 3 256 #define MONGOOSEV_IRQ_INT3 3 257 #define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3 258 259 #define MONGOOSEV_IRQ_INT4 4 260 268 261 /* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */ 269 #define MONGOOSEV_IRQ_PERIPHERAL_BASE 4 270 #define MONGOOSEV_IRQ_XINT0 4 271 #define MONGOOSEV_IRQ_XINT1 5 272 #define MONGOOSEV_IRQ_XINT2 6 273 #define MONGOOSEV_IRQ_XINT3 7 274 #define MONGOOSEV_IRQ_XINT4 8 275 #define MONGOOSEV_IRQ_XINT5 9 276 #define MONGOOSEV_IRQ_XINT6 10 277 #define MONGOOSEV_IRQ_XINT7 11 278 #define MONGOOSEV_IRQ_XINT8 12 279 #define MONGOOSEV_IRQ_XINT9 13 280 #define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION 14 281 #define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION 15 282 #define MONGOOSEV_IRQ_RESERVED_BIT_12 16 283 #define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR 17 284 #define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR 18 285 #define MONGOOSEV_IRQ_UART1_TX_EMPTY 19 286 #define MONGOOSEV_IRQ_UART1_TX_READY 20 287 #define MONGOOSEV_IRQ_UART1_RX_READY 21 288 #define MONGOOSEV_IRQ_RESERVED_BIT_18 22 289 #define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR 23 290 #define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR 24 291 #define MONGOOSEV_IRQ_UART0_TX_EMPTY 25 292 #define MONGOOSEV_IRQ_UART0_TX_READY 26 293 #define MONGOOSEV_IRQ_UART0_RX_READY 27 294 #define MONGOOSEV_IRQ_RESERVED_24 28 295 #define MONGOOSEV_IRQ_RESERVED_25 29 296 #define MONGOOSEV_IRQ_RESERVED_26 30 297 #define MONGOOSEV_IRQ_RESERVED_27 31 298 #define MONGOOSEV_IRQ_RESERVED_28 32 299 #define MONGOOSEV_IRQ_RESERVED_29 33 300 #define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR 34 301 #define MONGOOSEV_IRQ_CORRECTABLE_ERROR 35 302 303 #define MONGOOSEV_IRQ_SOFTWARE_1 36 304 #define MONGOOSEV_IRQ_SOFTWARE_2 37 262 #define MONGOOSEV_IRQ_PERIPHERAL_BASE 5 263 #define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0 264 #define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1 265 #define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2 266 #define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3 267 #define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4 268 #define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5 269 #define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6 270 #define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7 271 #define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8 272 #define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9 273 #define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10 274 #define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11 275 #define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12 276 #define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13 277 #define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14 278 #define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15 279 #define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16 280 #define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17 281 #define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18 282 #define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19 283 #define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20 284 #define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21 285 #define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22 286 #define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23 287 #define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24 288 #define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25 289 #define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26 290 #define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27 291 #define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28 292 #define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29 293 #define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30 294 #define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31 295 296 #define MONGOOSEV_IRQ_SOFTWARE_1 37 297 #define MONGOOSEV_IRQ_SOFTWARE_2 38 298 299 300 /* gdm, 5/14. Added exception vectoring to the ISR table- these 301 entries are never called by the ISR servicing, only by the exception 302 servicing routine. The ISR table is used because vector setup there 303 is already supported. Please note exception routines are passed 2 304 parameters; one of the below vectors and a pointer to the exception's 305 stack frame, the register layout of which is found in 306 307 exec/score/cpu/mips/iregdef.h 308 309 in conjunction with 310 311 exec/score/cpu/mips/cpu_asm.S 312 313 */ 314 315 #define MONGOOSEV_EXCEPTION_BASE 39 316 317 #define MONGOOSEV_EXCEPTION_ADEL MONGOOSEV_EXCEPTION_BASE+0 318 #define MONGOOSEV_EXCEPTION_ADES MONGOOSEV_EXCEPTION_BASE+1 319 #define MONGOOSEV_EXCEPTION_IBE MONGOOSEV_EXCEPTION_BASE+2 320 #define MONGOOSEV_EXCEPTION_DBE MONGOOSEV_EXCEPTION_BASE+3 321 #define MONGOOSEV_EXCEPTION_SYSCALL MONGOOSEV_EXCEPTION_BASE+4 322 #define MONGOOSEV_EXCEPTION_BREAK MONGOOSEV_EXCEPTION_BASE+5 323 #define MONGOOSEV_EXCEPTION_RI MONGOOSEV_EXCEPTION_BASE+6 324 #define MONGOOSEV_EXCEPTION_CPU MONGOOSEV_EXCEPTION_BASE+7 325 #define MONGOOSEV_EXCEPTION_OVERFLOW MONGOOSEV_EXCEPTION_BASE+8 326 327 328 329 330 331 332 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ 333 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ 334 #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ 335 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ 336 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ 337 #define SR_BEV 0x00400000 /* use boot exception vectors */ 338 #define SR_TS 0x00200000 /* TLB shutdown */ 339 #define SR_PE 0x00100000 /* cache parity error */ 340 #define SR_CM 0x00080000 /* cache miss */ 341 #define SR_PZ 0x00040000 /* cache parity zero */ 342 #define SR_SWC 0x00020000 /* swap cache */ 343 #define SR_ISC 0x00010000 /* Isolate data cache */ 344 #define SR_IMASK 0x0000ff00 /* Interrupt mask */ 345 #define SR_IMASK8 0x00000000 /* mask level 8 */ 346 #define SR_IMASK7 0x00008000 /* mask level 7 */ 347 #define SR_IMASK6 0x0000c000 /* mask level 6 */ 348 #define SR_IMASK5 0x0000e000 /* mask level 5 */ 349 #define SR_IMASK4 0x0000f000 /* mask level 4 */ 350 #define SR_IMASK3 0x0000f800 /* mask level 3 */ 351 #define SR_IMASK2 0x0000fc00 /* mask level 2 */ 352 #define SR_IMASK1 0x0000fe00 /* mask level 1 */ 353 #define SR_IMASK0 0x0000ff00 /* mask level 0 */ 354 355 #define SR_IBIT8 0x00008000 /* bit level 8 */ 356 #define SR_IBIT7 0x00004000 /* bit level 7 */ 357 #define SR_IBIT6 0x00002000 /* bit level 6 */ 358 #define SR_IBIT5 0x00001000 /* bit level 5 */ 359 #define SR_IBIT4 0x00000800 /* bit level 4 */ 360 #define SR_IBIT3 0x00000400 /* bit level 3 */ 361 #define SR_IBIT2 0x00000200 /* bit level 2 */ 362 #define SR_IBIT1 0x00000100 /* bit level 1 */ 363 364 #define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ 365 #define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ 366 #define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ 367 #define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ 368 #define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ 369 #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ 370 #define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC) 371 372 #define SR_IMASKSHIFT 8 305 373 306 374 #endif -
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
ra355e3ea r2e7ed911 16 16 #include <libcpu/mongoose-v.h> 17 17 18 #define mips_get_cause( _cause ) \ 19 do { \ 20 asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \ 21 } while (0) 22 23 #define CALL_ISR(_vector) \ 18 #include "iregdef.h" 19 #include "idtcpu.h" 20 21 22 #define CALL_ISR(_vector,_frame) \ 24 23 do { \ 25 24 if ( _ISR_Vector_table[_vector] ) \ 26 (_ISR_Vector_table[_vector])(_vector ); \25 (_ISR_Vector_table[_vector])(_vector,_frame); \ 27 26 else \ 28 mips_default_ exception(_vector); \27 mips_default_isr(_vector); \ 29 28 } while (0) 30 29 31 30 #include <bspIo.h> /* for printk */ 32 31 33 void mips_default_exception( int vector ) 34 { 35 printk( "Unhandled exception %d\n", vector ); 36 rtems_fatal_error_occurred(1); 37 } 38 39 void mips_vector_isr_handlers( void ) 32 33 34 35 36 37 void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) 38 { 39 unsigned32 sr, srmaskoff; 40 unsigned32 cause, cshifted; 41 unsigned32 bit; 42 unsigned32 pf_icr; 43 44 /* mips_get_sr( sr ); */ 45 sr = frame->regs[ R_SR ]; 46 47 mips_get_cause( cause ); 48 49 /* mask off everything other than the interrupt bits */ 50 cause &= SR_IMASK; 51 52 /* mask off the pending interrupts in the status register */ 53 srmaskoff = sr & ~cause; 54 mips_set_sr( srmaskoff ); 55 56 /* allow nesting for all non-pending interrupts */ 57 asm volatile( "rfe" ); 58 59 cshifted = (cause & (sr & SR_IMASK)) >> CAUSE_IPSHIFT; 60 61 if ( cshifted & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */ 62 CALL_ISR( MONGOOSEV_IRQ_TIMER1, frame ); 63 64 if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ 65 CALL_ISR( MONGOOSEV_IRQ_TIMER2, frame ); 66 67 if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */ 68 CALL_ISR( MONGOOSEV_IRQ_INT2, frame ); 69 70 if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */ 71 CALL_ISR( MONGOOSEV_IRQ_INT3, frame ); 72 73 if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */ 74 CALL_ISR( MONGOOSEV_IRQ_INT4, frame ); 75 76 if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */ 77 { 78 pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); 79 80 /* if !pf_icr */ 81 for ( bit=0 ; bit <= 31 ; bit++, pf_icr >>= 1 ) 82 { 83 if ( pf_icr & 1 ) 84 { 85 CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit, frame ); 86 } 87 } 88 } 89 90 91 /* all the pending interrupts were serviced, now re-enable them */ 92 mips_get_sr( sr ); 93 94 /* we allow the 2 software interrupts to nest freely, under the 95 * assumption that the program knows what its doing... 96 */ 97 98 if( cshifted & 0x3 ) 99 { 100 sr |= (SR_IBIT1 | SR_IBIT1); 101 cause &= ~(SR_IBIT1 | SR_IBIT1); 102 103 mips_set_cause(cause); 104 mips_set_sr(sr); 105 106 if ( cshifted & 0x01 ) /* SW[0] */ 107 { 108 CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame ); 109 } 110 if ( cshifted & 0x02 ) /* SW[1] */ 111 { 112 CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame ); 113 } 114 } 115 116 sr |= cause; 117 mips_set_sr( sr ); 118 } 119 120 121 122 123 124 125 126 void mips_default_isr( int vector ) 40 127 { 41 128 unsigned int sr; 42 129 unsigned int cause; 43 int bit;44 unsigned int pf_icr;45 130 46 131 mips_get_sr( sr ); 47 132 mips_get_cause( cause ); 48 133 49 cause &= (sr & SR_IMASK); 50 cause >>= CAUSE_IPSHIFT; 51 52 if ( cause & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */ 53 CALL_ISR( MONGOOSEV_IRQ_TIMER1 ); 54 55 if ( cause & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ 56 CALL_ISR( MONGOOSEV_IRQ_TIMER2 ); 57 58 if ( cause & 0x10 ) /* IP[2] ==> INT2 */ 59 CALL_ISR( MONGOOSEV_IRQ_INT2 ); 60 61 if ( cause & 0x20 ) /* IP[3] ==> INT4 */ 62 CALL_ISR( MONGOOSEV_IRQ_INT4 ); 63 64 if ( cause & 0x40 ) { /* IP[4] ==> INT5 */ 65 pf_icr = 66 MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); 67 /* XXX if !pf_icr */ 68 for ( bit=0 ; bit <= 31 ; bit++, pf_icr >>= 1 ) { 69 if ( pf_icr & 1 ) 70 CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit ); 71 } 134 printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr ); 135 rtems_fatal_error_occurred(1); 136 } 137 138 139 140 141 142 143 144 145 /* userspace routine to assert either software interrupt */ 146 147 int assertSoftwareInterrupt( unsigned32 n ) 148 { 149 if( n >= 0 && n<2 ) 150 { 151 unsigned32 c; 152 153 mips_get_cause(c); 154 c = ((n+1) << 8); 155 mips_set_cause(c); 156 157 return n; 158 } 159 else return -1; 160 } 161 162 163 164 165 166 167 168 169 170 171 172 /* exception vectoring, from vectorexceptions.c */ 173 174 /*#include <rtems.h> 175 #include <stdlib.h> 176 #include "iregdef.h" 177 #include <bsp.h> 178 #include <bspIo.h>*/ 179 180 181 182 183 char *cause_strings[32] = 184 { 185 /* 0 */ "Int", 186 /* 1 */ "TLB Mods", 187 /* 2 */ "TLB Load", 188 /* 3 */ "TLB Store", 189 /* 4 */ "Address Load", 190 /* 5 */ "Address Store", 191 /* 6 */ "Instruction Bus Error", 192 /* 7 */ "Data Bus Error", 193 /* 9 */ "Syscall", 194 /* 10 */ "Breakpoint", 195 /* 11 */ "Reserved Instruction", 196 /* 12 */ "Coprocessor Unuseable", 197 /* 13 */ "Overflow", 198 /* 14 */ "Trap", 199 /* 15 */ "Instruction Virtual Coherency Error", 200 /* 16 */ "FP Exception", 201 /* 17 */ "Reserved 17", 202 /* 18 */ "Reserved 17", 203 /* 19 */ "Reserved 17", 204 /* 20 */ "Reserved 20", 205 /* 21 */ "Reserved 21", 206 /* 22 */ "Reserved 22", 207 /* 23 */ "Watch", 208 /* 24 */ "Reserved 24", 209 /* 25 */ "Reserved 25", 210 /* 26 */ "Reserved 26", 211 /* 27 */ "Reserved 27", 212 /* 28 */ "Reserved 28", 213 /* 29 */ "Reserved 29", 214 /* 30 */ "Reserved 30", 215 /* 31 */ "Data Virtual Coherency Error" 216 }; 217 218 219 220 struct regdef 221 { 222 int offset; 223 char *name; 224 }; 225 226 227 /* 228 * this struct holds the set of registers we're going to dump on an 229 * exception, the symbols are defined by iregdef.h, and they are set 230 * by cpu_asm.S into the CPU_Interrupt_frame passed here by 231 * ISR_Handler. Note not all registers are stored, only those used 232 * by the cpu_asm.S code. Refer to cpu_asm.S 233 */ 234 235 236 struct regdef dumpregs[]= { { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, { R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" }, \ 237 { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, { R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" }, \ 238 { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, \ 239 { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, { R_EPC,"R_EPC"}, { -1, NULL } }; 240 241 242 243 void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame ) 244 { 245 unsigned int sr; 246 unsigned int cause; 247 int i, j; 248 249 mips_get_sr( sr ); 250 mips_get_cause( cause ); 251 252 printk( "Unhandled exception %d\n", exc ); 253 printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause, cause_strings[(cause >> 2) &0x1f] ); 254 255 for(i=0; dumpregs[i].offset > -1; i++) 256 { 257 printk(" %s", dumpregs[i].name); 258 for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" "); 259 printk(" %08X\n", frame->regs[dumpregs[i].offset] ); 72 260 } 73 74 if ( cause & 0x02 ) /* SW[0] */ 75 CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1 ); 76 77 if ( cause & 0x01 ) /* IP[1] */ 78 CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2 ); 79 } 261 262 rtems_fatal_error_occurred(1); 263 } 264 265 266 267 268 269 270 271 #define CALL_EXC(_vector,_frame) \ 272 do { \ 273 if( _ISR_Vector_table[_vector] ) \ 274 (_ISR_Vector_table[_vector])(_vector,_frame); \ 275 else \ 276 mips_default_exception_code_handler( _vector, _frame ); \ 277 } while(0) 278 279 280 281 282 283 void mips_vector_exceptions( CPU_Interrupt_frame *frame ) 284 { 285 unsigned32 cause; 286 unsigned32 exc; 287 288 mips_get_cause( cause ); 289 exc = (cause >> 2) & 0x1f; 290 291 if( exc == 4 ) 292 CALL_EXC( MONGOOSEV_EXCEPTION_ADEL, frame ); 293 294 else if( exc == 5 ) 295 CALL_EXC( MONGOOSEV_EXCEPTION_ADES, frame ); 296 297 else if( exc == 6 ) 298 CALL_EXC( MONGOOSEV_EXCEPTION_IBE, frame ); 299 300 else if( exc == 7 ) 301 CALL_EXC( MONGOOSEV_EXCEPTION_DBE, frame ); 302 303 else if( exc == 8 ) 304 CALL_EXC( MONGOOSEV_EXCEPTION_SYSCALL, frame ); 305 306 else if( exc == 9 ) 307 CALL_EXC( MONGOOSEV_EXCEPTION_BREAK, frame ); 308 309 else if( exc == 10 ) 310 CALL_EXC( MONGOOSEV_EXCEPTION_RI, frame ); 311 312 else if( exc == 11 ) 313 CALL_EXC( MONGOOSEV_EXCEPTION_CPU, frame ); 314 315 else if( exc == 12 ) 316 CALL_EXC( MONGOOSEV_EXCEPTION_OVERFLOW, frame ); 317 318 else 319 mips_default_exception_code_handler( exc, frame ); 320 } 321 322 323 // eof 324 -
c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
ra355e3ea r2e7ed911 7 7 PGM = $(ARCH)/interrupts.rel 8 8 9 C_FILES = installisrentries.c maxvectors.c vectorexceptions.c9 C_FILES = installisrentries.c maxvectors.c 10 10 11 11 S_FILES = isr_entries.S -
c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
ra355e3ea r2e7ed911 32 32 * these are reserved but for simplicity in processing, we 33 33 * reserve slots for those bits anyway. 34 * 35 * gdm, 5/14, added 15 more slots so exceptions can be vectored as well. 34 36 */ 35 37 36 38 #if defined(MONGOOSEV) 37 #define MAX_VECTORS 3739 #define MAX_VECTORS (38+10) 38 40 #endif 39 41 … … 43 45 44 46 unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS; 47
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