Changeset 2e2a41e in rtems


Ignore:
Timestamp:
Jul 28, 2017, 9:11:54 AM (2 years ago)
Author:
Christian Mauderer <Christian.Mauderer@…>
Branches:
master
Children:
3d374d9
Parents:
a5d49eb
git-author:
Christian Mauderer <Christian.Mauderer@…> (07/28/17 09:11:54)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/17/17 13:14:18)
Message:

bsp/atsam: Add timing for RAM mt48lc16m16a2p-6a.

Location:
c/src/lib/libbsp/arm/atsam
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/atsam/configure.ac

    ra5d49eb r2e2a41e  
    5757  is42s16100e-7bli) AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000 ;;
    5858  is42s16320f-7bl) AC_DEFINE([ATSAM_SDRAM_IS42S16320F_7BL],[1],[SDRAM variant]) EXTSDRAM=0x04000000 ;;
     59  mt48lc16m16a2p-6a) AC_DEFINE([ATSAM_SDRAM_MT48LC16M16A2P_6A],[1],[SDRAM variant]) EXTSDRAM=0x02000000 ;;
    5960  *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;;
    6061esac],
  • c/src/lib/libbsp/arm/atsam/startup/sdram-config.c

    ra5d49eb r2e2a41e  
    7575};
    7676
     77#elif defined ATSAM_SDRAM_MT48LC16M16A2P_6A
     78
     79/*
     80 * Refresh: 7.81 us
     81 * TWR: 12 ns
     82 * TRC_TRFC: 60 ns
     83 * TRP: 15 ns
     84 * TRCD: 18 ns
     85 * TRAS: 42 ns
     86 * TXSR: 67 ns
     87 * TMRD: 2 clock cycles
     88 */
     89
     90#if ATSAM_MCK == 60000000
     91const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
     92  .sdramc_tr = 0x1D4,
     93  .sdramc_cr =
     94      SDRAMC_CR_NC_COL9
     95    | SDRAMC_CR_NR_ROW13
     96    | SDRAMC_CR_NB_BANK4
     97    | SDRAMC_CR_CAS_LATENCY3
     98    | SDRAMC_CR_DBW
     99    | SDRAMC_CR_TWR(3)
     100    | SDRAMC_CR_TRC_TRFC(8)
     101    | SDRAMC_CR_TRP(3)
     102    | SDRAMC_CR_TRCD(3)
     103    | SDRAMC_CR_TRAS(5)
     104    | SDRAMC_CR_TXSR(9),
     105  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
     106  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
     107      SDRAMC_CFR1_TMRD(2)
     108};
     109
     110#elif ATSAM_MCK == 123000000
     111const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
     112  .sdramc_tr = 960,
     113  .sdramc_cr =
     114      SDRAMC_CR_NC_COL9
     115    | SDRAMC_CR_NR_ROW13
     116    | SDRAMC_CR_NB_BANK4
     117    | SDRAMC_CR_CAS_LATENCY3
     118    | SDRAMC_CR_DBW
     119    | SDRAMC_CR_TWR(2)
     120    | SDRAMC_CR_TRC_TRFC(8)
     121    | SDRAMC_CR_TRP(2)
     122    | SDRAMC_CR_TRCD(3)
     123    | SDRAMC_CR_TRAS(6)
     124    | SDRAMC_CR_TXSR(9),
     125  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
     126  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
     127      SDRAMC_CFR1_TMRD(2)
     128};
     129
     130#else /* ATSAM_MCK unknown */
     131#error Please check SDRAM settings for this frequency.
     132#endif
     133
    77134#else
    78135  #error SDRAM not supported.
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