Changeset 2e19bfd in rtems

Timestamp:

12/23/14 11:27:53 (8 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

4.11, 5, master

Children:

b1268e6

Parents:

0d0095f1

git-author:

Sebastian Huber <sebastian.huber@…> (12/23/14 11:27:53)

git-committer:

Sebastian Huber <sebastian.huber@…> (01/09/15 13:05:46)

Message:

powerpc: Use PPC_HAS_FPU

Provide floating point context support only if PPC_HAS_FPU == 1.

Files:

• c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S (modified) (6 diffs)
• cpukit/score/cpu/powerpc/rtems/score/cpu.h (modified) (2 diffs)

c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S

@@ -57 +57 @@
 #define PPC_CONTEXT_CACHE_LINE_4 (5 * PPC_DEFAULT_CACHE_LINE_SIZE)
 
+        BEGIN_CODE
+
+#if PPC_HAS_FPU == 1
+
 /*
- * Offsets for various Contexts
+ * Offsets for Context_Control_fp
  */
 
@@ -105 +109 @@
         .set    FP_FPSCR, (FP_31 + FP_SIZE)
 
-        BEGIN_CODE
 /*
  *  _CPU_Context_save_fp_context
@@ -122 +125 @@
         PUBLIC_PROC (_CPU_Context_save_fp)
 PROC (_CPU_Context_save_fp):
-#if (PPC_HAS_FPU == 1)
 /* A FP context switch may occur in an ISR or exception handler when the FPU is not
  * available. Therefore, we must explicitely enable it here!
@@ -172 +174 @@
         isync
 1:
-#endif
         blr
 
@@ -191 +192 @@
         PUBLIC_PROC (_CPU_Context_restore_fp)
 PROC (_CPU_Context_restore_fp):
-#if (PPC_HAS_FPU == 1)
         lwz     r3, 0(r3)
 /* A FP context switch may occur in an ISR or exception handler when the FPU is not
@@ -241 +241 @@
         isync
 1:
-#endif
         blr
+#endif /* PPC_HAS_FPU == 1 */
 
         ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)

cpukit/score/cpu/powerpc/rtems/score/cpu.h

@@ -393 +393 @@
 #ifndef ASM
 typedef struct {
+#if (PPC_HAS_FPU == 1)
     /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
      * procedure calls.  However, this would mean that the interrupt
@@ -406 +407 @@
     uint32_t    fpscr;
 #endif
+#endif /* (PPC_HAS_FPU == 1) */
 } Context_Control_fp;