Changeset 2df6f90 in rtems-docs


Ignore:
Timestamp:
Jul 3, 2020, 5:33:38 AM (6 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
d2d60c5
Parents:
0c13e94
git-author:
Sebastian Huber <sebastian.huber@…> (07/03/20 05:33:38)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/05/20 16:06:10)
Message:

Reflect removal of the epiphany target

Update #3941.

Files:
1 deleted
2 edited

Legend:

Unmodified
Added
Removed
  • cpu-supplement/epiphany.rst

    r0c13e94 r2df6f90  
    11.. SPDX-License-Identifier: CC-BY-SA-4.0
    22
    3 .. Copyright (C) 2015 Hesham Almatary
    4 .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
     3.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
    54
    65Epiphany Specific Information
    76*****************************
    87
    9 This chapter discusses the`Epiphany Architecture
    10 http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of
    11 RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can
    12 run RTEMS separately or they can work together to run a SMP RTEMS application.
    13 
    14 **Architecture Documents**
    15 
    16 For information on the Epiphany architecture refer to the *Epiphany
    17 Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf.
    18 
    19 Calling Conventions
    20 ===================
    21 
    22 Please refer to the *Epiphany SDK*
    23 http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary
    24 Interface
    25 
    26 Floating Point Unit
    27 -------------------
    28 
    29 A floating point unit is currently not supported.
    30 
    31 Memory Model
    32 ============
    33 
    34 A flat 32-bit memory model is supported, no caches. Each core has its own 32
    35 KiB strictly ordered local memory along with an access to a shared 32 MiB
    36 external DRAM.
    37 
    38 Interrupt Processing
    39 ====================
    40 
    41 Every Epiphany core has 10 exception types:
    42 
    43 - Reset
    44 
    45 - Software Exception
    46 
    47 - Data Page Fault
    48 
    49 - Timer 0
    50 
    51 - Timer 1
    52 
    53 - Message Interrupt
    54 
    55 - DMA0 Interrupt
    56 
    57 - DMA1 Interrupt
    58 
    59 - WANT Interrupt
    60 
    61 - User Interrupt
    62 
    63 Interrupt Levels
    64 ----------------
    65 
    66 There are only two levels: interrupts enabled and interrupts disabled.
    67 
    68 Interrupt Stack
    69 ---------------
    70 
    71 The Epiphany RTEMS port uses a dedicated software interrupt stack.  The stack
    72 for interrupts is allocated during interrupt driver initialization.  When an
    73 interrupt is entered, the _ISR_Handler routine is responsible for switching
    74 from the interrupted task stack to RTEMS software interrupt stack.
    75 
    76 Default Fatal Error Processing
    77 ==============================
    78 
    79 The default fatal error handler for this architecture performs the following
    80 actions:
    81 
    82 - disables operating system supported interrupts (IRQ),
    83 
    84 - places the error code in ``r0``, and
    85 
    86 - executes an infinite loop to simulate a halt processor instruction.
    87 
    88 Symmetric Multiprocessing
    89 =========================
    90 
    91 SMP is not supported.
     8Due to an unmaintained toolchain (internal errors in GCC, no FSF GDB
     9integration) the Epiphany architecture was obsoleted in
     10RTEMS 5.1 and removed in RTEMS 6.1.
  • user/bsps/index.rst

    r0c13e94 r2df6f90  
    2828    bsps-arm
    2929    bsps-bfin
    30     bsps-epiphany
    3130    bsps-i386
    3231    bsps-lm32
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