Changeset 2d5c486 in rtems


Ignore:
Timestamp:
Nov 27, 2014, 6:39:36 AM (5 years ago)
Author:
Nick Withers <nick.withers@…>
Branches:
4.11, master
Children:
86364e8
Parents:
2573e69
git-author:
Nick Withers <nick.withers@…> (11/27/14 06:39:36)
git-committer:
Gedare Bloom <gedare@…> (12/24/14 03:40:32)
Message:

Use fixed-width C99 types for PowerPC in_be16() and co.

Also use the const qualifier on the address pointer's target in in_*()

Closes #2128

Location:
c/src/lib
Files:
24 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/beatnik/marvell/discovery.c

    r2573e69 r2d5c486  
    5858#include <bsp/gtreg.h>
    5959#include <bsp/pci.h>
     60#include <stdint.h>
    6061
    6162#ifndef PCI_VENDOR_ID_MARVELL
     
    7980pci_early_config_read(int offset, int width)
    8081{
    81         out_be32((unsigned int*) pci.pci_config_addr,
     82        out_be32((uint32_t*) pci.pci_config_addr,
    8283                 0x80|(0<<8)|(PCI_DEVFN(0,0)<<16)|((offset&~3)<<24));
    8384        switch (width) {
    8485                default:
    8586                case 1:
    86                         return in_8((unsigned char*)pci.pci_config_data + (offset&3));
     87                        return in_8((uint8_t*)pci.pci_config_data + (offset&3));
    8788                case 2:
    88                         return in_le16((unsigned short*)pci.pci_config_data + (offset&3));
     89                        return in_le16((uint16_t*)pci.pci_config_data + (offset&3));
    8990                case 4:
    90                         return in_le32((unsigned long *)pci.pci_config_data + (offset&3));
     91                        return in_le32((uint32_t *)pci.pci_config_data + (offset&3));
    9192        }
    9293}
  • c/src/lib/libbsp/powerpc/beatnik/marvell/gt_timer.c

    r2573e69 r2d5c486  
    7070static inline uint32_t gt_rd(uint32_t off)
    7171{
    72   return in_le32( (volatile unsigned *)(BSP_MV64x60_BASE+off) );
     72  return in_le32( (volatile uint32_t *)(BSP_MV64x60_BASE+off) );
    7373}
    7474
    7575static inline void gt_wr(uint32_t off, uint32_t val)
    7676{
    77   out_le32( (volatile unsigned *)(BSP_MV64x60_BASE+off), val);
     77  out_le32( (volatile uint32_t *)(BSP_MV64x60_BASE+off), val);
    7878}
    7979
  • c/src/lib/libbsp/powerpc/beatnik/marvell/gti2c.c

    r2573e69 r2d5c486  
    114114gt_read(uint32_t base, uint32_t off)
    115115{
    116         return in_le32((volatile unsigned*)(base+off));
     116        return in_le32((volatile uint32_t*)(base+off));
    117117}
    118118
     
    120120gt_write(uint32_t base, uint32_t off, uint32_t val)
    121121{
    122         out_le32((volatile unsigned*)(base+off), val);
     122        out_le32((volatile uint32_t*)(base+off), val);
    123123}
    124124
     
    207207{unsigned from,to;
    208208        asm volatile("mftb %0":"=r"(from));
    209         while ( in_le32((volatile unsigned*)0xf100000c) & 0x20 )
     209        while ( in_le32((volatile uint32_t*)0xf100000c) & 0x20 )
    210210                ;
    211211        asm volatile("mftb %0":"=r"(to));
  • c/src/lib/libbsp/powerpc/beatnik/network/if_gfe/if_gfe.c

    r2573e69 r2d5c486  
    17611761        d = NEXT_TXD(l);
    17621762
    1763         out_be32((unsigned int*)&d->ed_cmdsts,0);
     1763        out_be32((uint32_t*)&d->ed_cmdsts,0);
    17641764
    17651765        GE_TXDPRESYNC(sc, txq, d - txq->txq_descs);
  • c/src/lib/libbsp/powerpc/beatnik/network/porting/rtemscompat.h

    r2573e69 r2d5c486  
    151151
    152152#ifdef __PPC__
    153 #define _out_byte(a,v) out_8((volatile unsigned char*)(a),(v))
    154 #define _inp_byte(a)   in_8((volatile unsigned char*)(a))
     153#define _out_byte(a,v) out_8((volatile uint8_t*)(a),(v))
     154#define _inp_byte(a)   in_8((volatile uint8_t*)(a))
    155155#ifdef NET_CHIP_LE
    156 #define _out_word(a,v) out_le16((volatile unsigned short*)(a),(v))
    157 #define _out_long(a,v) out_le32((volatile unsigned *)(a),(v))
    158 #define _inp_word(a)   in_le16((volatile unsigned short*)(a))
    159 #define _inp_long(a)   in_le32((volatile unsigned *)(a))
     156#define _out_word(a,v) out_le16((volatile uint16_t*)(a),(v))
     157#define _out_long(a,v) out_le32((volatile uint32_t *)(a),(v))
     158#define _inp_word(a)   in_le16((volatile uint16_t*)(a))
     159#define _inp_long(a)   in_le32((volatile uint32_t *)(a))
    160160#elif defined(NET_CHIP_BE)
    161 #define _out_word(a,v) out_be16((volatile unsigned short*)(a),(v))
    162 #define _out_long(a,v) out_be32((volatile unsigned *)(a),(v))
    163 #define _inp_word(a)   in_be16((volatile unsigned short*)(a))
    164 #define _inp_long(a)   in_be32((volatile unsigned *)(a))
     161#define _out_word(a,v) out_be16((volatile uint16_t*)(a),(v))
     162#define _out_long(a,v) out_be32((volatile uint32_t *)(a),(v))
     163#define _inp_word(a)   in_be16((volatile uint16_t*)(a))
     164#define _inp_long(a)   in_be32((volatile uint32_t *)(a))
    165165#else
    166166#error rtemscompat_defs.h must define either NET_CHIP_LE or NET_CHIP_BE
  • c/src/lib/libbsp/powerpc/beatnik/pci/gt_pci_init.c

    r2573e69 r2d5c486  
    8484                              unsigned char offset, uint8_t *val) {
    8585HOSE_PREAMBLE;
    86         out_be32((volatile unsigned *) pci.pci_config_addr,
     86        out_be32((volatile uint32_t *) pci.pci_config_addr,
    8787                 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
    8888        *val = in_8(pci.pci_config_data + (offset&3));
     
    9797        *val = 0xffff;
    9898        if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
    99         out_be32((unsigned int*) pci.pci_config_addr,
    100                  0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
    101         *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)));
     99        out_be32((uint32_t*) pci.pci_config_addr,
     100                 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
     101        *val = in_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)));
    102102        return PCIBIOS_SUCCESSFUL;
    103103}
     
    110110        *val = 0xffffffff;
    111111        if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
    112         out_be32((unsigned int*) pci.pci_config_addr,
     112        out_be32((uint32_t*) pci.pci_config_addr,
    113113                 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
    114         *val = in_le32((volatile unsigned *)pci.pci_config_data);
     114        *val = in_le32((volatile uint32_t *)pci.pci_config_data);
    115115        return PCIBIOS_SUCCESSFUL;
    116116}
     
    121121                               unsigned char offset, uint8_t val) {
    122122HOSE_PREAMBLE;
    123         out_be32((unsigned int*) pci.pci_config_addr,
     123        out_be32((uint32_t*) pci.pci_config_addr,
    124124                 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
    125125        out_8(pci.pci_config_data + (offset&3), val);
     
    133133HOSE_PREAMBLE;
    134134        if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
    135         out_be32((unsigned int*) pci.pci_config_addr,
    136                  0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
    137         out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val);
     135        out_be32((uint32_t*) pci.pci_config_addr,
     136                 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
     137        out_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)), val);
    138138        return PCIBIOS_SUCCESSFUL;
    139139}
     
    145145HOSE_PREAMBLE;
    146146        if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
    147         out_be32((unsigned int*) pci.pci_config_addr,
     147        out_be32((uint32_t*) pci.pci_config_addr,
    148148                 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
    149         out_le32((volatile unsigned *)pci.pci_config_data, val);
     149        out_le32((volatile uint32_t *)pci.pci_config_data, val);
    150150        return PCIBIOS_SUCCESSFUL;
    151151}
  • c/src/lib/libbsp/powerpc/beatnik/pci/motload_fixup.c

    r2573e69 r2d5c486  
    9797         */
    9898
    99         b0 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Low_Decode) );
    100         b1 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Low_Decode) );
     99        b0 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Low_Decode) );
     100        b1 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Low_Decode) );
    101101
    102         r0 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap) );
    103         r1 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap) );
     102        r0 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap) );
     103        r1 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap) );
    104104
    105105        switch ( BSP_getDiscoveryVersion(0) ) {
     
    108108                         * Disable by setting special bits in the 'BAR disable reg'.
    109109                         */
    110                         dis = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL) );
     110                        dis = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL) );
    111111                        /* disable PCI0 I/O and PCI1 I/O */
    112                         out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis | (1<<9) | (1<<14) );
     112                        out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis | (1<<9) | (1<<14) );
    113113                        /* remap busses on hose 0; if the remap register was already set, assume
    114114                         * that someone else [such as the bootloader] already performed the fixup
     
    116116                        if ( (b0 & 0xffff) && 0 == (r0 & 0xffff) ) {
    117117                                rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xffff)<<16 );
    118                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xffff) );
     118                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xffff) );
    119119                        }
    120120
     
    122122                        if ( (b1 & 0xffff) && 0 == (r1 & 0xffff) ) {
    123123                                rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xffff)<<16 );
    124                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xffff) );
     124                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xffff) );
    125125                        }
    126126
    127127                        /* re-enable */
    128                         out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis );
     128                        out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis );
    129129                break;
    130130
     
    134134                        if ( (b0 & 0xfff) && 0 == (r0 & 0xfff) ) { /* base are only 12 bits */
    135135                                /* switch window off by setting the limit < base */
    136                                 lim = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode) );
    137                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), 0 );
     136                                lim = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode) );
     137                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), 0 );
    138138                                /* remap busses on hose 0 */
    139139                                rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xfff)<<20 );
     
    142142                                 * value into the 'remap' register automatically (??)
    143143                                 */
    144                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xfff) );
     144                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xfff) );
    145145
    146146                                /* re-enable */
    147                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), lim );
     147                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), lim );
    148148                        }
    149149
    150150                        if ( (b1 & 0xfff) && 0 == (r1 & 0xfff) ) { /* base are only 12 bits */
    151151                                /* switch window off by setting the limit < base */
    152                                 lim = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode) );
    153                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), 0 );
     152                                lim = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode) );
     153                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), 0 );
    154154
    155155                                /* remap busses on hose 1 */
    156156                                rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xfff)<<20 );
    157157
    158                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xfff) );
     158                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xfff) );
    159159
    160160                                /* re-enable */
    161                                 out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), lim );
     161                                out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), lim );
    162162                        }
    163163                break;
  • c/src/lib/libbsp/powerpc/beatnik/startup/bspreset.c

    r2573e69 r2d5c486  
    55#include <libcpu/io.h>
    66#include <libcpu/stackTrace.h>
     7#include <stdint.h>
    78
    89void bsp_reset()
     
    1415  printk("RTEMS terminated; Rebooting ...\n");
    1516  /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov>  */
    16   out_8((volatile unsigned char*) (BSP_MV64x60_DEV1_BASE +2), 0x80);
     17  out_8((volatile uint8_t*) (BSP_MV64x60_DEV1_BASE +2), 0x80);
    1718}
  • c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c

    r2573e69 r2d5c486  
    5959
    6060static void write8( int addr, int data ){
    61   out_8((void *)addr, (unsigned char)data);
     61  out_8((uint8_t *)addr, (uint8_t)data);
    6262}
    6363
    6464static void write16( int addr, int data ) {
    65   out_be16((void *)addr, (short)data );
     65  out_be16((uint16_t *)addr, (uint16_t)data );
    6666}
    6767
    6868static void write32( int addr, int data ) {
    69   out_be32((unsigned int *)addr, data );
     69  out_be32((uint32_t *)addr, (uint32_t)data );
    7070}
    7171
  • c/src/lib/libbsp/powerpc/mvme3100/include/bsp.h

    r2573e69 r2d5c486  
    111111#define PCI_CONFIG_ADDR      (BSP_8540_CCSR_BASE+0x8000)
    112112#define PCI_CONFIG_DATA      (BSP_8540_CCSR_BASE+0x8004)
    113 #define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((unsigned int*)(addr), (val))
     113#define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val))
    114114
    115115#define BSP_CONSOLE_PORT        BSP_UART_COM1
  • c/src/lib/libbsp/powerpc/mvme3100/startup/bspstart.c

    r2573e69 r2d5c486  
    143143_ccsr_rd32(uint32_t off)
    144144{
    145   return in_be32( (volatile unsigned *)(BSP_8540_CCSR_BASE + off) );
     145  return in_be32( (volatile uint32_t *)(BSP_8540_CCSR_BASE + off) );
    146146}
    147147
     
    149149_ccsr_wr32(uint32_t off, uint32_t val)
    150150{
    151   out_be32( (volatile unsigned *)(BSP_8540_CCSR_BASE + off), val );
     151  out_be32( (volatile uint32_t *)(BSP_8540_CCSR_BASE + off), val );
    152152}
    153153
  • c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c

    r2573e69 r2d5c486  
    2828 */
    2929
     30#include <inttypes.h>
    3031#include <stdio.h>
    3132#include <rtems/system.h>
     
    315316  BSP_irqMask_cache[regNum] |= (1 << bitNum);
    316317
    317   out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
    318   while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
     318  out_le32((volatile uint32_t *)BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
     319  while (in_le32((volatile uint32_t *)BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
    319320
    320321  rtems_interrupt_enable(level);
     
    343344  BSP_irqMask_cache[regNum] &=  ~(1 << bitNum);
    344345
    345   out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
    346   while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
     346  out_le32((volatile uint32_t *)BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
     347  while (in_le32((volatile uint32_t *)BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
    347348
    348349  rtems_interrupt_enable(level);
     
    373374   * MOTload default is set as level sensitive(1). Set it agin to make sure.
    374375   */
    375   out_le32((volatile unsigned int *)GT_CommUnitArb_Ctrl,
    376            (in_le32((volatile unsigned int *)GT_CommUnitArb_Ctrl)| (1<<10)));
     376  out_le32((volatile uint32_t *)GT_CommUnitArb_Ctrl,
     377           (in_le32((volatile uint32_t *)GT_CommUnitArb_Ctrl)| (1<<10)));
    377378
    378379#if 0
    379   printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
    380          in_le32(BSP_irqMask_reg[0]),
    381          in_le32(BSP_irqCause_reg[0]));
    382   printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
    383          in_le32(BSP_irqMask_reg[1]),
    384          in_le32(BSP_irqCause_reg[1]));
    385   printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
    386          in_le32(BSP_irqMask_reg[2]),
    387          in_le32(BSP_irqCause_reg[2]));
     380  printk("BSP_irqMask_reg[0] = 0x%" PRIx32 ", BSP_irqCause_reg[0] 0x%" PRIx32 "\n",
     381         in_le32((volatile uint32_t *)BSP_irqMask_reg[0]),
     382         in_le32((volatile uint32_t *)BSP_irqCause_reg[0]));
     383  printk("BSP_irqMask_reg[1] = 0x%" PRIx32 ", BSP_irqCause_reg[1] 0x%" PRIx32 "\n",
     384         in_le32((volatile uint32_t *)BSP_irqMask_reg[1]),
     385         in_le32((volatile uint32_t *)BSP_irqCause_reg[1]));
     386  printk("BSP_irqMask_reg[2] = 0x%" PRIx32 ", BSP_irqCause_reg[2] 0x%" PRIx32 "\n",
     387         in_le32((volatile uint32_t *)BSP_irqMask_reg[2]),
     388         in_le32((volatile uint32_t *)BSP_irqCause_reg[2]));
    388389#endif
    389390
    390391  /* Initialize the interrupt related  registers */
    391392  for (i=0; i<3; i++) {
    392     out_le32(BSP_irqCause_reg[i], 0);
    393     out_le32(BSP_irqMask_reg[i], 0);
    394   }
    395   in_le32(BSP_irqMask_reg[2]);
     393    out_le32((volatile uint32_t *)BSP_irqCause_reg[i], 0);
     394    out_le32((volatile uint32_t *)BSP_irqMask_reg[i], 0);
     395  }
     396  in_le32((volatile uint32_t *)BSP_irqMask_reg[2]);
    396397  compute_pic_masks_from_prio();
    397398
    398399#if 0
    399   printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
    400          in_le32(BSP_irqMask_reg[0]),
    401          in_le32(BSP_irqCause_reg[0]));
    402   printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
    403          in_le32(BSP_irqMask_reg[1]),
    404          in_le32(BSP_irqCause_reg[1]));
    405   printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
    406          in_le32(BSP_irqMask_reg[2]),
    407          in_le32(BSP_irqCause_reg[2]));
     400  printk("BSP_irqMask_reg[0] = 0x%" PRIx32 ", BSP_irqCause_reg[0] 0x%" PRIx32 "\n",
     401         in_le32((volatile uint32_t *)BSP_irqMask_reg[0]),
     402         in_le32((volatile uint32_t *)BSP_irqCause_reg[0]));
     403  printk("BSP_irqMask_reg[1] = 0x%" PRIx32 ", BSP_irqCause_reg[1] 0x%" PRIx32 "\n",
     404         in_le32((volatile uint32_t *)BSP_irqMask_reg[1]),
     405         in_le32((volatile uint32_t *)BSP_irqCause_reg[1]));
     406  printk("BSP_irqMask_reg[2] = 0x%" PRIx32 ", BSP_irqCause_reg[2] 0x%" PRIx32 "\n",
     407         in_le32((volatile uint32_t *)BSP_irqMask_reg[2]),
     408         in_le32((volatile uint32_t *)BSP_irqCause_reg[2]));
    408409#endif
    409410
     
    443444
    444445  for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
    445   for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]);
     446  for (j=0; j<3; j++) irqCause[j] = in_le32((volatile uint32_t *)BSP_irqCause_reg[j]) & in_le32((volatile uint32_t *)BSP_irqMask_reg[j]);
    446447
    447448  while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP))
     
    451452        BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
    452453
    453       out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]);
    454       out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]);
    455       out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]);
    456       in_le32(BSP_irqMask_reg[2]);
     454      out_le32((volatile uint32_t *)BSP_irqMask_reg[0], BSP_irqMask_cache[0]);
     455      out_le32((volatile uint32_t *)BSP_irqMask_reg[1], BSP_irqMask_cache[1]);
     456      out_le32((volatile uint32_t *)BSP_irqMask_reg[2], BSP_irqMask_cache[2]);
     457      in_le32((volatile uint32_t *)BSP_irqMask_reg[2]);
    457458
    458459      bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl);
     
    460461      for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
    461462
    462       out_le32(BSP_irqMask_reg[0], oldMask[0]);
    463       out_le32(BSP_irqMask_reg[1], oldMask[1]);
    464       out_le32(BSP_irqMask_reg[2], oldMask[2]);
    465       in_le32(BSP_irqMask_reg[2]);
     463      out_le32((volatile uint32_t *)BSP_irqMask_reg[0], oldMask[0]);
     464      out_le32((volatile uint32_t *)BSP_irqMask_reg[1], oldMask[1]);
     465      out_le32((volatile uint32_t *)BSP_irqMask_reg[2], oldMask[2]);
     466      in_le32((volatile uint32_t *)BSP_irqMask_reg[2]);
    466467    }
    467468  }
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c

    r2573e69 r2d5c486  
    4040#include <rtems/bspIo.h>      /* printk */
    4141
     42#include <inttypes.h>
    4243#include <stdio.h>            /* printf for statistics */
    4344#include <string.h>
     
    218219#define WM_F_PCIX               0x40    /* bus is PCI-X */
    219220
    220 #define CSR_READ(sc,reg) in_le32((volatile unsigned *)(sc->sc_membase+reg))
    221 #define CSR_WRITE(sc,reg,val) out_le32((volatile unsigned *)(sc->sc_membase+reg), val)
     221#define CSR_READ(sc,reg) in_le32((volatile uint32_t *)(sc->sc_membase+reg))
     222#define CSR_WRITE(sc,reg,val) out_le32((volatile uint32_t *)(sc->sc_membase+reg), val)
    222223
    223224#define WM_CDTXADDR(sc) ( (uint32_t) &sc->sc_txdescs[0] )
     
    541542  printf("    Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts);
    542543  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
    543   printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
     544  printf("     Receive Packets:%-8u\n", (unsigned)CSR_READ(sc,WMREG_GPRC));
    544545  printf("     Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts);
    545   printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
     546  printf("     Receive  errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_RXERRC));
    546547  printf("   Rx sequence error:%-8lu\n", sc->stats.rxSeqErr);
    547548  printf("      Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered);
    548   printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
     549  printf("    Rx Length Errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_RLEC));
    549550  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
    550   printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
     551  printf("   Transmitt Packets:%-8u\n", (unsigned)CSR_READ(sc,WMREG_GPTC));
    551552  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
    552553  printf("         Active Txqs:%-8lu\n", sc->txq_nactive);
    553   printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
    554   printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
     554  printf("          collisions:%-8u\n", (unsigned)CSR_READ(sc,WMREG_COLC));
     555  printf("          Crc Errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_CRCERRS));
    555556  printf("  Link Status Change:%-8lu\n", sc->stats.linkStatusChng);
    556557}
     
    11471148void BSP_rdTIDV(void)
    11481149{
    1149   printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV)));
     1150  printf("Reg TIDV: 0x%" PRIx32 "\n", in_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_TIDV)));
    11501151}
    11511152void BSP_rdRDTR(void)
    11521153{
    1153   printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR)));
     1154  printf("Reg RDTR: 0x%" PRIx32 "\n", in_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_RDTR)));
    11541155}
    11551156
    11561157void BSP_setTIDV(int val)
    11571158{
    1158   out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val);
     1159  out_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_TIDV), val);
    11591160}
    11601161
    11611162void BSP_setRDTR(int val)
    11621163{
    1163   out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val);
     1164  out_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_RDTR), val);
    11641165}
    11651166/*
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c

    r2573e69 r2d5c486  
    103103#endif
    104104
    105   out_be32((volatile unsigned int *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     105  out_be32((volatile uint32_t *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
    106106  *val = in_8(BSP_pci[n].pci_config_data + (offset&3));
    107107  return PCIBIOS_SUCCESSFUL;
     
    124124    config_data,pciConfigPack(bus,dev,func,offset));
    125125#endif
    126   out_be32((volatile unsigned int *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
    127   *val = in_le16((volatile unsigned short *) (BSP_pci[n].pci_config_data + (offset&2)));
     126  out_be32((volatile uint32_t *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     127  *val = in_le16((volatile uint16_t *) (BSP_pci[n].pci_config_data + (offset&2)));
    128128  return PCIBIOS_SUCCESSFUL;
    129129}
     
    142142  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    143143
    144   out_be32((volatile unsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
    145   *val = in_le32((volatile unsigned int *)BSP_pci[n].pci_config_data);
     144  out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     145  *val = in_le32((volatile uint32_t *)BSP_pci[n].pci_config_data);
    146146  return PCIBIOS_SUCCESSFUL;
    147147}
     
    158158  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    159159
    160   out_be32((volatile unsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
    161   out_8((volatile unsigned char *) (BSP_pci[n].pci_config_data + (offset&3)), val);
     160  out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     161  out_8((volatile uint8_t *) (BSP_pci[n].pci_config_data + (offset&3)), val);
    162162  return PCIBIOS_SUCCESSFUL;
    163163}
     
    174174  if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    175175
    176   out_be32((volatile unsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
    177   out_le16((volatile unsigned short *)(BSP_pci[n].pci_config_data + (offset&3)), val);
     176  out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     177  out_le16((volatile uint16_t *)(BSP_pci[n].pci_config_data + (offset&3)), val);
    178178  return PCIBIOS_SUCCESSFUL;
    179179}
     
    190190  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    191191
    192   out_be32((volatile unsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
    193   out_le32((volatile unsigned int *)BSP_pci[n].pci_config_data, val);
     192  out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     193  out_le32((volatile uint32_t *)BSP_pci[n].pci_config_data, val);
    194194  return PCIBIOS_SUCCESSFUL;
    195195}
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c

    r2573e69 r2d5c486  
    2323#include <bsp/gtreg.h>
    2424#include <bsp/gtpcireg.h>
     25
     26#include <inttypes.h>
    2527
    2628#define PCI_DEBUG     0
     
    7274#ifdef CPU2PCI_ORDER
    7375    /* MOTLOad deafult : 0x07ff8600 */
    74     out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
     76    out_le32((volatile uint32_t *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
    7577#endif
    7678    /* asserts SERR upon various detection */
    77     out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
     79    out_le32((volatile uint32_t *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
    7880    pciAccessInit();
    7981}
     
    8486
    8587  for (PciLocal=0; PciLocal < 2; PciLocal++) {
    86     data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
     88    data = in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
    8789#if 0
    8890    printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data);
     
    9092    data |= PCI_ACCCTLBASEL_VALUE;
    9193    data &= ~0x300000;
    92     out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
     94    out_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
    9395#if 0
    94       printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));
     96      printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%" PRIx32 "\n",PciLocal,in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));
    9597#endif
    9698  }
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspreset.c

    r2573e69 r2d5c486  
    99#include <libcpu/io.h>
    1010#include <libcpu/stackTrace.h>
     11#include <stdint.h>
    1112
    1213void bsp_reset()
     
    1819  printk("RTEMS terminated; Rebooting ...\n");
    1920  /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov>  */
    20   out_8((volatile unsigned char*) (GT64x60_DEV1_BASE +2), 0x80);
     21  out_8((volatile uint8_t*) (GT64x60_DEV1_BASE +2), 0x80);
    2122}
  • c/src/lib/libbsp/powerpc/shared/bootloader/pci.c

    r2573e69 r2d5c486  
    572572   out_be32(pci->config_addr,
    573573            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
    574    *val=in_le16((volatile u_short *)(pci->config_data + (offset&3)));
     574   *val=in_le16((volatile uint16_t *)(pci->config_data + (offset&3)));
    575575   return PCIBIOS_SUCCESSFUL;
    576576}
     
    583583   out_be32(pci->config_addr,
    584584            0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
    585    *val=in_le32((volatile u_int *)pci->config_data);
     585   *val=in_le32((volatile uint32_t *)pci->config_data);
    586586   return PCIBIOS_SUCCESSFUL;
    587587}
     
    602602   out_be32(pci->config_addr,
    603603            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
    604    out_le16((volatile u_short *)(pci->config_data + (offset&3)), val);
     604   out_le16((volatile uint16_t *)(pci->config_data + (offset&3)), val);
    605605   return PCIBIOS_SUCCESSFUL;
    606606}
     
    612612   out_be32(pci->config_addr,
    613613            0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
    614    out_le32((volatile u_int *)pci->config_data, val);
     614   out_le32((volatile uint32_t *)pci->config_data, val);
    615615   return PCIBIOS_SUCCESSFUL;
    616616}
     
    645645      return PCIBIOS_DEVICE_NOT_FOUND;
    646646   }
    647    *val=in_le16((volatile u_short *)
     647   *val=in_le16((volatile uint16_t *)
    648648                (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
    649649                 + (PCI_FUNC(dev_fn)<<8) + offset));
     
    659659      return PCIBIOS_DEVICE_NOT_FOUND;
    660660   }
    661    *val=in_le32((volatile u_int *)
     661   *val=in_le32((volatile uint32_t *)
    662662                (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
    663663                 + (PCI_FUNC(dev_fn)<<8) + offset));
     
    684684      return PCIBIOS_DEVICE_NOT_FOUND;
    685685   }
    686    out_le16((volatile u_short *)
     686   out_le16((volatile uint16_t *)
    687687            (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
    688688             + (PCI_FUNC(dev_fn)<<8) + offset),
     
    698698      return PCIBIOS_DEVICE_NOT_FOUND;
    699699   }
    700    out_le32((volatile u_int *)
     700   out_le32((volatile uint32_t *)
    701701            (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
    702702             + (PCI_FUNC(dev_fn)<<8) + offset),
  • c/src/lib/libbsp/powerpc/shared/console/console.inl

    r2573e69 r2d5c486  
    77
    88#include <bsp.h>
     9#include <stdint.h>
    910
    1011#define INL_IN_DECL(name,base) \
    1112static inline unsigned char name(int off) \
    1213{ \
    13         return in_8((unsigned char*)(((unsigned long)base) + off)); \
     14        return in_8((uint8_t*)(((unsigned long)base) + off)); \
    1415}
    1516
     
    1718static inline void name(int off, unsigned int val) \
    1819{ \
    19         out_8((unsigned char*)(((unsigned long)base) + off), val); \
     20        out_8((uint8_t*)(((unsigned long)base) + off), val); \
    2021}
    2122
  • c/src/lib/libbsp/powerpc/shared/console/uart.c

    r2573e69 r2d5c486  
    66 */
    77
     8#include <stdint.h>
    89#include <stdio.h>
    910#include <bsp.h>
     
    7374uread(int uart, unsigned int reg)
    7475{
    75         return in_8((unsigned char*)(uart_data[uart].ioBase + reg));
     76        return in_8((uint8_t*)(uart_data[uart].ioBase + reg));
    7677}
    7778
     
    7980uwrite(int uart, int reg, unsigned int val)
    8081{
    81         out_8((unsigned char*)(uart_data[uart].ioBase + reg), val);
     82        out_8((uint8_t*)(uart_data[uart].ioBase + reg), val);
    8283}
    8384
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.c

    r2573e69 r2d5c486  
    9393
    9494#ifdef BSP_OPEN_PIC_BIG_ENDIAN
    95         val = in_be32(addr);
     95        val = in_be32((volatile uint32_t *)addr);
    9696#else
    97     val = in_le32(addr);
     97    val = in_le32((volatile uint32_t *)addr);
    9898#endif
    9999#ifdef REGISTER_DEBUG
     
    109109#endif
    110110#ifdef BSP_OPEN_PIC_BIG_ENDIAN
    111     out_be32(addr, val);
     111    out_be32((volatile uint32_t *)addr, val);
    112112#else
    113         out_le32(addr, val);
     113        out_le32((volatile uint32_t *)addr, val);
    114114#endif
    115115}
     
    308308                uint32_t eicr_val, ratio;
    309309                /* On the 8240 this is the EICR register */
    310                 eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);
     310                eicr_val = in_le32( (volatile uint32_t *)&OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);
    311311                if ( (1<<27) & eicr_val ) {
    312312                        /* serial interface mode enabled */
     
    319319                        if ( 0==ratio )
    320320                                ratio = 1;
    321                         out_le32(&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));
     321                        out_le32((volatile uint32_t *)&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));
    322322                        /*  Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */
    323323                        openpic_set_eoi_delay( 16 * (2*ratio) / 4 );
  • c/src/lib/libbsp/powerpc/shared/pci/pci.c

    r2573e69 r2d5c486  
    4444
    4545#ifndef  PCI_CONFIG_WR_ADDR
    46 #define  PCI_CONFIG_WR_ADDR( addr, val ) out_le32((unsigned int*)(addr), (val))
     46#define  PCI_CONFIG_WR_ADDR( addr, val ) out_le32((volatile uint32_t*)(addr), (val))
    4747#endif
    4848
     
    8484
    8585  PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset);
    86   *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)));
     86  *val = in_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)));
    8787  return PCIBIOS_SUCCESSFUL;
    8888}
     
    101101
    102102  PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset);
    103   *val = in_le32((volatile unsigned int *)pci.pci_config_data);
     103  *val = in_le32((volatile uint32_t *)pci.pci_config_data);
    104104  return PCIBIOS_SUCCESSFUL;
    105105}
     
    130130
    131131  PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset);
    132   out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val);
     132  out_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)), val);
    133133  return PCIBIOS_SUCCESSFUL;
    134134}
     
    145145    return PCIBIOS_BAD_REGISTER_NUMBER;
    146146  PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset);
    147   out_le32((volatile unsigned int *)pci.pci_config_data, val);
     147  out_le32((volatile uint32_t *)pci.pci_config_data, val);
    148148  return PCIBIOS_SUCCESSFUL;
    149149}
     
    195195     return PCIBIOS_DEVICE_NOT_FOUND;
    196196
    197   *val=in_le16((volatile unsigned short *)
     197  *val=in_le16((volatile uint16_t *)
    198198      (pci.pci_config_data + ((1<<slot)&~1)
    199199       + (function<<8) + offset));
     
    215215     return PCIBIOS_DEVICE_NOT_FOUND;
    216216
    217   *val=in_le32((volatile unsigned int *)
     217  *val=in_le32((volatile uint32_t *)
    218218      (pci.pci_config_data + ((1<<slot)&~1)
    219219       + (function<<8) + offset));
     
    251251     return PCIBIOS_DEVICE_NOT_FOUND;
    252252
    253   out_le16((volatile unsigned short *)
     253  out_le16((volatile uint16_t *)
    254254     (pci.pci_config_data + ((1<<slot)&~1)
    255255   + (function<<8) + offset),
     
    271271     return PCIBIOS_DEVICE_NOT_FOUND;
    272272
    273   out_le32((volatile unsigned int *)
     273  out_le32((volatile uint32_t *)
    274274     (pci.pci_config_data + ((1<<slot)&~1)
    275275   + (function<<8) + offset),
  • c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

    r2573e69 r2d5c486  
    125125 */
    126126static unsigned int get_eumbbar(void) {
    127   out_le32( (volatile unsigned *)0xfec00000, 0x80000078 );
    128   return in_le32( (volatile unsigned *)0xfee00000 );
     127  out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 );
     128  return in_le32( (volatile uint32_t *)0xfee00000 );
    129129}
    130130#endif
  • c/src/lib/libbsp/shared/vmeUniverse/vmeTsi148.c

    r2573e69 r2d5c486  
    327327
    328328
    329 #define TSI_RD(base, reg)                               in_be32((volatile unsigned *)((base) + (reg)/sizeof(*base)))
    330 #define TSI_RD16(base, reg)                             in_be16((volatile unsigned short *)(base) + (reg)/sizeof(short))
    331 #define TSI_LE_RD16(base, reg)                  in_le16((volatile unsigned short *)(base) + (reg)/sizeof(short))
    332 #define TSI_LE_RD32(base, reg)                  in_le32((volatile unsigned *)(base) + (reg)/sizeof(*base))
    333 #define TSI_RD8(base, reg)                              in_8((volatile unsigned char *)(base) + (reg))
    334 #define TSI_WR(base, reg, val)                  out_be32((volatile unsigned *)((base) + (reg)/sizeof(*base)), val)
     329#define TSI_RD(base, reg)                               in_be32((volatile uint32_t *)((base) + (reg)/sizeof(*base)))
     330#define TSI_RD16(base, reg)                             in_be16((volatile uint16_t *)(base) + (reg)/sizeof(uint16_t))
     331#define TSI_LE_RD16(base, reg)                  in_le16((volatile uint16_t *)(base) + (reg)/sizeof(uint16_t))
     332#define TSI_LE_RD32(base, reg)                  in_le32((volatile uint32_t *)(base) + (reg)/sizeof(*base))
     333#define TSI_RD8(base, reg)                              in_8((volatile uint8_t *)(base) + (reg))
     334#define TSI_WR(base, reg, val)                  out_be32((volatile uint32_t *)((base) + (reg)/sizeof(*base)), val)
    335335
    336336#define UNIV_SCTL_AM_MASK       (UNIV_CTL_VAS | UNIV_SCTL_PGM | UNIV_SCTL_DAT | UNIV_SCTL_USER | UNIV_SCTL_SUPER)
  • c/src/lib/libcpu/powerpc/shared/include/io.h

    r2573e69 r2d5c486  
    3131
    3232#include <bsp.h>                /* for _IO_BASE & friends */
     33#include <stdint.h>
    3334
    3435/* NOTE: The use of these macros is DISCOURAGED.
     
    3839 *       to port.
    3940 */
    40 #define inb(port)               in_8((unsigned char *)((port)+_IO_BASE))
    41 #define outb(val, port)         out_8((unsigned char *)((port)+_IO_BASE), (val))
    42 #define inw(port)               in_le16((unsigned short *)((port)+_IO_BASE))
    43 #define outw(val, port)         out_le16((unsigned short *)((port)+_IO_BASE), (val))
    44 #define inl(port)               in_le32((unsigned *)((port)+_IO_BASE))
    45 #define outl(val, port)         out_le32((unsigned *)((port)+_IO_BASE), (val))
     41#define inb(port)               in_8((uint8_t *)((port)+_IO_BASE))
     42#define outb(val, port)         out_8((uint8_t *)((port)+_IO_BASE), (val))
     43#define inw(port)               in_le16((uint16_t *)((port)+_IO_BASE))
     44#define outw(val, port)         out_le16((uint16_t *)((port)+_IO_BASE), (val))
     45#define inl(port)               in_le32((uint32_t *)((port)+_IO_BASE))
     46#define outl(val, port)         out_le32((uint32_t *)((port)+_IO_BASE), (val))
    4647
    4748/*
     
    6667 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
    6768 */
    68 static inline int in_8(volatile unsigned char *addr)
     69static inline uint8_t in_8(const volatile uint8_t *addr)
    6970{
    70         int ret;
     71        uint8_t ret;
    7172
    7273        __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
     
    7475}
    7576
    76 static inline void out_8(volatile unsigned char *addr, int val)
     77static inline void out_8(volatile uint8_t *addr, uint8_t val)
    7778{
    7879        __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
    7980}
    8081
    81 static inline int in_le16(volatile unsigned short *addr)
     82static inline uint16_t in_le16(const volatile uint16_t *addr)
    8283{
    83         int ret;
     84        uint16_t ret;
    8485
    8586        __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
     
    8889}
    8990
    90 static inline int in_be16(volatile unsigned short *addr)
     91static inline uint16_t in_be16(const volatile uint16_t *addr)
    9192{
    92         int ret;
     93        uint16_t ret;
    9394
    9495        __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
     
    9697}
    9798
    98 static inline void out_le16(volatile unsigned short *addr, int val)
     99static inline void out_le16(volatile uint16_t *addr, uint16_t val)
    99100{
    100101        __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
     
    102103}
    103104
    104 static inline void out_be16(volatile unsigned short *addr, int val)
     105static inline void out_be16(volatile uint16_t *addr, uint16_t val)
    105106{
    106107        __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
    107108}
    108109
    109 static inline unsigned in_le32(volatile unsigned *addr)
     110static inline uint32_t in_le32(const volatile uint32_t *addr)
    110111{
    111         unsigned ret;
     112        uint32_t ret;
    112113
    113114        __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
     
    116117}
    117118
    118 static inline unsigned in_be32(volatile unsigned *addr)
     119static inline uint32_t in_be32(const volatile uint32_t *addr)
    119120{
    120         unsigned ret;
     121        uint32_t ret;
    121122
    122123        __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
     
    124125}
    125126
    126 static inline void out_le32(volatile unsigned *addr, int val)
     127static inline void out_le32(volatile uint32_t *addr, uint32_t val)
    127128{
    128129        __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
     
    130131}
    131132
    132 static inline void out_be32(volatile unsigned *addr, int val)
     133static inline void out_be32(volatile uint32_t *addr, uint32_t val)
    133134{
    134135        __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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