Changeset 2d5c486 in rtems
- Timestamp:
- 11/27/14 06:39:36 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 86364e8
- Parents:
- 2573e69
- git-author:
- Nick Withers <nick.withers@…> (11/27/14 06:39:36)
- git-committer:
- Gedare Bloom <gedare@…> (12/24/14 03:40:32)
- Location:
- c/src/lib
- Files:
-
- 24 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/beatnik/marvell/discovery.c
r2573e69 r2d5c486 58 58 #include <bsp/gtreg.h> 59 59 #include <bsp/pci.h> 60 #include <stdint.h> 60 61 61 62 #ifndef PCI_VENDOR_ID_MARVELL … … 79 80 pci_early_config_read(int offset, int width) 80 81 { 81 out_be32((u nsigned int*) pci.pci_config_addr,82 out_be32((uint32_t*) pci.pci_config_addr, 82 83 0x80|(0<<8)|(PCI_DEVFN(0,0)<<16)|((offset&~3)<<24)); 83 84 switch (width) { 84 85 default: 85 86 case 1: 86 return in_8((u nsigned char*)pci.pci_config_data + (offset&3));87 return in_8((uint8_t*)pci.pci_config_data + (offset&3)); 87 88 case 2: 88 return in_le16((u nsigned short*)pci.pci_config_data + (offset&3));89 return in_le16((uint16_t*)pci.pci_config_data + (offset&3)); 89 90 case 4: 90 return in_le32((u nsigned long*)pci.pci_config_data + (offset&3));91 return in_le32((uint32_t *)pci.pci_config_data + (offset&3)); 91 92 } 92 93 } -
c/src/lib/libbsp/powerpc/beatnik/marvell/gt_timer.c
r2573e69 r2d5c486 70 70 static inline uint32_t gt_rd(uint32_t off) 71 71 { 72 return in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE+off) );72 return in_le32( (volatile uint32_t *)(BSP_MV64x60_BASE+off) ); 73 73 } 74 74 75 75 static inline void gt_wr(uint32_t off, uint32_t val) 76 76 { 77 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE+off), val);77 out_le32( (volatile uint32_t *)(BSP_MV64x60_BASE+off), val); 78 78 } 79 79 -
c/src/lib/libbsp/powerpc/beatnik/marvell/gti2c.c
r2573e69 r2d5c486 114 114 gt_read(uint32_t base, uint32_t off) 115 115 { 116 return in_le32((volatile u nsigned*)(base+off));116 return in_le32((volatile uint32_t*)(base+off)); 117 117 } 118 118 … … 120 120 gt_write(uint32_t base, uint32_t off, uint32_t val) 121 121 { 122 out_le32((volatile u nsigned*)(base+off), val);122 out_le32((volatile uint32_t*)(base+off), val); 123 123 } 124 124 … … 207 207 {unsigned from,to; 208 208 asm volatile("mftb %0":"=r"(from)); 209 while ( in_le32((volatile u nsigned*)0xf100000c) & 0x20 )209 while ( in_le32((volatile uint32_t*)0xf100000c) & 0x20 ) 210 210 ; 211 211 asm volatile("mftb %0":"=r"(to)); -
c/src/lib/libbsp/powerpc/beatnik/network/if_gfe/if_gfe.c
r2573e69 r2d5c486 1761 1761 d = NEXT_TXD(l); 1762 1762 1763 out_be32((u nsigned int*)&d->ed_cmdsts,0);1763 out_be32((uint32_t*)&d->ed_cmdsts,0); 1764 1764 1765 1765 GE_TXDPRESYNC(sc, txq, d - txq->txq_descs); -
c/src/lib/libbsp/powerpc/beatnik/network/porting/rtemscompat.h
r2573e69 r2d5c486 151 151 152 152 #ifdef __PPC__ 153 #define _out_byte(a,v) out_8((volatile u nsigned char*)(a),(v))154 #define _inp_byte(a) in_8((volatile u nsigned char*)(a))153 #define _out_byte(a,v) out_8((volatile uint8_t*)(a),(v)) 154 #define _inp_byte(a) in_8((volatile uint8_t*)(a)) 155 155 #ifdef NET_CHIP_LE 156 #define _out_word(a,v) out_le16((volatile u nsigned short*)(a),(v))157 #define _out_long(a,v) out_le32((volatile u nsigned*)(a),(v))158 #define _inp_word(a) in_le16((volatile u nsigned short*)(a))159 #define _inp_long(a) in_le32((volatile u nsigned*)(a))156 #define _out_word(a,v) out_le16((volatile uint16_t*)(a),(v)) 157 #define _out_long(a,v) out_le32((volatile uint32_t *)(a),(v)) 158 #define _inp_word(a) in_le16((volatile uint16_t*)(a)) 159 #define _inp_long(a) in_le32((volatile uint32_t *)(a)) 160 160 #elif defined(NET_CHIP_BE) 161 #define _out_word(a,v) out_be16((volatile u nsigned short*)(a),(v))162 #define _out_long(a,v) out_be32((volatile u nsigned*)(a),(v))163 #define _inp_word(a) in_be16((volatile u nsigned short*)(a))164 #define _inp_long(a) in_be32((volatile u nsigned*)(a))161 #define _out_word(a,v) out_be16((volatile uint16_t*)(a),(v)) 162 #define _out_long(a,v) out_be32((volatile uint32_t *)(a),(v)) 163 #define _inp_word(a) in_be16((volatile uint16_t*)(a)) 164 #define _inp_long(a) in_be32((volatile uint32_t *)(a)) 165 165 #else 166 166 #error rtemscompat_defs.h must define either NET_CHIP_LE or NET_CHIP_BE -
c/src/lib/libbsp/powerpc/beatnik/pci/gt_pci_init.c
r2573e69 r2d5c486 84 84 unsigned char offset, uint8_t *val) { 85 85 HOSE_PREAMBLE; 86 out_be32((volatile u nsigned *) pci.pci_config_addr,86 out_be32((volatile uint32_t *) pci.pci_config_addr, 87 87 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); 88 88 *val = in_8(pci.pci_config_data + (offset&3)); … … 97 97 *val = 0xffff; 98 98 if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; 99 out_be32((u nsigned int*) pci.pci_config_addr,100 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); 101 *val = in_le16((volatile u nsigned short *)(pci.pci_config_data + (offset&3)));99 out_be32((uint32_t*) pci.pci_config_addr, 100 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); 101 *val = in_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3))); 102 102 return PCIBIOS_SUCCESSFUL; 103 103 } … … 110 110 *val = 0xffffffff; 111 111 if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; 112 out_be32((u nsigned int*) pci.pci_config_addr,112 out_be32((uint32_t*) pci.pci_config_addr, 113 113 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); 114 *val = in_le32((volatile u nsigned*)pci.pci_config_data);114 *val = in_le32((volatile uint32_t *)pci.pci_config_data); 115 115 return PCIBIOS_SUCCESSFUL; 116 116 } … … 121 121 unsigned char offset, uint8_t val) { 122 122 HOSE_PREAMBLE; 123 out_be32((u nsigned int*) pci.pci_config_addr,123 out_be32((uint32_t*) pci.pci_config_addr, 124 124 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); 125 125 out_8(pci.pci_config_data + (offset&3), val); … … 133 133 HOSE_PREAMBLE; 134 134 if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; 135 out_be32((u nsigned int*) pci.pci_config_addr,136 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); 137 out_le16((volatile u nsigned short *)(pci.pci_config_data + (offset&3)), val);135 out_be32((uint32_t*) pci.pci_config_addr, 136 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); 137 out_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)), val); 138 138 return PCIBIOS_SUCCESSFUL; 139 139 } … … 145 145 HOSE_PREAMBLE; 146 146 if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; 147 out_be32((u nsigned int*) pci.pci_config_addr,147 out_be32((uint32_t*) pci.pci_config_addr, 148 148 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); 149 out_le32((volatile u nsigned*)pci.pci_config_data, val);149 out_le32((volatile uint32_t *)pci.pci_config_data, val); 150 150 return PCIBIOS_SUCCESSFUL; 151 151 } -
c/src/lib/libbsp/powerpc/beatnik/pci/motload_fixup.c
r2573e69 r2d5c486 97 97 */ 98 98 99 b0 = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Low_Decode) );100 b1 = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Low_Decode) );99 b0 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Low_Decode) ); 100 b1 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Low_Decode) ); 101 101 102 r0 = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap) );103 r1 = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap) );102 r0 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap) ); 103 r1 = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap) ); 104 104 105 105 switch ( BSP_getDiscoveryVersion(0) ) { … … 108 108 * Disable by setting special bits in the 'BAR disable reg'. 109 109 */ 110 dis = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL) );110 dis = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL) ); 111 111 /* disable PCI0 I/O and PCI1 I/O */ 112 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis | (1<<9) | (1<<14) );112 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis | (1<<9) | (1<<14) ); 113 113 /* remap busses on hose 0; if the remap register was already set, assume 114 114 * that someone else [such as the bootloader] already performed the fixup … … 116 116 if ( (b0 & 0xffff) && 0 == (r0 & 0xffff) ) { 117 117 rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xffff)<<16 ); 118 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xffff) );118 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xffff) ); 119 119 } 120 120 … … 122 122 if ( (b1 & 0xffff) && 0 == (r1 & 0xffff) ) { 123 123 rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xffff)<<16 ); 124 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xffff) );124 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xffff) ); 125 125 } 126 126 127 127 /* re-enable */ 128 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis );128 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis ); 129 129 break; 130 130 … … 134 134 if ( (b0 & 0xfff) && 0 == (r0 & 0xfff) ) { /* base are only 12 bits */ 135 135 /* switch window off by setting the limit < base */ 136 lim = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode) );137 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), 0 );136 lim = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode) ); 137 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), 0 ); 138 138 /* remap busses on hose 0 */ 139 139 rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xfff)<<20 ); … … 142 142 * value into the 'remap' register automatically (??) 143 143 */ 144 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xfff) );144 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xfff) ); 145 145 146 146 /* re-enable */ 147 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), lim );147 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), lim ); 148 148 } 149 149 150 150 if ( (b1 & 0xfff) && 0 == (r1 & 0xfff) ) { /* base are only 12 bits */ 151 151 /* switch window off by setting the limit < base */ 152 lim = in_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode) );153 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), 0 );152 lim = in_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode) ); 153 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), 0 ); 154 154 155 155 /* remap busses on hose 1 */ 156 156 rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xfff)<<20 ); 157 157 158 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xfff) );158 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xfff) ); 159 159 160 160 /* re-enable */ 161 out_le32( (volatile u nsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), lim );161 out_le32( (volatile uint32_t*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), lim ); 162 162 } 163 163 break; -
c/src/lib/libbsp/powerpc/beatnik/startup/bspreset.c
r2573e69 r2d5c486 5 5 #include <libcpu/io.h> 6 6 #include <libcpu/stackTrace.h> 7 #include <stdint.h> 7 8 8 9 void bsp_reset() … … 14 15 printk("RTEMS terminated; Rebooting ...\n"); 15 16 /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov> */ 16 out_8((volatile u nsigned char*) (BSP_MV64x60_DEV1_BASE +2), 0x80);17 out_8((volatile uint8_t*) (BSP_MV64x60_DEV1_BASE +2), 0x80); 17 18 } -
c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c
r2573e69 r2d5c486 59 59 60 60 static void write8( int addr, int data ){ 61 out_8(( void *)addr, (unsigned char)data);61 out_8((uint8_t *)addr, (uint8_t)data); 62 62 } 63 63 64 64 static void write16( int addr, int data ) { 65 out_be16(( void *)addr, (short)data );65 out_be16((uint16_t *)addr, (uint16_t)data ); 66 66 } 67 67 68 68 static void write32( int addr, int data ) { 69 out_be32((u nsigned int *)addr,data );69 out_be32((uint32_t *)addr, (uint32_t)data ); 70 70 } 71 71 -
c/src/lib/libbsp/powerpc/mvme3100/include/bsp.h
r2573e69 r2d5c486 111 111 #define PCI_CONFIG_ADDR (BSP_8540_CCSR_BASE+0x8000) 112 112 #define PCI_CONFIG_DATA (BSP_8540_CCSR_BASE+0x8004) 113 #define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((u nsigned int*)(addr), (val))113 #define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val)) 114 114 115 115 #define BSP_CONSOLE_PORT BSP_UART_COM1 -
c/src/lib/libbsp/powerpc/mvme3100/startup/bspstart.c
r2573e69 r2d5c486 143 143 _ccsr_rd32(uint32_t off) 144 144 { 145 return in_be32( (volatile u nsigned*)(BSP_8540_CCSR_BASE + off) );145 return in_be32( (volatile uint32_t *)(BSP_8540_CCSR_BASE + off) ); 146 146 } 147 147 … … 149 149 _ccsr_wr32(uint32_t off, uint32_t val) 150 150 { 151 out_be32( (volatile u nsigned*)(BSP_8540_CCSR_BASE + off), val );151 out_be32( (volatile uint32_t *)(BSP_8540_CCSR_BASE + off), val ); 152 152 } 153 153 -
c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c
r2573e69 r2d5c486 28 28 */ 29 29 30 #include <inttypes.h> 30 31 #include <stdio.h> 31 32 #include <rtems/system.h> … … 315 316 BSP_irqMask_cache[regNum] |= (1 << bitNum); 316 317 317 out_le32( BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);318 while (in_le32( BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);318 out_le32((volatile uint32_t *)BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); 319 while (in_le32((volatile uint32_t *)BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); 319 320 320 321 rtems_interrupt_enable(level); … … 343 344 BSP_irqMask_cache[regNum] &= ~(1 << bitNum); 344 345 345 out_le32( BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);346 while (in_le32( BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);346 out_le32((volatile uint32_t *)BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); 347 while (in_le32((volatile uint32_t *)BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); 347 348 348 349 rtems_interrupt_enable(level); … … 373 374 * MOTload default is set as level sensitive(1). Set it agin to make sure. 374 375 */ 375 out_le32((volatile u nsigned int *)GT_CommUnitArb_Ctrl,376 (in_le32((volatile u nsigned int *)GT_CommUnitArb_Ctrl)| (1<<10)));376 out_le32((volatile uint32_t *)GT_CommUnitArb_Ctrl, 377 (in_le32((volatile uint32_t *)GT_CommUnitArb_Ctrl)| (1<<10))); 377 378 378 379 #if 0 379 printk("BSP_irqMask_reg[0] = 0x% x, BSP_irqCause_reg[0] 0x%x\n",380 in_le32( BSP_irqMask_reg[0]),381 in_le32( BSP_irqCause_reg[0]));382 printk("BSP_irqMask_reg[1] = 0x% x, BSP_irqCause_reg[1] 0x%x\n",383 in_le32( BSP_irqMask_reg[1]),384 in_le32( BSP_irqCause_reg[1]));385 printk("BSP_irqMask_reg[2] = 0x% x, BSP_irqCause_reg[2] 0x%x\n",386 in_le32( BSP_irqMask_reg[2]),387 in_le32( BSP_irqCause_reg[2]));380 printk("BSP_irqMask_reg[0] = 0x%" PRIx32 ", BSP_irqCause_reg[0] 0x%" PRIx32 "\n", 381 in_le32((volatile uint32_t *)BSP_irqMask_reg[0]), 382 in_le32((volatile uint32_t *)BSP_irqCause_reg[0])); 383 printk("BSP_irqMask_reg[1] = 0x%" PRIx32 ", BSP_irqCause_reg[1] 0x%" PRIx32 "\n", 384 in_le32((volatile uint32_t *)BSP_irqMask_reg[1]), 385 in_le32((volatile uint32_t *)BSP_irqCause_reg[1])); 386 printk("BSP_irqMask_reg[2] = 0x%" PRIx32 ", BSP_irqCause_reg[2] 0x%" PRIx32 "\n", 387 in_le32((volatile uint32_t *)BSP_irqMask_reg[2]), 388 in_le32((volatile uint32_t *)BSP_irqCause_reg[2])); 388 389 #endif 389 390 390 391 /* Initialize the interrupt related registers */ 391 392 for (i=0; i<3; i++) { 392 out_le32( BSP_irqCause_reg[i], 0);393 out_le32( BSP_irqMask_reg[i], 0);394 } 395 in_le32( BSP_irqMask_reg[2]);393 out_le32((volatile uint32_t *)BSP_irqCause_reg[i], 0); 394 out_le32((volatile uint32_t *)BSP_irqMask_reg[i], 0); 395 } 396 in_le32((volatile uint32_t *)BSP_irqMask_reg[2]); 396 397 compute_pic_masks_from_prio(); 397 398 398 399 #if 0 399 printk("BSP_irqMask_reg[0] = 0x% x, BSP_irqCause_reg[0] 0x%x\n",400 in_le32( BSP_irqMask_reg[0]),401 in_le32( BSP_irqCause_reg[0]));402 printk("BSP_irqMask_reg[1] = 0x% x, BSP_irqCause_reg[1] 0x%x\n",403 in_le32( BSP_irqMask_reg[1]),404 in_le32( BSP_irqCause_reg[1]));405 printk("BSP_irqMask_reg[2] = 0x% x, BSP_irqCause_reg[2] 0x%x\n",406 in_le32( BSP_irqMask_reg[2]),407 in_le32( BSP_irqCause_reg[2]));400 printk("BSP_irqMask_reg[0] = 0x%" PRIx32 ", BSP_irqCause_reg[0] 0x%" PRIx32 "\n", 401 in_le32((volatile uint32_t *)BSP_irqMask_reg[0]), 402 in_le32((volatile uint32_t *)BSP_irqCause_reg[0])); 403 printk("BSP_irqMask_reg[1] = 0x%" PRIx32 ", BSP_irqCause_reg[1] 0x%" PRIx32 "\n", 404 in_le32((volatile uint32_t *)BSP_irqMask_reg[1]), 405 in_le32((volatile uint32_t *)BSP_irqCause_reg[1])); 406 printk("BSP_irqMask_reg[2] = 0x%" PRIx32 ", BSP_irqCause_reg[2] 0x%" PRIx32 "\n", 407 in_le32((volatile uint32_t *)BSP_irqMask_reg[2]), 408 in_le32((volatile uint32_t *)BSP_irqCause_reg[2])); 408 409 #endif 409 410 … … 443 444 444 445 for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j]; 445 for (j=0; j<3; j++) irqCause[j] = in_le32( BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]);446 for (j=0; j<3; j++) irqCause[j] = in_le32((volatile uint32_t *)BSP_irqCause_reg[j]) & in_le32((volatile uint32_t *)BSP_irqMask_reg[j]); 446 447 447 448 while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP)) … … 451 452 BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]); 452 453 453 out_le32( BSP_irqMask_reg[0], BSP_irqMask_cache[0]);454 out_le32( BSP_irqMask_reg[1], BSP_irqMask_cache[1]);455 out_le32( BSP_irqMask_reg[2], BSP_irqMask_cache[2]);456 in_le32( BSP_irqMask_reg[2]);454 out_le32((volatile uint32_t *)BSP_irqMask_reg[0], BSP_irqMask_cache[0]); 455 out_le32((volatile uint32_t *)BSP_irqMask_reg[1], BSP_irqMask_cache[1]); 456 out_le32((volatile uint32_t *)BSP_irqMask_reg[2], BSP_irqMask_cache[2]); 457 in_le32((volatile uint32_t *)BSP_irqMask_reg[2]); 457 458 458 459 bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl); … … 460 461 for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j]; 461 462 462 out_le32( BSP_irqMask_reg[0], oldMask[0]);463 out_le32( BSP_irqMask_reg[1], oldMask[1]);464 out_le32( BSP_irqMask_reg[2], oldMask[2]);465 in_le32( BSP_irqMask_reg[2]);463 out_le32((volatile uint32_t *)BSP_irqMask_reg[0], oldMask[0]); 464 out_le32((volatile uint32_t *)BSP_irqMask_reg[1], oldMask[1]); 465 out_le32((volatile uint32_t *)BSP_irqMask_reg[2], oldMask[2]); 466 in_le32((volatile uint32_t *)BSP_irqMask_reg[2]); 466 467 } 467 468 } -
c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c
r2573e69 r2d5c486 40 40 #include <rtems/bspIo.h> /* printk */ 41 41 42 #include <inttypes.h> 42 43 #include <stdio.h> /* printf for statistics */ 43 44 #include <string.h> … … 218 219 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 219 220 220 #define CSR_READ(sc,reg) in_le32((volatile u nsigned*)(sc->sc_membase+reg))221 #define CSR_WRITE(sc,reg,val) out_le32((volatile u nsigned*)(sc->sc_membase+reg), val)221 #define CSR_READ(sc,reg) in_le32((volatile uint32_t *)(sc->sc_membase+reg)) 222 #define CSR_WRITE(sc,reg,val) out_le32((volatile uint32_t *)(sc->sc_membase+reg), val) 222 223 223 224 #define WM_CDTXADDR(sc) ( (uint32_t) &sc->sc_txdescs[0] ) … … 541 542 printf(" Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts); 542 543 printf(" Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts); 543 printf(" Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));544 printf(" Receive Packets:%-8u\n", (unsigned)CSR_READ(sc,WMREG_GPRC)); 544 545 printf(" Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts); 545 printf(" Receive errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));546 printf(" Receive errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_RXERRC)); 546 547 printf(" Rx sequence error:%-8lu\n", sc->stats.rxSeqErr); 547 548 printf(" Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered); 548 printf(" Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));549 printf(" Rx Length Errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_RLEC)); 549 550 printf(" Tx Interrupts:%-8lu\n", sc->stats.txInterrupts); 550 printf(" Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));551 printf(" Transmitt Packets:%-8u\n", (unsigned)CSR_READ(sc,WMREG_GPTC)); 551 552 printf(" Transmitt errors:%-8lu\n", ifp->if_oerrors); 552 553 printf(" Active Txqs:%-8lu\n", sc->txq_nactive); 553 printf(" collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));554 printf(" Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));554 printf(" collisions:%-8u\n", (unsigned)CSR_READ(sc,WMREG_COLC)); 555 printf(" Crc Errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_CRCERRS)); 555 556 printf(" Link Status Change:%-8lu\n", sc->stats.linkStatusChng); 556 557 } … … 1147 1148 void BSP_rdTIDV(void) 1148 1149 { 1149 printf("Reg TIDV: 0x% x\n", in_le32((volatile unsigned*) (BSP_1GHz_membase+WMREG_TIDV)));1150 printf("Reg TIDV: 0x%" PRIx32 "\n", in_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_TIDV))); 1150 1151 } 1151 1152 void BSP_rdRDTR(void) 1152 1153 { 1153 printf("Reg RDTR: 0x% x\n", in_le32((volatile unsigned*) (BSP_1GHz_membase+WMREG_RDTR)));1154 printf("Reg RDTR: 0x%" PRIx32 "\n", in_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_RDTR))); 1154 1155 } 1155 1156 1156 1157 void BSP_setTIDV(int val) 1157 1158 { 1158 out_le32((volatile u nsigned*) (BSP_1GHz_membase+WMREG_TIDV), val);1159 out_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_TIDV), val); 1159 1160 } 1160 1161 1161 1162 void BSP_setRDTR(int val) 1162 1163 { 1163 out_le32((volatile u nsigned*) (BSP_1GHz_membase+WMREG_RDTR), val);1164 out_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_RDTR), val); 1164 1165 } 1165 1166 /* -
c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c
r2573e69 r2d5c486 103 103 #endif 104 104 105 out_be32((volatile u nsigned int *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));105 out_be32((volatile uint32_t *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 106 106 *val = in_8(BSP_pci[n].pci_config_data + (offset&3)); 107 107 return PCIBIOS_SUCCESSFUL; … … 124 124 config_data,pciConfigPack(bus,dev,func,offset)); 125 125 #endif 126 out_be32((volatile u nsigned int *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));127 *val = in_le16((volatile u nsigned short *) (BSP_pci[n].pci_config_data + (offset&2)));126 out_be32((volatile uint32_t *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 127 *val = in_le16((volatile uint16_t *) (BSP_pci[n].pci_config_data + (offset&2))); 128 128 return PCIBIOS_SUCCESSFUL; 129 129 } … … 142 142 if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; 143 143 144 out_be32((volatile u nsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));145 *val = in_le32((volatile u nsigned int *)BSP_pci[n].pci_config_data);144 out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 145 *val = in_le32((volatile uint32_t *)BSP_pci[n].pci_config_data); 146 146 return PCIBIOS_SUCCESSFUL; 147 147 } … … 158 158 if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; 159 159 160 out_be32((volatile u nsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));161 out_8((volatile u nsigned char*) (BSP_pci[n].pci_config_data + (offset&3)), val);160 out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 161 out_8((volatile uint8_t *) (BSP_pci[n].pci_config_data + (offset&3)), val); 162 162 return PCIBIOS_SUCCESSFUL; 163 163 } … … 174 174 if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; 175 175 176 out_be32((volatile u nsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));177 out_le16((volatile u nsigned short *)(BSP_pci[n].pci_config_data + (offset&3)), val);176 out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 177 out_le16((volatile uint16_t *)(BSP_pci[n].pci_config_data + (offset&3)), val); 178 178 return PCIBIOS_SUCCESSFUL; 179 179 } … … 190 190 if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; 191 191 192 out_be32((volatile u nsigned int *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));193 out_le32((volatile u nsigned int *)BSP_pci[n].pci_config_data, val);192 out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 193 out_le32((volatile uint32_t *)BSP_pci[n].pci_config_data, val); 194 194 return PCIBIOS_SUCCESSFUL; 195 195 } -
c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c
r2573e69 r2d5c486 23 23 #include <bsp/gtreg.h> 24 24 #include <bsp/gtpcireg.h> 25 26 #include <inttypes.h> 25 27 26 28 #define PCI_DEBUG 0 … … 72 74 #ifdef CPU2PCI_ORDER 73 75 /* MOTLOad deafult : 0x07ff8600 */ 74 out_le32((volatile u nsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);76 out_le32((volatile uint32_t *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600); 75 77 #endif 76 78 /* asserts SERR upon various detection */ 77 out_le32((volatile u nsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff);79 out_le32((volatile uint32_t *)(GT64x60_REG_BASE+0xc28), 0x3fffff); 78 80 pciAccessInit(); 79 81 } … … 84 86 85 87 for (PciLocal=0; PciLocal < 2; PciLocal++) { 86 data = in_le32((volatile u nsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));88 data = in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); 87 89 #if 0 88 90 printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data); … … 90 92 data |= PCI_ACCCTLBASEL_VALUE; 91 93 data &= ~0x300000; 92 out_le32((volatile u nsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);94 out_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data); 93 95 #if 0 94 printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x% x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));96 printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%" PRIx32 "\n",PciLocal,in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)))); 95 97 #endif 96 98 } -
c/src/lib/libbsp/powerpc/mvme5500/startup/bspreset.c
r2573e69 r2d5c486 9 9 #include <libcpu/io.h> 10 10 #include <libcpu/stackTrace.h> 11 #include <stdint.h> 11 12 12 13 void bsp_reset() … … 18 19 printk("RTEMS terminated; Rebooting ...\n"); 19 20 /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov> */ 20 out_8((volatile u nsigned char*) (GT64x60_DEV1_BASE +2), 0x80);21 out_8((volatile uint8_t*) (GT64x60_DEV1_BASE +2), 0x80); 21 22 } -
c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
r2573e69 r2d5c486 572 572 out_be32(pci->config_addr, 573 573 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); 574 *val=in_le16((volatile u _short *)(pci->config_data + (offset&3)));574 *val=in_le16((volatile uint16_t *)(pci->config_data + (offset&3))); 575 575 return PCIBIOS_SUCCESSFUL; 576 576 } … … 583 583 out_be32(pci->config_addr, 584 584 0x80|(bus<<8)|(dev_fn<<16)|(offset<<24)); 585 *val=in_le32((volatile u _int *)pci->config_data);585 *val=in_le32((volatile uint32_t *)pci->config_data); 586 586 return PCIBIOS_SUCCESSFUL; 587 587 } … … 602 602 out_be32(pci->config_addr, 603 603 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); 604 out_le16((volatile u _short *)(pci->config_data + (offset&3)), val);604 out_le16((volatile uint16_t *)(pci->config_data + (offset&3)), val); 605 605 return PCIBIOS_SUCCESSFUL; 606 606 } … … 612 612 out_be32(pci->config_addr, 613 613 0x80|(bus<<8)|(dev_fn<<16)|(offset<<24)); 614 out_le32((volatile u _int *)pci->config_data, val);614 out_le32((volatile uint32_t *)pci->config_data, val); 615 615 return PCIBIOS_SUCCESSFUL; 616 616 } … … 645 645 return PCIBIOS_DEVICE_NOT_FOUND; 646 646 } 647 *val=in_le16((volatile u _short *)647 *val=in_le16((volatile uint16_t *) 648 648 (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) 649 649 + (PCI_FUNC(dev_fn)<<8) + offset)); … … 659 659 return PCIBIOS_DEVICE_NOT_FOUND; 660 660 } 661 *val=in_le32((volatile u _int *)661 *val=in_le32((volatile uint32_t *) 662 662 (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) 663 663 + (PCI_FUNC(dev_fn)<<8) + offset)); … … 684 684 return PCIBIOS_DEVICE_NOT_FOUND; 685 685 } 686 out_le16((volatile u _short *)686 out_le16((volatile uint16_t *) 687 687 (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) 688 688 + (PCI_FUNC(dev_fn)<<8) + offset), … … 698 698 return PCIBIOS_DEVICE_NOT_FOUND; 699 699 } 700 out_le32((volatile u _int *)700 out_le32((volatile uint32_t *) 701 701 (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) 702 702 + (PCI_FUNC(dev_fn)<<8) + offset), -
c/src/lib/libbsp/powerpc/shared/console/console.inl
r2573e69 r2d5c486 7 7 8 8 #include <bsp.h> 9 #include <stdint.h> 9 10 10 11 #define INL_IN_DECL(name,base) \ 11 12 static inline unsigned char name(int off) \ 12 13 { \ 13 return in_8((u nsigned char*)(((unsigned long)base) + off)); \14 return in_8((uint8_t*)(((unsigned long)base) + off)); \ 14 15 } 15 16 … … 17 18 static inline void name(int off, unsigned int val) \ 18 19 { \ 19 out_8((u nsigned char*)(((unsigned long)base) + off), val); \20 out_8((uint8_t*)(((unsigned long)base) + off), val); \ 20 21 } 21 22 -
c/src/lib/libbsp/powerpc/shared/console/uart.c
r2573e69 r2d5c486 6 6 */ 7 7 8 #include <stdint.h> 8 9 #include <stdio.h> 9 10 #include <bsp.h> … … 73 74 uread(int uart, unsigned int reg) 74 75 { 75 return in_8((u nsigned char*)(uart_data[uart].ioBase + reg));76 return in_8((uint8_t*)(uart_data[uart].ioBase + reg)); 76 77 } 77 78 … … 79 80 uwrite(int uart, int reg, unsigned int val) 80 81 { 81 out_8((u nsigned char*)(uart_data[uart].ioBase + reg), val);82 out_8((uint8_t*)(uart_data[uart].ioBase + reg), val); 82 83 } 83 84 -
c/src/lib/libbsp/powerpc/shared/openpic/openpic.c
r2573e69 r2d5c486 93 93 94 94 #ifdef BSP_OPEN_PIC_BIG_ENDIAN 95 val = in_be32( addr);95 val = in_be32((volatile uint32_t *)addr); 96 96 #else 97 val = in_le32( addr);97 val = in_le32((volatile uint32_t *)addr); 98 98 #endif 99 99 #ifdef REGISTER_DEBUG … … 109 109 #endif 110 110 #ifdef BSP_OPEN_PIC_BIG_ENDIAN 111 out_be32( addr, val);111 out_be32((volatile uint32_t *)addr, val); 112 112 #else 113 out_le32( addr, val);113 out_le32((volatile uint32_t *)addr, val); 114 114 #endif 115 115 } … … 308 308 uint32_t eicr_val, ratio; 309 309 /* On the 8240 this is the EICR register */ 310 eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);310 eicr_val = in_le32( (volatile uint32_t *)&OpenPIC->Global.Global_Configuration1 ) & ~(7<<28); 311 311 if ( (1<<27) & eicr_val ) { 312 312 /* serial interface mode enabled */ … … 319 319 if ( 0==ratio ) 320 320 ratio = 1; 321 out_le32( &OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));321 out_le32((volatile uint32_t *)&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28)); 322 322 /* Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */ 323 323 openpic_set_eoi_delay( 16 * (2*ratio) / 4 ); -
c/src/lib/libbsp/powerpc/shared/pci/pci.c
r2573e69 r2d5c486 44 44 45 45 #ifndef PCI_CONFIG_WR_ADDR 46 #define PCI_CONFIG_WR_ADDR( addr, val ) out_le32(( unsigned int*)(addr), (val))46 #define PCI_CONFIG_WR_ADDR( addr, val ) out_le32((volatile uint32_t*)(addr), (val)) 47 47 #endif 48 48 … … 84 84 85 85 PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset); 86 *val = in_le16((volatile u nsigned short *)(pci.pci_config_data + (offset&3)));86 *val = in_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3))); 87 87 return PCIBIOS_SUCCESSFUL; 88 88 } … … 101 101 102 102 PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset); 103 *val = in_le32((volatile u nsigned int *)pci.pci_config_data);103 *val = in_le32((volatile uint32_t *)pci.pci_config_data); 104 104 return PCIBIOS_SUCCESSFUL; 105 105 } … … 130 130 131 131 PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset); 132 out_le16((volatile u nsigned short *)(pci.pci_config_data + (offset&3)), val);132 out_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)), val); 133 133 return PCIBIOS_SUCCESSFUL; 134 134 } … … 145 145 return PCIBIOS_BAD_REGISTER_NUMBER; 146 146 PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset); 147 out_le32((volatile u nsigned int *)pci.pci_config_data, val);147 out_le32((volatile uint32_t *)pci.pci_config_data, val); 148 148 return PCIBIOS_SUCCESSFUL; 149 149 } … … 195 195 return PCIBIOS_DEVICE_NOT_FOUND; 196 196 197 *val=in_le16((volatile u nsigned short *)197 *val=in_le16((volatile uint16_t *) 198 198 (pci.pci_config_data + ((1<<slot)&~1) 199 199 + (function<<8) + offset)); … … 215 215 return PCIBIOS_DEVICE_NOT_FOUND; 216 216 217 *val=in_le32((volatile u nsigned int *)217 *val=in_le32((volatile uint32_t *) 218 218 (pci.pci_config_data + ((1<<slot)&~1) 219 219 + (function<<8) + offset)); … … 251 251 return PCIBIOS_DEVICE_NOT_FOUND; 252 252 253 out_le16((volatile u nsigned short *)253 out_le16((volatile uint16_t *) 254 254 (pci.pci_config_data + ((1<<slot)&~1) 255 255 + (function<<8) + offset), … … 271 271 return PCIBIOS_DEVICE_NOT_FOUND; 272 272 273 out_le32((volatile u nsigned int *)273 out_le32((volatile uint32_t *) 274 274 (pci.pci_config_data + ((1<<slot)&~1) 275 275 + (function<<8) + offset), -
c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
r2573e69 r2d5c486 125 125 */ 126 126 static unsigned int get_eumbbar(void) { 127 out_le32( (volatile u nsigned*)0xfec00000, 0x80000078 );128 return in_le32( (volatile u nsigned*)0xfee00000 );127 out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 ); 128 return in_le32( (volatile uint32_t *)0xfee00000 ); 129 129 } 130 130 #endif -
c/src/lib/libbsp/shared/vmeUniverse/vmeTsi148.c
r2573e69 r2d5c486 327 327 328 328 329 #define TSI_RD(base, reg) in_be32((volatile u nsigned*)((base) + (reg)/sizeof(*base)))330 #define TSI_RD16(base, reg) in_be16((volatile u nsigned short *)(base) + (reg)/sizeof(short))331 #define TSI_LE_RD16(base, reg) in_le16((volatile u nsigned short *)(base) + (reg)/sizeof(short))332 #define TSI_LE_RD32(base, reg) in_le32((volatile u nsigned*)(base) + (reg)/sizeof(*base))333 #define TSI_RD8(base, reg) in_8((volatile u nsigned char*)(base) + (reg))334 #define TSI_WR(base, reg, val) out_be32((volatile u nsigned*)((base) + (reg)/sizeof(*base)), val)329 #define TSI_RD(base, reg) in_be32((volatile uint32_t *)((base) + (reg)/sizeof(*base))) 330 #define TSI_RD16(base, reg) in_be16((volatile uint16_t *)(base) + (reg)/sizeof(uint16_t)) 331 #define TSI_LE_RD16(base, reg) in_le16((volatile uint16_t *)(base) + (reg)/sizeof(uint16_t)) 332 #define TSI_LE_RD32(base, reg) in_le32((volatile uint32_t *)(base) + (reg)/sizeof(*base)) 333 #define TSI_RD8(base, reg) in_8((volatile uint8_t *)(base) + (reg)) 334 #define TSI_WR(base, reg, val) out_be32((volatile uint32_t *)((base) + (reg)/sizeof(*base)), val) 335 335 336 336 #define UNIV_SCTL_AM_MASK (UNIV_CTL_VAS | UNIV_SCTL_PGM | UNIV_SCTL_DAT | UNIV_SCTL_USER | UNIV_SCTL_SUPER) -
c/src/lib/libcpu/powerpc/shared/include/io.h
r2573e69 r2d5c486 31 31 32 32 #include <bsp.h> /* for _IO_BASE & friends */ 33 #include <stdint.h> 33 34 34 35 /* NOTE: The use of these macros is DISCOURAGED. … … 38 39 * to port. 39 40 */ 40 #define inb(port) in_8((u nsigned char*)((port)+_IO_BASE))41 #define outb(val, port) out_8((u nsigned char*)((port)+_IO_BASE), (val))42 #define inw(port) in_le16((u nsigned short *)((port)+_IO_BASE))43 #define outw(val, port) out_le16((u nsigned short *)((port)+_IO_BASE), (val))44 #define inl(port) in_le32((u nsigned*)((port)+_IO_BASE))45 #define outl(val, port) out_le32((u nsigned*)((port)+_IO_BASE), (val))41 #define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) 42 #define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) 43 #define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) 44 #define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) 45 #define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) 46 #define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) 46 47 47 48 /* … … 66 67 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. 67 68 */ 68 static inline int in_8(volatile unsigned char*addr)69 static inline uint8_t in_8(const volatile uint8_t *addr) 69 70 { 70 int ret;71 uint8_t ret; 71 72 72 73 __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); … … 74 75 } 75 76 76 static inline void out_8(volatile u nsigned char *addr, int val)77 static inline void out_8(volatile uint8_t *addr, uint8_t val) 77 78 { 78 79 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); 79 80 } 80 81 81 static inline int in_le16(volatile unsigned short *addr)82 static inline uint16_t in_le16(const volatile uint16_t *addr) 82 83 { 83 int ret;84 uint16_t ret; 84 85 85 86 __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : … … 88 89 } 89 90 90 static inline int in_be16(volatile unsigned short *addr)91 static inline uint16_t in_be16(const volatile uint16_t *addr) 91 92 { 92 int ret;93 uint16_t ret; 93 94 94 95 __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); … … 96 97 } 97 98 98 static inline void out_le16(volatile u nsigned short *addr, int val)99 static inline void out_le16(volatile uint16_t *addr, uint16_t val) 99 100 { 100 101 __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : … … 102 103 } 103 104 104 static inline void out_be16(volatile u nsigned short *addr, int val)105 static inline void out_be16(volatile uint16_t *addr, uint16_t val) 105 106 { 106 107 __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); 107 108 } 108 109 109 static inline u nsigned in_le32(volatile unsigned*addr)110 static inline uint32_t in_le32(const volatile uint32_t *addr) 110 111 { 111 u nsignedret;112 uint32_t ret; 112 113 113 114 __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : … … 116 117 } 117 118 118 static inline u nsigned in_be32(volatile unsigned*addr)119 static inline uint32_t in_be32(const volatile uint32_t *addr) 119 120 { 120 u nsignedret;121 uint32_t ret; 121 122 122 123 __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); … … 124 125 } 125 126 126 static inline void out_le32(volatile u nsigned *addr, int val)127 static inline void out_le32(volatile uint32_t *addr, uint32_t val) 127 128 { 128 129 __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : … … 130 131 } 131 132 132 static inline void out_be32(volatile u nsigned *addr, int val)133 static inline void out_be32(volatile uint32_t *addr, uint32_t val) 133 134 { 134 135 __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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