Changeset 2d2de4eb in rtems


Ignore:
Timestamp:
Oct 23, 2009, 7:32:46 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 5, master
Children:
d7637d8d
Parents:
cc1e864d
Message:

Update for exception support changes.

Location:
c/src/lib
Files:
103 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/clock/clock.c, shared/irq/irq_init.c,
     4        shared/irq/openpic_i8259_irq.c: Changed exception header file
     5        includes.
     6
    172009-10-20      Till Straumann <strauman@slac.stanford.edu>
    28
  • c/src/lib/libbsp/powerpc/ep1a/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq_init.c, irq/openpic_xxx_irq.c: Changed exception header file
     5        includes.
     6        * startup/bspstart.c: Update for ppc_exc_initialize() changes.
     7
    182009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/ep1a/Makefile.am

    rcc1e864d r2d2de4eb  
    6666
    6767include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \
    68         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
    69         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    7068        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    7169# irq
     
    8886
    8987libbsp_a_LIBADD = \
     88    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    9089    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    9190    ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
    9291    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    9392    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    94     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    9593    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    9694    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
  • c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2828#include <bsp/irq.h>
    2929#include <bsp.h>
    30 #include <libcpu/raw_exception.h>
     30#include <bsp/vectors.h>
    3131#include <bsp/motorola.h>
    3232#include <rtems/bspIo.h>
  • c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c

    rcc1e864d r2d2de4eb  
    1919#include <bsp/VMEConfig.h>
    2020#include <bsp/openpic.h>
    21 #include <libcpu/raw_exception.h>
    2221#include <libcpu/io.h>
    2322#include <bsp/vectors.h>
  • c/src/lib/libbsp/powerpc/ep1a/preinstall.am

    rcc1e864d r2d2de4eb  
    106106PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    107107
    108 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    109         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    110 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    111 
    112 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    113         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    114 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    115 
    116108$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    117109        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
  • c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    278278void bsp_start( void )
    279279{
    280   uint32_t intrStackStart;
    281   uint32_t intrStackSize;
     280  rtems_status_code sc = RTEMS_SUCCESSFUL;
     281  uintptr_t intrStackStart;
     282  uintptr_t intrStackSize;
    282283  ppc_cpu_id_t myCpu;
    283284  ppc_cpu_revision_t myCpuRevision;
     
    316317   * Initialize the interrupt related settings.
    317318   */
    318   intrStackStart = (uint32_t) __rtems_end;
     319  intrStackStart = (uintptr_t) __rtems_end;
    319320  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    320321
     
    322323   * Initialize default raw exception hanlders.
    323324   */
    324   ppc_exc_initialize(
     325  sc = ppc_exc_initialize(
    325326    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    326327    intrStackStart,
    327328    intrStackSize
    328329  );
     330  if (sc != RTEMS_SUCCESSFUL) {
     331    BSP_panic("cannot initialize exceptions");
     332  }
    329333
    330334  /*
  • c/src/lib/libbsp/powerpc/gen5200/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq.c: Changed exception header file includes.
     5        * startup/bspstart.c: Changed exception header file includes.  Update
     6        for ppc_exc_initialize() changes.
     7
    182009-10-22      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/gen5200/Makefile.am

    rcc1e864d r2d2de4eb  
    6969libbsp_a_SOURCES += ide/idecfg.c ide/pcmcia_ide.c ide/pcmcia_ide.h
    7070
    71 include_bsp_HEADERS = ../../../libcpu/@RTEMS_CPU@/new-exceptions/bspsupport/vectors.h \
    72         ../../../libcpu/@RTEMS_CPU@/new-exceptions/bspsupport/ppc_exc_bspsupp.h \
    73         ../../shared/include/irq-generic.h \
     71include_bsp_HEADERS = ../../shared/include/irq-generic.h \
    7472        include/irq-config.h \
    7573        include/irq.h \
     
    135133        ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
    136134        ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    137         ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    138135        ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    139136        ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
  • c/src/lib/libbsp/powerpc/gen5200/irq/irq.c

    rcc1e864d r2d2de4eb  
    7777
    7878#include <libcpu/powerpc-utility.h>
    79 #include <libcpu/raw_exception.h>
     79#include <bsp/vectors.h>
    8080
    8181#include <bsp.h>
    8282#include <bsp/irq.h>
    83 #include <bsp/vectors.h>
    84 #include <bsp/ppc_exc_bspsupp.h>
    8583#include <bsp/irq-generic.h>
    8684#include <bsp/mpc5200.h>
  • c/src/lib/libbsp/powerpc/gen5200/preinstall.am

    rcc1e864d r2d2de4eb  
    102102PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.pm520
    103103
    104 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/new-exceptions/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    105         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    107 
    108 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/new-exceptions/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    109         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    110 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    111 
    112104$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    113105        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
  • c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    9595/***********************************************************************/
    9696
    97 #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
     97#include <rtems.h>
    9898
    99 #include <rtems.h>
    10099#include <libcpu/powerpc-utility.h>
    101 #include <libcpu/raw_exception.h>
    102100
    103101#include <bsp.h>
     102#include <bsp/vectors.h>
    104103#include <bsp/bootcard.h>
    105 #include <bsp/ppc_exc_bspsupp.h>
    106 
    107104#include <bsp/irq.h>
     105#include <bsp/irq-generic.h>
    108106
    109107#if defined(HAS_UBOOT)
     
    133131void bsp_start(void)
    134132{
     133  rtems_status_code sc = RTEMS_SUCCESSFUL;
    135134  ppc_cpu_id_t myCpu;
    136135  ppc_cpu_revision_t myCpuRevision;
     
    171170  /* Initialize exception handler */
    172171  ppc_exc_cache_wb_check = 0;
    173   ppc_exc_initialize(
     172  sc = ppc_exc_initialize(
    174173    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    175     (uint32_t) bsp_interrupt_stack_start,
    176     (uint32_t) bsp_interrupt_stack_size
     174    (uintptr_t) bsp_interrupt_stack_start,
     175    (uintptr_t) bsp_interrupt_stack_size
    177176  );
     177  if (sc != RTEMS_SUCCESSFUL) {
     178    BSP_panic("cannot initialize exceptions");
     179  }
    178180
    179181  /* Initalize interrupt support */
    180   if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    181     BSP_panic( "Cannot intitialize interrupt support\n");
     182  sc = bsp_interrupt_initialize();
     183  if (sc != RTEMS_SUCCESSFUL) {
     184    BSP_panic("cannot intitialize interrupts");
    182185  }
    183186
  • c/src/lib/libbsp/powerpc/gen83xx/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq.c, irq/irq_init.c: Changed exception header file includes.
     5        * startup/bspstart.c: Changed exception header file includes.  Update
     6        for ppc_exc_initialize() changes.
     7
    182009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/gen83xx/Makefile.am

    rcc1e864d r2d2de4eb  
    6767        include/irq-config.h \
    6868        ../../shared/include/irq-generic.h \
     69        ../../shared/include/irq-info.h \
    6970        include/hwreg_vals.h \
    7071        ../shared/include/u-boot.h \
     
    7273
    7374# irq
    74 libbsp_a_SOURCES += include/irq.h \
    75         include/irq-config.h \
    76         irq/irq.c \
     75libbsp_a_SOURCES += irq/irq.c \
    7776        ../../shared/src/irq-generic.c \
    78         ../../shared/src/irq-legacy.c
     77        ../../shared/src/irq-legacy.c \
     78        ../../shared/src/irq-info.c \
     79        ../../shared/src/irq-shell.c \
     80        ../../shared/src/irq-server.c
    7981
    8082# console
     
    9698        ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    9799        ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    98         ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    99100        ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    100101        ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel   \
  • c/src/lib/libbsp/powerpc/gen83xx/include/tm27.h

    rcc1e864d r2d2de4eb  
    2525
    2626#include <libcpu/powerpc-utility.h>
    27 #include <libcpu/raw_exception.h>
    28 
    29 #include <bsp/ppc_exc_bspsupp.h>
     27#include <bsp/vectors.h>
    3028
    3129#define MUST_WAIT_FOR_INTERRUPT 1
  • c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c

    rcc1e864d r2d2de4eb  
    2323
    2424#include <libcpu/powerpc-utility.h>
    25 #include <libcpu/raw_exception.h>
     25#include <bsp/vectors.h>
    2626
    2727#include <bsp.h>
    2828#include <bsp/irq.h>
    29 #include <bsp/vectors.h>
    30 #include <bsp/ppc_exc_bspsupp.h>
    3129#include <bsp/irq-generic.h>
    3230
  • c/src/lib/libbsp/powerpc/gen83xx/preinstall.am

    rcc1e864d r2d2de4eb  
    102102PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
    103103
     104$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     105        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     106PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     107
    104108$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    105109        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
  • c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    2222
    2323#include <libcpu/powerpc-utility.h>
    24 #include <libcpu/raw_exception.h>
    2524
    2625#include <bsp.h>
     26#include <bsp/vectors.h>
    2727#include <bsp/bootcard.h>
    2828#include <bsp/irq-generic.h>
    29 #include <bsp/ppc_exc_bspsupp.h>
    3029
    3130#ifdef HAS_UBOOT
     
    8584{
    8685  rtems_status_code sc = RTEMS_SUCCESSFUL;
    87   int rv = 0;
    8886
    8987  ppc_cpu_id_t myCpu;
    9088  ppc_cpu_revision_t myCpuRevision;
    9189
    92   uint32_t interrupt_stack_start = (uint32_t) bsp_interrupt_stack_start;
    93   uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size;
     90  uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
     91  uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;
    9492
    9593  /*
     
    131129
    132130  /* Initialize exception handler */
    133   ppc_exc_initialize(
     131  sc = ppc_exc_initialize(
    134132    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    135133    interrupt_stack_start,
    136134    interrupt_stack_size
    137135  );
     136  if (sc != RTEMS_SUCCESSFUL) {
     137    BSP_panic("cannot initialize exceptions");
     138  }
    138139
    139140  /* Install default handler for the decrementer exception */
    140   rv = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
    141   if (rv < 0) {
    142     BSP_panic( "Cannot install decrementer exception handler!\n");
     141  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
     142  if (sc != RTEMS_SUCCESSFUL) {
     143    BSP_panic("cannot install decrementer exception handler");
    143144  }
    144145
     
    146147  sc = bsp_interrupt_initialize();
    147148  if (sc != RTEMS_SUCCESSFUL) {
    148     BSP_panic( "Cannot intitialize interrupt support\n");
     149    BSP_panic("cannot intitialize interrupts\n");
    149150  }
    150151
  • c/src/lib/libbsp/powerpc/haleakala/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq.c, include/tm27.h: Changed exception header file includes.
     5        * startup/bspstart.c: Changed exception header file includes.  Update
     6        for ppc_exc_initialize() changes.
     7
    182009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/haleakala/Makefile.am

    rcc1e864d r2d2de4eb  
    4747
    4848include_bsp_HEADERS += irq/irq.h \
    49     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    50     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \
    51     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
     49    ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    5250
    5351# irq
     
    5553
    5654libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    57     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    5855    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    5956    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
     57    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    6058    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    6159    ../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
  • c/src/lib/libbsp/powerpc/haleakala/irq/irq.c

    rcc1e864d r2d2de4eb  
    1515#include <bsp/irq.h>
    1616#include <bsp/irq_supp.h>
    17 #include <libcpu/raw_exception.h>
     17#include <bsp/vectors.h>
    1818#include <libcpu/powerpc-utility.h>
    1919
     
    167167 
    168168int
    169 C_dispatch_irq_handler( struct _BSP_Exception_frame* frame, unsigned int excNum )
     169C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum )
    170170{
    171171        if (excNum == ASM_EXT_VECTOR) {
  • c/src/lib/libbsp/powerpc/haleakala/irq/irq.h

    rcc1e864d r2d2de4eb  
    140140        #define BSP_UART_COM2_IRQ               BSP_UIC_UART1
    141141
    142         /* Define processor IRQ numbers; IRQs that are handled by the raw_exception vectors */
     142        /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */
    143143
    144144        #define BSP_PIT                         BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */
  • c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    1414#include <bsp/irq.h>
    1515#include <bsp.h>
    16 #include <libcpu/raw_exception.h>
     16#include <bsp/vectors.h>
    1717#include <rtems/bspIo.h>
    1818#include <rtems/powerpc/powerpc.h>
  • c/src/lib/libbsp/powerpc/haleakala/preinstall.am

    rcc1e864d r2d2de4eb  
    7878PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    7979
    80 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    81         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    82 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    83 
    8480$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8581        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
    8682PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    8783
    88 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    89         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    91 
  • c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    6565#include <bsp/uart.h>
    6666#include <bsp/irq.h>
    67 #include <rtems/bspIo.h>
    68 #include <libcpu/cpuIdent.h>
    69 #include <rtems/powerpc/powerpc.h>
    70 #include <bsp/ppc_exc_bspsupp.h>
     67#include <libcpu/powerpc-utility.h>
     68#include <bsp/vectors.h>
    7169#include <ppc4xx/ppc405gp.h>
    7270#include <ppc4xx/ppc405ex.h>
     
    172170void bsp_start( void )
    173171{
     172  rtems_status_code sc = RTEMS_SUCCESSFUL;
    174173  LINKER_SYMBOL(intrStack_start);
    175174  LINKER_SYMBOL(intrStack_size);
     
    206205   * Initialize default raw exception handlers.
    207206   */
    208   ppc_exc_initialize(
     207  sc = ppc_exc_initialize(
    209208    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    210     (uint32_t) intrStack_start,
    211     (uint32_t) intrStack_size);
     209    (uintptr_t) intrStack_start,
     210    (uintptr_t) intrStack_size
     211  );
     212  if (sc != RTEMS_SUCCESSFUL) {
     213    BSP_panic("cannot initialize exceptions");
     214  }
    212215
    213216  /*
  • c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-23      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * include/irq-config.h: New file.
     4        * Makefile.am, preinstall.am: Update for exception support changes.
     5        Use generic interrupt support.
     6        * make/custom/mbx8xx.inc, startup/linkcmds: Enable EABI.
     7        * irq/irq.c, startup/bspstart.c: Converted to generic interrupt
     8        support.  Update for exception support changes.
     9
    1102009-10-23      Ralf Corsépius <ralf.corsepius@rtems.org>
    211
  • c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am

    rcc1e864d r2d2de4eb  
    2222include_HEADERS += include/coverhd.h
    2323include_bsp_HEADERS = include/mbx.h include/commproc.h include/8xx_immap.h \
    24     irq/irq.h vectors/vectors.h
     24        irq/irq.h \
     25        include/irq-config.h \
     26        ../../shared/include/irq-generic.h \
     27        ../../shared/include/irq-info.h
    2528
    2629EXTRA_DIST = times-mbx821 times-mbx860
     
    3639libbsp_a_SOURCES += console/console.c
    3740# irq
    38 libbsp_a_SOURCES += irq/irq.c irq/irq_asm.S irq/irq_init.c
     41libbsp_a_SOURCES += irq/irq.c \
     42        ../../shared/src/irq-generic.c \
     43        ../../shared/src/irq-legacy.c \
     44        ../../shared/src/irq-info.c \
     45        ../../shared/src/irq-shell.c \
     46        ../../shared/src/irq-server.c
    3947# ide
    4048libbsp_a_SOURCES += ide/idecfg.c ide/pcmcia_ide.c
    41 # vectors
    42 libbsp_a_SOURCES += vectors/vectors.h vectors/vectors_init.c \
    43     vectors/vectors.S
    4449# startup
    4550libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \
     
    6267    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    6368    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    64     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
     69    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    6570    ../../../libcpu/@RTEMS_CPU@/mpc8xx/clock.rel \
    6671    ../../../libcpu/@RTEMS_CPU@/mpc8xx/console-generic.rel \
  • c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c

    rcc1e864d r2d2de4eb  
    22 *
    33 *  This file contains the implementation of the function described in irq.h
     4 *
     5 *  Copyright (c) 2009 embedded brains GmbH.
    46 *
    57 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
     
    1517#include <bsp.h>
    1618#include <bsp/irq.h>
    17 #include <rtems/score/thread.h>
    18 #include <rtems/score/apiext.h>
    19 #include <libcpu/raw_exception.h>
     19#include <bsp/irq-generic.h>
    2020#include <bsp/vectors.h>
    2121#include <bsp/8xx_immap.h>
     
    2323#include <bsp/commproc.h>
    2424
    25 /*
    26  * default handler connected on each irq after bsp initialization
    27  */
    28 static rtems_irq_connect_data   default_rtems_entry;
    29 
    30 /*
    31  * location used to store initial tables used for interrupt
    32  * management.
    33  */
    34 static rtems_irq_global_settings*       internal_config;
    35 static rtems_irq_connect_data*          rtems_hdl_tbl;
     25volatile unsigned int ppc_cached_irq_mask;
    3626
    3727/*
     
    4131{
    4232  return (((int) irqLine <= BSP_SIU_IRQ_MAX_OFFSET) &
    43           ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET)
    44         );
     33    ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET)
     34  );
    4535}
    4636
     
    5141{
    5242  return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
    53           ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
    54          );
    55 }
    56 
    57 /*
    58  * Check if symbolic IRQ name is a Processor IRQ
    59  */
    60 static inline int is_processor_irq(const rtems_irq_number irqLine)
    61 {
    62   return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
    63           ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    64          );
     43    ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
     44   );
    6545}
    6646
     
    8666};
    8767
    88 /*
    89  * ------------------------ RTEMS Irq helper functions ----------------
    90  */
    91 
    92 /*
    93  * Caution : this function assumes the variable "internal_config"
    94  * is already set and that the tables it contains are still valid
    95  * and accessible.
    96  */
    97 static void compute_SIU_IvectMask_from_prio (void)
    98 {
    99   /*
    100    * In theory this is feasible. No time to code it yet. See i386/shared/irq.c
    101    * for an example based on 8259 controller mask. The actual masks defined
    102    * correspond to the priorities defined for the SIU in irq_init.c.
    103    */
    104 }
    105 
    106 /*
    107  * This function check that the value given for the irq line
    108  * is valid.
    109  */
    110 
    111 static int isValidInterrupt(int irq)
    112 {
    113   if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) || (irq == BSP_CPM_INTERRUPT) )
    114     return 0;
    115   return 1;
    116 }
    117 
    11868int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine)
    11969{
     
    181131}
    182132
    183 int BSP_irq_enabled_at_siu      (const rtems_irq_number irqLine)
     133int BSP_irq_enabled_at_siu       (const rtems_irq_number irqLine)
    184134{
    185135  int siu_irq_index;
     
    192142}
    193143
    194 /*
    195  * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
    196  */
    197 
    198 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    199 {
    200     rtems_interrupt_level       level;
    201 
    202     if (!isValidInterrupt(irq->name)) {
    203       return 0;
    204     }
    205     /*
    206      * Check if default handler is actually connected. If not issue an error.
    207      * You must first get the current handler via i386_get_current_idt_entry
    208      * and then disconnect it using i386_delete_idt_entry.
    209      * RATIONALE : to always have the same transition by forcing the user
    210      * to get the previous handler before accepting to disconnect.
    211      */
    212     if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
    213       return 0;
    214     }
    215 
    216     rtems_interrupt_disable(level);
    217 
    218     /*
    219      * store the data provided by user
    220      */
    221     rtems_hdl_tbl[irq->name] = *irq;
    222 
    223     if (is_cpm_irq(irq->name)) {
    224       /*
    225        * Enable interrupt at PIC level
    226        */
    227       BSP_irq_enable_at_cpm (irq->name);
    228     }
    229 
    230     if (is_siu_irq(irq->name)) {
    231       /*
    232        * Enable interrupt at SIU level
    233        */
    234       BSP_irq_enable_at_siu (irq->name);
    235     }
    236 
    237     if (is_processor_irq(irq->name)) {
    238       /*
    239        * Should Enable exception at processor level but not needed.  Will restore
    240        * EE flags at the end of the routine anyway.
    241        */
    242     }
    243     /*
    244      * Enable interrupt on device
    245      */
    246         if (irq->on)
    247         irq->on(irq);
    248 
    249     rtems_interrupt_enable(level);
    250 
    251     return 1;
    252 }
    253 
    254 int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* irq)
    255 {
    256      if (!isValidInterrupt(irq->name)) {
    257       return 0;
    258      }
    259      *irq = rtems_hdl_tbl[irq->name];
    260      return 1;
    261 }
    262 
    263 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    264 {
    265     rtems_interrupt_level       level;
    266 
    267     if (!isValidInterrupt(irq->name)) {
    268       return 0;
    269     }
    270     /*
    271      * Check if default handler is actually connected. If not issue an error.
    272      * You must first get the current handler via i386_get_current_idt_entry
    273      * and then disconnect it using i386_delete_idt_entry.
    274      * RATIONALE : to always have the same transition by forcing the user
    275      * to get the previous handler before accepting to disconnect.
    276      */
    277     if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
    278       return 0;
    279     }
    280     rtems_interrupt_disable(level);
    281 
    282     if (is_cpm_irq(irq->name)) {
    283       /*
    284        * disable interrupt at PIC level
    285        */
    286       BSP_irq_disable_at_cpm (irq->name);
    287     }
    288     if (is_siu_irq(irq->name)) {
    289       /*
    290        * disable interrupt at OPENPIC level
    291        */
    292       BSP_irq_disable_at_siu (irq->name);
    293     }
    294     if (is_processor_irq(irq->name)) {
    295       /*
    296        * disable exception at processor level
    297        */
    298     }
    299 
    300     /*
    301      * Disable interrupt on device
    302      */
    303         if (irq->off)
    304         irq->off(irq);
    305 
    306     /*
    307      * restore the default irq value
    308      */
    309     rtems_hdl_tbl[irq->name] = default_rtems_entry;
    310 
    311     rtems_interrupt_enable(level);
    312 
    313     return 1;
    314 }
    315 
    316 /*
    317  * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
    318  */
    319 
    320 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
    321 {
    322     int                    i;
    323     rtems_interrupt_level  level;
    324 
    325     /*
    326      * Store various code accelerators
    327      */
    328     internal_config             = config;
    329     default_rtems_entry         = config->defaultEntry;
    330     rtems_hdl_tbl               = config->irqHdlTbl;
    331 
    332     rtems_interrupt_disable(level);
    333     /*
    334      * start with CPM IRQ
    335      */
    336     for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) {
    337       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    338         BSP_irq_enable_at_cpm (i);
    339         if (rtems_hdl_tbl[i].on)
    340                 rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    341       }
    342       else {
    343         if (rtems_hdl_tbl[i].off)
    344                 rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    345         BSP_irq_disable_at_cpm (i);
    346       }
    347     }
    348 
    349     /*
    350      * continue with PCI IRQ
    351      */
    352     /*
    353      * set up internal tables used by rtems interrupt prologue
    354      */
    355     compute_SIU_IvectMask_from_prio ();
    356 
    357     for (i=BSP_SIU_IRQ_LOWEST_OFFSET; i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ; i++) {
    358       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    359         BSP_irq_enable_at_siu (i);
    360         if (rtems_hdl_tbl[i].on)
    361                 rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    362       }
    363       else {
    364         if (rtems_hdl_tbl[i].off)
    365                 rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    366         BSP_irq_disable_at_siu (i);
    367        }
    368     }
    369     /*
    370      * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been
    371      * set up in BSP_CPM_irq_init.
    372      */
    373     ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN;
    374     BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT);
    375     /*
    376      * finish with Processor exceptions handled like IRQ
    377      */
    378     for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
    379       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    380         if (rtems_hdl_tbl[i].on)
    381                 rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    382       }
    383       else {
    384         if (rtems_hdl_tbl[i].off)
    385                 rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    386       }
    387     }
    388     rtems_interrupt_enable(level);
    389     return 1;
    390 }
    391 
    392 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
    393 {
    394     *config = internal_config;
    395     return 0;
    396 }
    397 
    398144#ifdef DISPATCH_HANDLER_STAT
    399145volatile unsigned int maxLoop = 0;
     
    403149 * High level IRQ handler called from shared_raw_irq_code_entry
    404150 */
    405 int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
     151int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
    406152{
    407153  register unsigned int irq;
    408154  register unsigned cpmIntr;                  /* boolean */
    409   register unsigned oldMask;                  /* old siu pic masks */
     155  register unsigned oldMask;          /* old siu pic masks */
    410156  register unsigned msr;
    411157  register unsigned new_msr;
     
    421167    _CPU_MSR_SET(new_msr);
    422168
    423     rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
     169    bsp_interrupt_handler_dispatch(BSP_DECREMENTER);
    424170
    425171    _CPU_MSR_SET(msr);
     
    483229    _CPU_MSR_SET(new_msr);
    484230
    485     rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
     231    bsp_interrupt_handler_dispatch(irq);
    486232
    487233    _CPU_MSR_SET(msr);
     
    506252}
    507253
    508 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    509 {
    510   /*
    511    * Process pending signals that have not already been
    512    * processed by _Thread_Displatch. This happens quite
    513    * unfrequently : the ISR must have posted an action
    514    * to the current running thread.
    515    */
    516   if ( _Thread_Do_post_task_switch_extension ||
    517        _Thread_Executing->do_post_task_switch_extension ) {
    518     _Thread_Executing->do_post_task_switch_extension = false;
    519     _API_extensions_Run_postswitch();
    520   }
    521   /*
    522    * I plan to process other thread related events here.
    523    * This will include DEBUG session requested from keyboard...
    524    */
    525 }
     254void BSP_SIU_irq_init(void)
     255{
     256  /*
     257   * In theory we should initialize two registers at least :
     258   * SIMASK, SIEL. SIMASK is reset at 0 value meaning no interrupt. But
     259   * we should take care that a monitor may have restoreed to another value.
     260   * If someone find a reasonnable value for SIEL, AND THE NEED TO CHANGE IT
     261   * please feel free to add it here.
     262   */
     263  ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = 0;
     264  ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 0xffff0000;
     265  ppc_cached_irq_mask = 0;
     266  ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel;
     267}
     268
     269/*
     270 * Initialize CPM interrupt management
     271 */
     272void
     273BSP_CPM_irq_init(void)
     274{
     275  /*
     276   * Initialize the CPM interrupt controller.
     277   */
     278  ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr =
     279#ifdef mpc860
     280    (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
     281#else
     282    (CICR_SCB_SCC2 | CICR_SCA_SCC1) |
     283#endif
     284    ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
     285  ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0;
     286
     287  ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN;
     288}
     289
     290rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
     291{
     292  if (is_cpm_irq(irqnum)) {
     293    /*
     294     * Enable interrupt at PIC level
     295     */
     296    BSP_irq_enable_at_cpm (irqnum);
     297  }
     298
     299  if (is_siu_irq(irqnum)) {
     300    /*
     301     * Enable interrupt at SIU level
     302     */
     303    BSP_irq_enable_at_siu (irqnum);
     304  }
     305
     306  return RTEMS_SUCCESSFUL;
     307}
     308
     309rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
     310{
     311  if (is_cpm_irq(irqnum)) {
     312    /*
     313     * disable interrupt at PIC level
     314     */
     315    BSP_irq_disable_at_cpm (irqnum);
     316  }
     317  if (is_siu_irq(irqnum)) {
     318    /*
     319     * disable interrupt at OPENPIC level
     320     */
     321    BSP_irq_disable_at_siu (irqnum);
     322  }
     323
     324  return RTEMS_SUCCESSFUL;
     325}
     326
     327rtems_status_code bsp_interrupt_facility_initialize()
     328{
     329  /* Install exception handler */
     330  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
     331    return RTEMS_IO_ERROR;
     332  }
     333  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
     334    return RTEMS_IO_ERROR;
     335  }
     336
     337  /* Initialize the interrupt controller */
     338  BSP_SIU_irq_init();
     339  BSP_CPM_irq_init();
     340
     341  /*
     342   * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been
     343   * set up in BSP_CPM_irq_init.
     344   */
     345  ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN;
     346  BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT);
     347
     348  return RTEMS_SUCCESSFUL;
     349}
     350
     351void bsp_interrupt_handler_default( rtems_vector_number vector)
     352{
     353  printk( "Spurious interrupt: 0x%08x\n", vector);
     354}
  • c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc

    rcc1e864d r2d2de4eb  
    4141#  and (hopefully) optimize for it.
    4242#
    43 CPU_CFLAGS = -mcpu=$(8XX_CPU_TYPE) -Dmpc$(8XX_CPU_TYPE) -D$(RTEMS_MBX_MODEL)
     43CPU_CFLAGS = -mcpu=$(8XX_CPU_TYPE) -Dmpc$(8XX_CPU_TYPE) -D$(RTEMS_MBX_MODEL) \
     44        -meabi -msdata -fno-common
    4445
    4546# optimize flag: typically -O2
  • c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am

    rcc1e864d r2d2de4eb  
    6969PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    7070
    71 $(PROJECT_INCLUDE)/bsp/vectors.h: vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    72         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    73 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
     71$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     72        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
     73PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
     74
     75$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     76        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     77PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     78
     79$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     80        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     81PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
    7482
    7583$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
  • c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    1919 */
    2020
    21 #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
    22 
    2321#include <bsp.h>
    2422#include <bsp/irq.h>
     
    2927
    3028SPR_RW(SPRG1)
    31 
    32 extern unsigned long intrStackPtr;
    3329
    3430/*
     
    4541uint32_t   bsp_timer_least_valid;      /* Least valid number from timer      */
    4642bool       bsp_timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
     43
     44extern char IntrStack_start [];
     45extern char intrStack [];
    4746
    4847void BSP_panic(char *s)
     
    8483void bsp_start(void)
    8584{
     85  rtems_status_code sc = RTEMS_SUCCESSFUL;
    8686  ppc_cpu_id_t myCpu;
    8787  ppc_cpu_revision_t myCpuRevision;
    88   register unsigned char* intrStack;
    8988
    9089  /*
     
    113112#endif
    114113#endif
    115   /*
    116    * Initialize some SPRG registers related to irq handling
    117    */
    118114
    119   intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
    120   _write_SPRG1((unsigned int)intrStack);
     115  /* Initialize exception handler */
     116  sc = ppc_exc_initialize(
     117    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     118    (uintptr_t) IntrStack_start,
     119    (uintptr_t) intrStack - (uintptr_t) IntrStack_start
     120  );
     121  if ( sc != RTEMS_SUCCESSFUL ) {
     122    BSP_panic( "cannot initialize exceptions" );
     123  }
    121124
    122   /*
    123    * Install our own set of exception vectors
    124    */
    125   initialize_exceptions();
     125  /* Initalize interrupt support */
     126  sc = bsp_interrupt_initialize();
     127  if ( sc != RTEMS_SUCCESSFUL ) {
     128    BSP_panic( "cannot initialize interrupts" );
     129  }
    126130
    127131  /*
     
    166170  m8xx.scc2p.tbase=0;
    167171  m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );
    168   /*
    169    * Initalize RTEMS IRQ system
    170    */
    171   BSP_rtems_irq_mng_init(0);
     172
    172173#ifdef SHOW_MORE_INIT_SETTINGS
    173174  printk("Exit from bspstart\n");
  • c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds

    rcc1e864d r2d2de4eb  
    2222 
    2323MEMORY
    24         {
    25         ram : org = 0x0, l = 4M
    26         nvram : org = 0xfa000000, l = 32K
    27         dpram : org = 0xfa200000, l = 16K
    28         flash : org = 0xfc000000, l = 2M
    29         immr  : org = 0xfa200000, l = 16K
    30         }
     24  {
     25    ram : org = 0x0, l = 4M
     26    nvram : org = 0xfa000000, l = 32K
     27    dpram : org = 0xfa200000, l = 16K
     28    flash : org = 0xfc000000, l = 2M
     29    immr  : org = 0xfa200000, l = 16K
     30  }
    3131
    3232
     
    4646   *  the text section.
    4747   */
    48        
     48 
    4949  .text 0x10000:
    5050  {
     
    5959    /* Actual code */
    6060    *(.text*)
    61              
     61       
    6262    /* C++ constructors/destructors */
    6363    *(.gnu.linkonce.t*)
    64              
     64       
    6565    /*  Initialization and finalization code.
    6666     *
     
    9292     */
    9393     
    94     PROVIDE (__CTOR_LIST__ = .);             
     94    PROVIDE (__CTOR_LIST__ = .);       
    9595    /* LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) */
    9696    *crtbegin.o(.ctors)
     
    9999    LONG(0)
    100100    PROVIDE (__CTOR_END__ = .);
    101        
     101 
    102102    PROVIDE (__DTOR_LIST__ = .);
    103103    /* LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) */
     
    107107    LONG(0)
    108108    PROVIDE (__DTOR_END__ = .);
    109        
     109 
    110110    /*
    111111     * Special FreeBSD sysctl sections.
     
    193193    *(.data1)
    194194   
    195     PROVIDE (__SDATA_START__ = .);
    196     *(.sdata*)
    197     *(.gnu.linkonce.d*)
    198     *(.gnu.linkonce.s.*)
    199     PROVIDE (__SDATA_END__ = .);
    200    
    201195    PROVIDE (__EXCEPT_START__ = .);
    202196    *(.gcc_except_table*)
     
    207201    *(.got)
    208202    PROVIDE(__GOT_END__ = .);
    209        
     203 
    210204    *(.got1)
    211205   
     
    215209    PROVIDE (__GOT2_END__ = .);
    216210    PROVIDE (_GOT2_END_ = .);
    217        
     211 
    218212    PROVIDE (__FIXUP_START__ = .);
    219213    PROVIDE (_FIXUP_START_ = .);
     
    221215    PROVIDE (_FIXUP_END_ = .);
    222216    PROVIDE (__FIXUP_END__ = .);
    223 
    224   /*  We want the small data sections together, so single-instruction offsets
    225    *   can access them all.
    226    */
    227     PROVIDE (__SDATA2_START__ = .);
    228     *(.sdata2)
    229     *(.gnu.linkonce.s2.*)
    230     *(.sbss2)
    231     PROVIDE (__SDATA2_END__ = .);
    232217  } > ram
    233        
    234          
     218 
     219  .sdata : {
     220    PROVIDE (_SDA_BASE_ = 32768);
     221    *(.sdata .sdata.* .gnu.linkonce.s.*)
     222  } > ram
     223
     224  .sbss : {
     225    __bss_start = .;
     226
     227    PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);
     228    *(.scommon)
     229    *(.dynsbss)
     230    *(.sbss .sbss.* .gnu.linkonce.sb.*)
     231    PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);
     232  } > ram
     233
     234  .sdata2 : {
     235    PROVIDE (_SDA2_BASE_ = 32768);
     236
     237    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
     238  } > ram =0
     239
     240  .sbss2 : {
     241    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
     242  } > ram =0
     243   
    235244  .bss :
    236245  {
    237     PROVIDE (__SBSS_START__ = .);
    238        
    239     PROVIDE (__SBSS2_START__ = .);
    240     *(.sbss2)
    241     PROVIDE (__SBSS2_END__ = .);
    242        
    243246    bss.start = .;
    244247    *(.bss .bss* .gnu.linkonce.b*)
    245     *(.sbss*)
    246248    *(COMMON)
    247249    . = ALIGN(4);
    248250    bss.end = .;
    249    
    250    PROVIDE (__SBSS_END__ = .);
    251251
    252252  } > ram
  • c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4
    152009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    26
  • c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am

    rcc1e864d r2d2de4eb  
    8181
    8282include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \
    83         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \
    84         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    85         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
     83        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    8684
    8785# irq
     
    134132libbsp_a_LIBADD = \
    135133    polledIO.rel \
     134    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    136135    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    137136    ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
    138137    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    139138    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    140     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    141139    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    142140    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
  • c/src/lib/libbsp/powerpc/motorola_powerpc/preinstall.am

    rcc1e864d r2d2de4eb  
    9898PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    9999
    100 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    101         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    102 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    103 
    104 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    105         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    107 
    108100$(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    109101        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h
  • c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am: Update for exception support changes.
     4        * startup/bspstart.c: Changed exception header file includes.  Update
     5        for ppc_exc_initialize() changes.
     6
    172009-10-21      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am

    rcc1e864d r2d2de4eb  
    8484    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/esci.rel \
    8585    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    86     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    8786    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel
    8887
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    2626
    2727#include <libcpu/powerpc-utility.h>
     28#include <bsp/vectors.h>
    2829
    2930#include <bsp.h>
     
    3132#include <bsp/irq.h>
    3233#include <bsp/irq-generic.h>
    33 #include <bsp/ppc_exc_bspsupp.h>
    3434
    3535#define RTEMS_STATUS_CHECKS_USE_PRINTK
     
    189189void bsp_start(void)
    190190{
     191        rtems_status_code sc = RTEMS_SUCCESSFUL;
    191192        ppc_cpu_id_t myCpu;
    192193        ppc_cpu_revision_t myCpuRevision;
     
    225226        /* Initialize exceptions */
    226227        RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n");
    227         ppc_exc_initialize(
    228           PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    229           interrupt_stack_start,
    230           interrupt_stack_size
    231         );
    232         DEBUG_DONE();
     228        sc = ppc_exc_initialize(
     229                PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     230                interrupt_stack_start,
     231                interrupt_stack_size
     232        );
     233        if (sc != RTEMS_SUCCESSFUL) {
     234                BSP_panic( "Cannot initialize exceptions");
     235        } else {
     236                DEBUG_DONE();
     237        }
    233238
    234239        /* Initialize interrupts */
    235240        RTEMS_DEBUG_PRINT( "Initialize interrupts ...\n");
    236         if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
     241        sc = bsp_interrupt_initialize();
     242        if (sc != RTEMS_SUCCESSFUL) {
    237243                BSP_panic( "Cannot initialize interrupts");
    238244        } else {
  • c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * include/irq-config.h: New file.
     4        * Makefile.am, preinstall.am: Update for exception support changes.
     5        Use generic interrupt support.
     6        * make/custom/mpc8260ads.cfg, startup/linkcmds: Enable EABI.
     7        * irq/irq.c, startup/bspstart.c: Converted to generic interrupt
     8        support.  Update for exception support changes.
     9
    1102009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    211
  • c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am

    rcc1e864d r2d2de4eb  
    3636libbsp_a_SOURCES += console/console.c
    3737
    38 include_bsp_HEADERS = irq/irq.h
     38include_bsp_HEADERS = irq/irq.h \
     39        include/irq-config.h \
     40        ../../shared/include/irq-generic.h \
     41        ../../shared/include/irq-info.h
     42
    3943# irq
    40 libbsp_a_SOURCES += irq/irq.c irq/irq_init.c irq/irq.h irq/irq_asm.S
     44libbsp_a_SOURCES += irq/irq.c \
     45        ../../shared/src/irq-generic.c \
     46        ../../shared/src/irq-legacy.c \
     47        ../../shared/src/irq-info.c \
     48        ../../shared/src/irq-shell.c \
     49        ../../shared/src/irq-server.c
    4150
    42 include_bsp_HEADERS += vectors/vectors.h
    4351# startup
    4452libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \
     
    4755    ../../shared/sbrk.c ../../shared/gnatinstallhandler.c startup/cpuinit.c \
    4856    ../../shared/bspgetworkarea.c ../../shared/bsppretaskinghook.c
    49 
    50 # vectors
    51 libbsp_a_SOURCES += vectors/vectors_init.c vectors/vectors.h \
    52     vectors/vectors.S
    5357
    5458if HAS_NETWORKING
     
    6468    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    6569    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     70    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    6671    ../../../libcpu/@RTEMS_CPU@/mpc8260/clock.rel \
    6772    ../../../libcpu/@RTEMS_CPU@/mpc8260/console-generic.rel \
    6873    ../../../libcpu/@RTEMS_CPU@/mpc8260/cpm.rel \
    6974    ../../../libcpu/@RTEMS_CPU@/mpc8260/mmu.rel \
    70     ../../../libcpu/@RTEMS_CPU@/mpc8260/timer.rel \
    71     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel
     75    ../../../libcpu/@RTEMS_CPU@/mpc8260/timer.rel
    7276if HAS_NETWORKING
    7377libbsp_a_LIBADD += network.rel
  • c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c

    rcc1e864d r2d2de4eb  
    77 *  Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk>
    88 *  Surrey Satellite Technology Limited, 2000
    9 +  *    21/4/2002 Added support for nested interrupts and improved
    10 +  *    masking operations.  Now we compute priority mask based
    11 +  *            on table in irq_init.c
     9 *    21/4/2002 Added support for nested interrupts and improved
     10 *    masking operations.  Now we compute priority mask based
     11 *     on table in irq_init.c
    1212 *
    1313 *  The license and distribution terms for this file may be
     
    2020#include <bsp.h>
    2121#include <bsp/irq.h>
     22#include <bsp/irq-generic.h>
    2223#include <rtems.h>
    23 #include <rtems/score/apiext.h>
    2424#include <rtems/bspIo.h>
    25 #include <libcpu/raw_exception.h>
    2625#include <bsp/vectors.h>
    2726#include <mpc8260.h>
    2827
    2928/*
    30  * default handler connected on each irq after bsp initialization
    31  */
    32 static rtems_irq_connect_data   default_rtems_entry;
    33 
    34 /*
    35  * location used to store initial tables used for interrupt
    36  * management.
    37  */
    38 static rtems_irq_global_settings*       internal_config;
    39 static rtems_irq_connect_data*          rtems_hdl_tbl;
    40 
    41 /*
    4229 * Check if symbolic IRQ name is an CPM IRQ
    4330 */
    4431static inline int is_cpm_irq(const rtems_irq_number irqLine)
    4532{
    46         return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
    47                         ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
    48         );
    49 }
    50 
    51 /*
    52  * Check if symbolic IRQ name is a Processor IRQ
    53  */
    54 static inline int is_processor_irq(const rtems_irq_number irqLine)
    55 {
    56         return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
    57                         ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    58         );
     33  return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
     34      ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
     35  );
    5936}
    6037
    6138typedef struct {
    62         uint32_t         mask_h;        /* mask for sipnr_h and simr_h */
    63         uint32_t         mask_l;        /* mask for sipnr_l and simr_l */
    64         uint32_t         priority_h;  /* mask this and lower priority ints */
    65         uint32_t         priority_l;
     39  uint32_t         mask_h;  /* mask for sipnr_h and simr_h */
     40  uint32_t         mask_l;  /* mask for sipnr_l and simr_l */
     41  uint32_t         priority_h;  /* mask this and lower priority ints */
     42  uint32_t         priority_l;
    6643} m82xxIrqMasks_t;
     44
     45static unsigned char irqPrioTable[BSP_CPM_IRQ_NUMBER]={
     46  /*
     47   * actual priorities for interrupt :
     48   */
     49  /*
     50   * CPM Interrupts
     51   */
     52  0,  45, 63, 44, 66, 68, 35, 39, 50, 62, 34,  0,  30, 40, 52, 58,
     53  2,  3,  0,  5,  15, 16, 17, 18, 49, 51,  0,  0,  0,  0,  0,  0,
     54  6,  7,  8,  0,  11, 12, 0,  0,  20, 21, 22,  23, 0,  0,  0,  0,
     55  29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57,  60, 64, 65, 69, 70,
     56
     57};
    6758
    6859/*
    6960 *  Mask fields should have a '1' in the bit position for that
    7061 *  interrupt.
    71  *      Priority masks calculated later based on priority table
     62 *  Priority masks calculated later based on priority table
    7263 */
    7364
    7465static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
    7566{
    76         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
    77         { 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
    78         { 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
    79         { 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
    80         { 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
    81         { 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
    82         { 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
    83         { 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
    84         { 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
    85         { 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
    86         { 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
    87         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    88         { 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
    89         { 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
    90         { 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
    91         { 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
    92         { 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
    93         { 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
    94         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    95         { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
    96         { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
    97         { 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
    98         { 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
    99         { 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
    100         { 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
    101         { 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
    102         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    103         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    104         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    105         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    106         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    107         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    108         { 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
    109         { 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
    110         { 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
    111         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    112         { 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
    113         { 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
    114         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    115         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    116         { 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
    117         { 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
    118         { 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
    119         { 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
    120         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    121         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    122         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    123         { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
    124         { 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
    125         { 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
    126         { 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
    127         { 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
    128         { 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
    129         { 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
    130         { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
    131         { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
    132         { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
    133         { 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
    134         { 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
    135         { 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
    136         { 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
    137         { 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
    138         { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
    139         { 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
     67  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
     68  { 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
     69  { 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
     70  { 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
     71  { 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
     72  { 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
     73  { 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
     74  { 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
     75  { 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
     76  { 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
     77  { 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
     78  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     79  { 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
     80  { 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
     81  { 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
     82  { 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
     83  { 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
     84  { 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
     85  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     86  { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
     87  { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
     88  { 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
     89  { 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
     90  { 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
     91  { 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
     92  { 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
     93  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     94  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     95  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     96  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     97  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     98  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     99  { 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
     100  { 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
     101  { 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
     102  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     103  { 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
     104  { 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
     105  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     106  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     107  { 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
     108  { 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
     109  { 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
     110  { 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
     111  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     112  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     113  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     114  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
     115  { 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
     116  { 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
     117  { 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
     118  { 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
     119  { 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
     120  { 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
     121  { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
     122  { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
     123  { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
     124  { 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
     125  { 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
     126  { 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
     127  { 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
     128  { 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
     129  { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
     130  { 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
    140131
    141132};
    142 
    143 void dump_irq_masks(void )
    144 {
    145         int i;
    146         for( i=0; i<BSP_CPM_IRQ_NUMBER;i++ )
    147         {
    148                 printk( "%04d: %08X %08X\n",
    149                         i,
    150                         SIU_MaskBit[i].priority_h,
    151                         SIU_MaskBit[i].priority_l
    152                 );
    153         }
    154 }
    155133
    156134/*
     
    165143static void compute_SIU_IvectMask_from_prio (void)
    166144{
    167         /*
    168          * The actual masks defined
    169          * correspond to the priorities defined
    170          * for the SIU in irq_init.c.
    171          */
    172 
    173          int i,j;
    174 
    175          for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
    176          {
    177                 for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
    178                         if( internal_config->irqPrioTbl[j] < internal_config->irqPrioTbl[i] )
    179                         {
    180                                 SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
    181                                 SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
    182                         }
    183          }
    184 
    185 }
    186 
    187 /*
    188  * This function check that the value given for the irq line
    189  * is valid.
    190  */
    191 
    192 static int isValidInterrupt(int irq)
    193 {
    194         if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) )
    195                 return 0;
    196         return 1;
    197 }
     145  /*
     146   * The actual masks defined
     147   * correspond to the priorities defined
     148   * for the SIU in irq_init.c.
     149   */
     150
     151   int i,j;
     152
     153   for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
     154   {
     155     for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
     156       if( irqPrioTable[j] < irqPrioTable[i] )
     157       {
     158        SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
     159        SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
     160      }
     161   }
     162
     163}
     164
    198165
    199166int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine)
    200167{
    201         int cpm_irq_index;
    202 
    203         if (!is_cpm_irq(irqLine))
    204                 return 1;
    205 
    206         cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
    207 
    208         m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
    209         m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
    210 
    211         return 0;
     168  int cpm_irq_index;
     169
     170  if (!is_cpm_irq(irqLine))
     171    return 1;
     172
     173  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
     174
     175  m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
     176  m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
     177
     178  return 0;
    212179}
    213180
    214181int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine)
    215182{
    216         int cpm_irq_index;
    217 
    218         if (!is_cpm_irq(irqLine))
    219                 return 1;
    220 
    221         cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
    222 
    223         m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
    224         m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
    225 
    226         return 0;
    227 }
    228 
    229 int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)
    230 {
    231         int cpm_irq_index;
    232 
    233         if (!is_cpm_irq(irqLine))
    234                 return 0;
    235 
    236         cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
    237 
    238         return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
    239                     (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
    240 }
    241 
    242 /*
    243  * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
    244  */
    245 
    246 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    247 {
    248         rtems_interrupt_level level;
    249 
    250         if (!isValidInterrupt(irq->name)) {
    251                 printk( "not a valid intr\n" ) ;
    252                 return 0;
    253         }
    254         /*
    255          * Check if default handler is actually connected. If not issue an error.
    256          * You must first get the current handler via i386_get_current_idt_entry
    257          * and then disconnect it using i386_delete_idt_entry.
    258          * RATIONALE : to always have the same transition by forcing the user
    259          * to get the previous handler before accepting to disconnect.
    260          */
    261         if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
    262                 printk( "Default handler not there\n" );
    263                 return 0;
    264         }
    265 
    266         rtems_interrupt_disable(level);
    267 
    268         /*
    269          * store the data provided by user
    270          */
    271         rtems_hdl_tbl[irq->name] = *irq;
    272 
    273         if (is_cpm_irq(irq->name)) {
    274             /*
    275              * Enable interrupt at PIC level
    276              */
    277             BSP_irq_enable_at_cpm (irq->name);
    278         }
    279 
     183  int cpm_irq_index;
     184
     185  if (!is_cpm_irq(irqLine))
     186    return 1;
     187
     188  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
     189
     190  m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
     191  m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
     192
     193  return 0;
     194}
     195                                                                                             
     196int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)                                 
     197{                                                                                           
     198       int cpm_irq_index;                                                                   
     199                                                                                           
     200       if (!is_cpm_irq(irqLine))                                                           
     201               return 0;                                                                   
     202                                                                                           
     203       cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);                       
     204                                                                                           
     205       return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||                       
     206                   (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));                     
     207}
     208
     209#ifdef DISPATCH_HANDLER_STAT
     210volatile unsigned int maxLoop = 0;
     211#endif
     212
     213/*
     214 * High level IRQ handler called from shared_raw_irq_code_entry
     215 */
     216int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
     217{
     218  register unsigned int irq;
    280219#if 0
    281         if (is_processor_irq(irq->name)) {
    282                 /*
    283                  * Should Enable exception at processor level but not needed.  Will restore
    284                  * EE flags at the end of the routine anyway.
    285                  */
    286         }
    287 #endif
    288 
    289         /*
    290          * Enable interrupt on device
    291          */
    292         if (irq->on)
    293                 irq->on(irq);
    294 
    295         rtems_interrupt_enable(level);
    296 
    297         /*
    298             printk( "Enabled\n" );
    299         */
    300         return 1;
    301 }
    302 
    303 int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* irq)
    304 {
    305         if (!isValidInterrupt(irq->name)) {
    306                 return 0;
    307         }
    308         *irq = rtems_hdl_tbl[irq->name];
    309         return 1;
    310 }
    311 
    312 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    313 {
    314         rtems_interrupt_level level;
    315 
    316         if (!isValidInterrupt(irq->name)) {
    317                 return 0;
    318         }
    319         /*
    320          * Check if default handler is actually connected. If not issue an error.
    321          * You must first get the current handler via i386_get_current_idt_entry
    322          * and then disconnect it using i386_delete_idt_entry.
    323          * RATIONALE : to always have the same transition by forcing the user
    324          * to get the previous handler before accepting to disconnect.
    325          */
    326         if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
    327           return 0;
    328         }
    329         rtems_interrupt_disable(level);
    330 
    331         if (is_cpm_irq(irq->name)) {
    332           /*
    333            * disable interrupt at PIC level
    334            */
    335           BSP_irq_disable_at_cpm (irq->name);
    336         }
    337 
    338         if (is_processor_irq(irq->name)) {
    339           /*
    340            * disable exception at processor level
    341            */
    342         }
    343 
    344         /*
    345          * Disable interrupt on device
    346          */
    347         if (irq->off)
    348                 irq->off(irq);
    349 
    350         /*
    351          * restore the default irq value
    352          */
    353         rtems_hdl_tbl[irq->name] = default_rtems_entry;
    354 
    355         rtems_interrupt_enable(level);
    356 
    357         return 1;
    358 }
    359 
    360 /*
    361  * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
    362  */
    363 
    364 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
    365 {
    366         int                   i;
    367         rtems_interrupt_level level;
    368 
    369         /*
    370          * Store various code accelerators
    371          */
    372         internal_config                 = config;
    373         default_rtems_entry             = config->defaultEntry;
    374         rtems_hdl_tbl           = config->irqHdlTbl;
    375 
    376         /* Fill in priority masks */
    377         compute_SIU_IvectMask_from_prio();
    378 
    379         rtems_interrupt_disable(level);
    380         /*
    381          * start with CPM IRQ
    382          */
    383         for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) {
    384                 if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    385                         BSP_irq_enable_at_cpm (i);
    386                         if (rtems_hdl_tbl[i].on)
    387                                 rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    388                 } else {
    389                         if (rtems_hdl_tbl[i].off)
    390                                 rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    391                         BSP_irq_disable_at_cpm (i);
    392                 }
    393         }
    394 
    395         /*
    396          * finish with Processor exceptions handled like IRQ
    397          */
    398         for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
    399                 if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    400                         if (rtems_hdl_tbl[i].on)
    401                                 rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    402                 } else {
    403                         if (rtems_hdl_tbl[i].off)
    404                                 rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    405                 }
    406         }
    407 
    408         rtems_interrupt_enable(level);
    409         return 1;
    410 }
    411 
    412 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
    413 {
    414         *config = internal_config;
    415         return 0;
    416 }
    417 
    418 #ifdef DISPATCH_HANDLER_STAT
    419 volatile unsigned int maxLoop = 0;
    420 #endif
    421 
    422 /*
    423  * High level IRQ handler called from shared_raw_irq_code_entry
    424  */
    425 int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
    426 {
    427         register unsigned int irq;
    428 #if 0
    429         register unsigned oldMask;                    /* old siu pic masks */
    430 #endif
    431         register unsigned msr;
    432         register unsigned new_msr;
    433         register unsigned old_simr_h;
    434         register unsigned old_simr_l;
    435 #ifdef DISPATCH_HANDLER_STAT
    436         unsigned loopCounter;
    437 #endif
    438 
    439         /*
    440          * Handle decrementer interrupt
    441          */
    442         if (excNum == ASM_DEC_VECTOR) {
    443                 _CPU_MSR_GET(msr);
    444                 new_msr = msr | MSR_EE;
    445                 _CPU_MSR_SET(new_msr);
    446 
    447                 rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
    448 
    449                 _CPU_MSR_SET(msr);
    450 
    451                 return 0;
    452         }
    453 
    454         /*
    455          * Handle external interrupt generated by SIU on PPC core
    456          */
    457 #ifdef DISPATCH_HANDLER_STAT
    458         loopCounter = 0;
    459 #endif
    460 
    461         while (1) {
    462 
    463                 if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
    464 #ifdef DISPATCH_HANDLER_STAT
    465                         if (loopCounter >  maxLoop) maxLoop = loopCounter;
    466 #endif
    467                         break;
    468                 }
    469 
    470                 irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
    471 
    472                 /* Clear mask and pending register */
    473                 if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
    474                         /* save interrupt masks */
    475                         old_simr_h = m8260.simr_h;
    476                         old_simr_l = m8260.simr_l;
    477 
    478                         /* mask off current interrupt and lower priority ones */
    479                         m8260.simr_h &= SIU_MaskBit[irq].priority_h;
    480                         m8260.simr_l &= SIU_MaskBit[irq].priority_l;
    481 
    482                         /* clear pending bit */
    483                         m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
    484                         m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
    485 
    486                         /*
    487                          * make sure, that the masking operations in
    488                          * ICTL and MSR are executed in order
    489                          */
    490                         asm volatile("sync":::"memory");
    491 
    492                         /* re-enable external exceptions */
    493                         _CPU_MSR_GET(msr);
    494                         new_msr = msr | MSR_EE;
    495                         _CPU_MSR_SET(new_msr);
    496 
    497                         /* call handler */
    498                         rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
    499 
    500                         /* disable exceptions again */
    501                         _CPU_MSR_SET(msr);
    502 
    503                         /*
    504                          * make sure, that the masking operations in
    505                          * ICTL and MSR are executed in order
    506                          */
    507                         asm volatile("sync":::"memory");
    508 
    509                         /* restore interrupt masks */
    510                         m8260.simr_h = old_simr_h;
    511                         m8260.simr_l = old_simr_l;
    512 
    513                 }
    514 #ifdef DISPATCH_HANDLER_STAT
    515                 ++ loopCounter;
    516 #endif
    517         }
    518         return 0;
    519 }
    520 
    521 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    522 {
    523         /*
    524          * Process pending signals that have not already been
    525          * processed by _Thread_Displatch. This happens quite
    526          * unfrequently : the ISR must have posted an action
    527          * to the current running thread.
    528          */
    529         if ( _Thread_Do_post_task_switch_extension ||
    530                 _Thread_Executing->do_post_task_switch_extension ) {
    531                 _Thread_Executing->do_post_task_switch_extension = false;
    532                 _API_extensions_Run_postswitch();
    533         }
    534 
    535         /*
    536          * I plan to process other thread related events here.
    537          * This will include DEBUG session requested from keyboard...
    538          */
    539 }
     220  register unsigned oldMask;          /* old siu pic masks */
     221#endif
     222  register unsigned msr;
     223  register unsigned new_msr;
     224  register unsigned old_simr_h;
     225  register unsigned old_simr_l;
     226#ifdef DISPATCH_HANDLER_STAT
     227  unsigned loopCounter;
     228#endif
     229
     230  /*
     231   * Handle decrementer interrupt
     232   */
     233  if (excNum == ASM_DEC_VECTOR) {
     234    _CPU_MSR_GET(msr);
     235    new_msr = msr | MSR_EE;
     236    _CPU_MSR_SET(new_msr);
     237
     238    bsp_interrupt_handler_dispatch(BSP_DECREMENTER);
     239
     240    _CPU_MSR_SET(msr);
     241
     242    return 0;
     243  }
     244
     245  /*
     246   * Handle external interrupt generated by SIU on PPC core
     247   */
     248#ifdef DISPATCH_HANDLER_STAT
     249  loopCounter = 0;
     250#endif
     251
     252  while (1) {
     253
     254    if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
     255#ifdef DISPATCH_HANDLER_STAT
     256      if (loopCounter >  maxLoop) maxLoop = loopCounter;
     257#endif
     258      break;
     259    }
     260
     261    irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
     262
     263    /* Clear mask and pending register */
     264    if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
     265      /* save interrupt masks */
     266      old_simr_h = m8260.simr_h;
     267      old_simr_l = m8260.simr_l;
     268
     269      /* mask off current interrupt and lower priority ones */
     270      m8260.simr_h &= SIU_MaskBit[irq].priority_h;
     271      m8260.simr_l &= SIU_MaskBit[irq].priority_l;
     272
     273      /* clear pending bit */
     274      m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
     275      m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
     276
     277      /*
     278       * make sure, that the masking operations in
     279       * ICTL and MSR are executed in order
     280       */
     281      asm volatile("sync":::"memory");
     282
     283      /* re-enable external exceptions */
     284      _CPU_MSR_GET(msr);
     285      new_msr = msr | MSR_EE;
     286      _CPU_MSR_SET(new_msr);
     287
     288      /* call handler */
     289      bsp_interrupt_handler_dispatch(irq);
     290
     291      /* disable exceptions again */
     292      _CPU_MSR_SET(msr);
     293
     294      /*
     295       * make sure, that the masking operations in
     296       * ICTL and MSR are executed in order
     297       */
     298      asm volatile("sync":::"memory");
     299
     300      /* restore interrupt masks */
     301      m8260.simr_h = old_simr_h;
     302      m8260.simr_l = old_simr_l;
     303
     304    }
     305#ifdef DISPATCH_HANDLER_STAT
     306    ++ loopCounter;
     307#endif
     308  }
     309  return 0;
     310}
     311
     312/*
     313 * Initialize CPM interrupt management
     314 */
     315void
     316BSP_CPM_irq_init(void)
     317{
     318   m8260.simr_l = 0;
     319   m8260.simr_h = 0;
     320   m8260.sipnr_l = 0xffffffff;
     321   m8260.sipnr_h = 0xffffffff;
     322   m8260.sicr = 0;
     323
     324  /*
     325   * Initialize the interrupt priorities.
     326   */
     327   m8260.siprr   = 0x05309770;  /* reset value */
     328   m8260.scprr_h = 0x05309770;  /* reset value */
     329   m8260.scprr_l = 0x05309770;  /* reset value */
     330
     331}
     332
     333rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
     334{
     335  if (is_cpm_irq(irqnum)) {
     336    /*
     337     * Enable interrupt at PIC level
     338     */
     339    BSP_irq_enable_at_cpm (irqnum);
     340  }
     341
     342  return RTEMS_SUCCESSFUL;
     343}
     344
     345rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
     346{
     347  if (is_cpm_irq(irqnum)) {
     348    /*
     349     * disable interrupt at PIC level
     350     */
     351    BSP_irq_disable_at_cpm (irqnum);
     352  }
     353
     354  return RTEMS_SUCCESSFUL;
     355}
     356
     357rtems_status_code bsp_interrupt_facility_initialize()
     358{
     359  /* Install exception handler */
     360  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
     361    return RTEMS_IO_ERROR;
     362  }
     363  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
     364    return RTEMS_IO_ERROR;
     365  }
     366
     367  /* Fill in priority masks */
     368  compute_SIU_IvectMask_from_prio();
     369
     370  /* Initialize the interrupt controller */
     371  BSP_CPM_irq_init();
     372
     373  return RTEMS_SUCCESSFUL;
     374}
     375
     376void bsp_interrupt_handler_default( rtems_vector_number vector)
     377{
     378  printk( "Spurious interrupt: 0x%08x\n", vector);
     379}
  • c/src/lib/libbsp/powerpc/mpc8260ads/make/custom/mpc8260ads.cfg

    rcc1e864d r2d2de4eb  
    1515#
    1616# CPU_CFLAGS = -mcpu=$(8XX_CPU_TYPE) -mstrict-align
    17 CPU_CFLAGS = -mcpu=603e -mstrict-align -Dmpc8260
     17CPU_CFLAGS = -mcpu=603e -mstrict-align -Dmpc8260 \
     18        -meabi -msdata -fno-common
    1819
    1920# optimize flag: typically -O2
  • c/src/lib/libbsp/powerpc/mpc8260ads/preinstall.am

    rcc1e864d r2d2de4eb  
    7070PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    7171
    72 $(PROJECT_INCLUDE)/bsp/vectors.h: vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    73         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    74 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
     72$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     73        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
     74PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
    7575
     76$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     77        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     78PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     79
     80$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     81        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     82PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
     83
  • c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    3636 */
    3737
    38 #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
    39 
    4038#include <bsp.h>
    4139
     
    5553
    5654SPR_RW(SPRG1)
    57 
    58 extern unsigned long intrStackPtr;
    5955
    6056/*
     
    7571void  _BSP_GPLED0_on(void);
    7672void  cpu_init(void);
    77 void  initialize_exceptions(void);
     73
     74extern char IntrStack_start [];
     75extern char intrStack [];
    7876
    7977void BSP_panic(char *s)
     
    151149void bsp_start(void)
    152150{
     151  rtems_status_code sc = RTEMS_SUCCESSFUL;
    153152  extern void *_WorkspaceBase;
    154153  ppc_cpu_id_t myCpu;
    155154  ppc_cpu_revision_t myCpuRevision;
    156   register unsigned char* intrStack;
    157155
    158156  /* Set MPC8260ADS board LEDS and Uart enable lines */
     
    174172  mmu_init();
    175173*/
    176   /*
    177    * Initialize some SPRG registers related to irq handling
    178    */
    179 
    180   intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
    181   _write_SPRG1((unsigned int)intrStack);
    182 
    183 /*
    184   printk( "About to call initialize_exceptions\n" );
    185 */
    186    /*
    187     * Install our own set of exception vectors
    188     */
    189 
    190    initialize_exceptions();
     174
     175  /* Initialize exception handler */
     176  /* FIXME: Interrupt stack begin and size */
     177  sc = ppc_exc_initialize(
     178    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     179    (uintptr_t) IntrStack_start,
     180    (uintptr_t) intrStack - (uintptr_t) IntrStack_start
     181  );
     182  if (sc != RTEMS_SUCCESSFUL) {
     183    BSP_panic("cannot intitialize exceptions");
     184  }
     185
     186  /* Initalize interrupt support */
     187  sc = bsp_interrupt_initialize();
     188  if (sc != RTEMS_SUCCESSFUL) {
     189    BSP_panic("cannot intitialize interrupts");
     190  }
     191
    191192
    192193/*
     
    228229*/
    229230
    230   /*
    231    * Initalize RTEMS IRQ system
    232    */
    233   BSP_rtems_irq_mng_init(0);
    234 
    235231#ifdef SHOW_MORE_INIT_SETTINGS
    236232  printk("Exit from bspstart\n");
  • c/src/lib/libbsp/powerpc/mpc8260ads/startup/linkcmds

    rcc1e864d r2d2de4eb  
    209209    PROVIDE (_FIXUP_END_ = .);
    210210    PROVIDE (__FIXUP_END__ = .);
    211 
    212     PROVIDE (__SDATA2_START__ = .);
    213     .sdata2       : { *(.sdata2) *(.gnu.linkonce.s2.*)  } >ram
    214     .sbss2        : { *(.sbss2) *(.gnu.linkonce.sb2.*)  } >ram
    215     PROVIDE (__SBSS2_END__ = .);
    216 
    217     .sbss2        : { *(.sbss2)         } >ram
    218     PROVIDE (__SBSS2_END__ = .);
    219 
    220     __SBSS_START__ = .;
     211 
     212    .sdata : {
     213      PROVIDE (_SDA_BASE_ = 32768);
     214      *(.sdata .sdata.* .gnu.linkonce.s.*)
     215    } > ram
     216 
     217    .sbss : {
     218      __bss_start = .;
     219 
     220      PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);
     221      *(.scommon)
     222      *(.dynsbss)
     223      *(.sbss .sbss.* .gnu.linkonce.sb.*)
     224      PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);
     225    } > ram
     226 
     227    .sdata2 : {
     228      PROVIDE (_SDA2_BASE_ = 32768);
     229 
     230      *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
     231    } > ram =0
     232 
     233    .sbss2 : {
     234      *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
     235    } > ram =0
     236
    221237    .bss :
    222238    {
    223239      bss.start = .;
    224240      *(.bss .bss* .gnu.linkonce.b*)
    225       *(.sbss*) *(COMMON)
    226241      . = ALIGN(4);
    227242      bss.end = .;
    228243    } > ram
    229     __SBSS_END__ = .;
    230 
    231 
    232 
    233 
    234244
    235245    /* R/W Data */
  • c/src/lib/libbsp/powerpc/mvme3100/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq_init.c: Changed exception header file includes.
     5        * startup/bspstart.c: Update for ppc_exc_initialize() changes.
     6
    172009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    28
  • c/src/lib/libbsp/powerpc/mvme3100/Makefile.am

    rcc1e864d r2d2de4eb  
    9898
    9999include_bsp_HEADERS += \
    100   ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    101   ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
    102100  ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    103101
     
    143141
    144142libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
     143    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    145144    ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
    146145    ../../../libcpu/@RTEMS_CPU@/e500/clock.rel \
     
    148147    ../../../libcpu/@RTEMS_CPU@/e500/mmu.rel \
    149148    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    150     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    151149    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    152150    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel
  • c/src/lib/libbsp/powerpc/mvme3100/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2626#include <bsp/irq.h>
    2727#include <bsp.h>
    28 #include <libcpu/raw_exception.h>
     28#include <bsp/vectors.h>
    2929#include <rtems/bspIo.h>
    3030
  • c/src/lib/libbsp/powerpc/mvme3100/preinstall.am

    rcc1e864d r2d2de4eb  
    9090PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
    9191
    92 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    93         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    94 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    95 
    96 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    97         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    98 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    99 
    10092$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    10193        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
  • c/src/lib/libbsp/powerpc/mvme3100/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    226226void bsp_start( void )
    227227{
     228rtems_status_code   sc;
    228229unsigned char       *stack;
    229 uint32_t            intrStackStart;
    230 uint32_t            intrStackSize;
     230uintptr_t           intrStackStart;
     231uintptr_t           intrStackSize;
    231232char                *chpt;
    232233ppc_cpu_id_t        myCpu;
     
    272273         * Initialize the interrupt related settings.
    273274         */
    274         intrStackStart = (uint32_t) __rtems_end;
     275        intrStackStart = (uintptr_t) __rtems_end;
    275276        intrStackSize = rtems_configuration_get_interrupt_stack_size();
    276277
     
    278279         * Initialize default raw exception handlers.
    279280         */
    280         ppc_exc_initialize(
     281        sc = ppc_exc_initialize(
    281282                PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    282283                intrStackStart,
    283284                intrStackSize
    284285        );
     286        if (sc != RTEMS_SUCCESSFUL) {
     287                BSP_panic("cannot initialize exceptions");
     288        }
    285289
    286290        printk("CPU 0x%x - rev 0x%x\n", myCpu, myCpuRevision);
  • c/src/lib/libbsp/powerpc/mvme5500/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-23      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/BSP_irq.c, irq/irq_init.c, vectors/exceptionhandler.c: Changed
     5        exception header file includes.
     6        * startup/bspstart.c: Update for ppc_exc_initialize() changes.
     7
    182009-10-23      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/mvme5500/Makefile.am

    rcc1e864d r2d2de4eb  
    6666include_bsp_HEADERS += vectors/bspException.h
    6767include_bsp_HEADERS += \
    68         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    69         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \
    70         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
     68        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    7169
    7270# vectors
     
    121119    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    122120    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    123     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    124121    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    125122    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
  • c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c

    rcc1e864d r2d2de4eb  
    3333#include <rtems/score/thread.h>
    3434#include <rtems/score/apiext.h>
    35 #include <libcpu/raw_exception.h>
    3635#include <rtems/rtems/intr.h>
    3736#include <libcpu/io.h>
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    1919#include <bsp/irq.h>
    2020#include <bsp.h>
    21 #include <libcpu/raw_exception.h>  /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */
     21#include <bsp/vectors.h>  /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */
    2222/*#define  TRACE_IRQ_INIT*/
    2323
  • c/src/lib/libbsp/powerpc/mvme5500/preinstall.am

    rcc1e864d r2d2de4eb  
    9090PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bspException.h
    9191
    92 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    93         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    94 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    95 
    9692$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    9793        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
    9894PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    99 
    100 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    101         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    102 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    10395
    10496$(PROJECT_INCLUDE)/bsp/bspMvme5500.h: GT64260/bspMvme5500.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    217217void bsp_start( void )
    218218{
     219  rtems_status_code sc = RTEMS_SUCCESSFUL;
    219220#ifdef CONF_VPD
    220221  int i;
     
    229230  unsigned l3cr;
    230231#endif
    231   uint32_t intrStackStart;
    232   uint32_t intrStackSize;
     232  uintptr_t intrStackStart;
     233  uintptr_t intrStackSize;
    233234  ppc_cpu_id_t myCpu;
    234235  ppc_cpu_revision_t myCpuRevision;
     
    268269   * Initialize the interrupt related settings.
    269270   */
    270   intrStackStart = (uint32_t) __rtems_end;
     271  intrStackStart = (uintptr_t) __rtems_end;
    271272  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    272273
     
    274275   * Initialize default raw exception handlers.
    275276   */
    276   ppc_exc_initialize(
     277  sc = ppc_exc_initialize(
    277278    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    278279    intrStackStart,
    279280    intrStackSize
    280281  );
     282  if (sc != RTEMS_SUCCESSFUL) {
     283    BSP_panic("cannot initialize exceptions");
     284  }
    281285
    282286  /*
  • c/src/lib/libbsp/powerpc/mvme5500/vectors/exceptionhandler.c

    rcc1e864d r2d2de4eb  
    5151#include <bsp.h>
    5252#include <bsp/vectors.h>
    53 #include <libcpu/raw_exception.h>
    5453#include <libcpu/spr.h>
    5554#include <bsp/pci.h>
     
    6059#define SRR1_TEA_EXC    (1<<(31-13))
    6160#define SRR1_MCP_EXC    (1<<(31-12))
    62 
    63 extern void
    64 BSP_printStackTrace(BSP_Exception_frame* excPtr);
    6561
    6662static volatile BSP_ExceptionExtension  BSP_exceptionExtension = 0;
  • c/src/lib/libbsp/powerpc/psim/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq_init.c: Changed exception header file includes.
     5        * startup/bspstart.c: Update for ppc_exc_initialize() changes.
     6
    172009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    28
  • c/src/lib/libbsp/powerpc/psim/Makefile.am

    rcc1e864d r2d2de4eb  
    5858libbsp_a_SOURCES += vectors/align_h.S
    5959
    60 include_bsp_HEADERS += \
    61         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h   \
    62         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h  \
    63         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
     60include_bsp_HEADERS += ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    6461
    6562EXTRA_DIST += shmsupp/README
     
    7572
    7673libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
     74    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    7775    ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
    7876    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    7977    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    80     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    8178    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    8279    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
  • c/src/lib/libbsp/powerpc/psim/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2121#include <bsp.h>
    2222#include <psim.h>
    23 #include <libcpu/raw_exception.h>
     23#include <bsp/vectors.h>
    2424#include <rtems/bspIo.h>
    2525#include <bsp/openpic.h>
  • c/src/lib/libbsp/powerpc/psim/preinstall.am

    rcc1e864d r2d2de4eb  
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
    8383
    84 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    85         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    86 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    87 
    8884$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8985        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
    9086PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    9187
    92 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    93         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    94 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    95 
  • c/src/lib/libbsp/powerpc/psim/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    8080void bsp_start( void )
    8181{
    82   uint32_t intrStackStart;
    83   uint32_t intrStackSize;
     82  rtems_status_code sc = RTEMS_SUCCESSFUL;
     83  uintptr_t intrStackStart;
     84  uintptr_t intrStackSize;
    8485
    8586  /*
     
    104105   * Initialize the interrupt related settings.
    105106   */
    106   intrStackStart = (uint32_t) __rtems_end;
     107  intrStackStart = (uintptr_t) __rtems_end;
    107108  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    108109
     
    110111   * Initialize default raw exception handlers.
    111112   */
    112   ppc_exc_initialize(
     113  sc = ppc_exc_initialize(
    113114    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    114115    intrStackStart,
    115116    intrStackSize
    116117  );
     118  if (sc != RTEMS_SUCCESSFUL) {
     119    BSP_panic("cannot initialize exceptions");
     120  }
    117121
    118122  /*
  • c/src/lib/libbsp/powerpc/qemuppc/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq_init.c: Changed exception header file includes.
     5        * startup/bspstart.c: Changed exception header file includes.  Update
     6        for ppc_exc_initialize() changes.
     7
    182009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/qemuppc/Makefile.am

    rcc1e864d r2d2de4eb  
    5757    $(irq_SOURCES)
    5858
    59 #    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel
    60 include_bsp_HEADERS +=  ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h   \
    61                        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h   \
    62                        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
    63 
    64 
    6559libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    6660    ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
    6761    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    68     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    6962    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    70     ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
    7163    ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
    7264    ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
  • c/src/lib/libbsp/powerpc/qemuppc/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2121
    2222#include <libcpu/powerpc-utility.h>
    23 #include <libcpu/raw_exception.h>
    2423
    2524#include <bsp.h>
    2625#include <bsp/irq.h>
    2726#include <bsp/vectors.h>
    28 #include <bsp/ppc_exc_bspsupp.h>
    2927
    3028int qemuppc_exception_handler( BSP_Exception_frame *frame, unsigned exception_number)
     
    5654        }
    5755
     56        return RTEMS_SUCCESSFUL;
    5857}
    5958
  • c/src/lib/libbsp/powerpc/qemuppc/preinstall.am

    rcc1e864d r2d2de4eb  
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
    8383
    84 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    85         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    86 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    87 
    88 $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    89         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
    90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    91 
    92 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    93         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    94 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    95 
  • c/src/lib/libbsp/powerpc/qemuppc/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    1717#include <string.h>
    1818#include <fcntl.h>
     19
     20#include <libcpu/bat.h>
     21#include <libcpu/spr.h>
     22#include <libcpu/powerpc-utility.h>
     23
    1924#include <bsp.h>
    2025#include <bsp/irq.h>
     26#include <bsp/vectors.h>
    2127#include <bsp/bootcard.h>
    22 #include <rtems/bspIo.h>
    23 #include <rtems/powerpc/powerpc.h>
    24 #include <libcpu/powerpc-utility.h>
    25 #include <libcpu/raw_exception.h>
    2628#include <bsp/irq-generic.h>
    27 #include <bsp/ppc_exc_bspsupp.h>
    28 
    29 #include <libcpu/cpuIdent.h>
    30 #include <libcpu/bat.h>
    31 #include <libcpu/spr.h>
    3229
    3330/*
     
    6663void bsp_start( void )
    6764{
    68   uint32_t intrStackStart;
    69   uint32_t intrStackSize;
    70   int rv = 0;
    71   rtems_status_code sc;
     65  rtems_status_code sc = RTEMS_SUCCESSFUL;
     66  uintptr_t intrStackStart;
     67  uintptr_t intrStackSize;
     68
    7269  /*
    7370   * Note we can not get CPU identification dynamically, so
     
    8784   * Initialize the interrupt related settings.
    8885   */
    89   intrStackStart = (uint32_t) bsp_interrupt_stack_start;
    90   intrStackSize =  (uint32_t) bsp_interrupt_stack_size;
     86  intrStackStart = (uintptr_t) bsp_interrupt_stack_start;
     87  intrStackSize =  (uintptr_t) bsp_interrupt_stack_size;
    9188
    9289  BSP_mem_size = (uint32_t )RamSize;
     
    9592   * Initialize default raw exception handlers.
    9693   */
    97   ppc_exc_initialize(
     94  sc = ppc_exc_initialize(
    9895    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    9996    intrStackStart,
    10097    intrStackSize
    10198  );
     99  if (sc != RTEMS_SUCCESSFUL) {
     100    BSP_panic("cannot initialize exceptions");
     101  }
    102102
    103103  /* Install default handler for the decrementer exception */
    104   rv = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);
    105   if (rv < 0) {
    106     BSP_panic( "Cannot install decrementer exception handler!\n");
     104  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);
     105  if (sc != RTEMS_SUCCESSFUL) {
     106    BSP_panic("cannot install decrementer exception handler");
    107107  }
    108108
     
    110110  sc = bsp_interrupt_initialize();
    111111  if (sc != RTEMS_SUCCESSFUL) {
    112     BSP_panic( "Cannot intitialize interrupt support\n");
     112    BSP_panic("cannot intitialize interrupts");
    113113  }
    114114
  • c/src/lib/libbsp/powerpc/score603e/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq.c, irq/irq_init.c, irq/no_pic.c: Changed exception header
     5        file includes.  Fixes for type changes.
     6        * startup/bspstart.c: Changed exception header file includes.  Update
     7        for ppc_exc_initialize() changes.
     8
    192009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    210
  • c/src/lib/libbsp/powerpc/score603e/Makefile.am

    rcc1e864d r2d2de4eb  
    4747
    4848include_bsp_HEADERS += irq/irq.h \
    49         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
    50         ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    5149        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    5250
     
    7169
    7270libbsp_a_LIBADD = \
     71    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    7372    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    7473    ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     
    7776    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    7877    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
    79     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    8078     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
    8179    ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
  • c/src/lib/libbsp/powerpc/score603e/irq/irq.c

    rcc1e864d r2d2de4eb  
    1717#include <bsp/VME.h>
    1818#include <rtems/score/apiext.h>  /* for post ISR signal processing */
    19 #include <libcpu/raw_exception.h>
    2019#include <libcpu/io.h>
    2120#include <bsp/vectors.h>
  • c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2525#include <bsp/irq.h>
    2626#include <bsp.h>
    27 #include <libcpu/raw_exception.h>
     27#include <bsp/vectors.h>
    2828#include <rtems/bspIo.h>
    2929
  • c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c

    rcc1e864d r2d2de4eb  
    1717#include <bsp/irq.h>
    1818#include <bsp/irq_supp.h>
    19 #include <libcpu/raw_exception.h>
     19#include <bsp/vectors.h>
    2020
    2121static rtems_irq_connect_data *rtems_hdl_tbl;
     
    2626 */
    2727int C_dispatch_irq_handler(
    28   struct _BSP_Exception_frame *frame,
     28  BSP_Exception_frame *frame,
    2929  unsigned int excNum
    3030)
  • c/src/lib/libbsp/powerpc/score603e/preinstall.am

    rcc1e864d r2d2de4eb  
    9494PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    9595
    96 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    97         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    98 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    99 
    100 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    101         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    102 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    103 
    10496$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    10597        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
  • c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    158158void bsp_start( void )
    159159{
     160  rtems_status_code sc = RTEMS_SUCCESSFUL;
    160161  unsigned char        *work_space_start;
    161162  unsigned int         msr_value = 0x0000;
    162   uint32_t             intrStackStart;
    163   uint32_t             intrStackSize;
     163  uintptr_t            intrStackStart;
     164  uintptr_t            intrStackSize;
    164165  volatile uint32_t    *ptr;
    165166  ppc_cpu_id_t         myCpu;
     
    191192   * Initialize the interrupt related settings.
    192193   */
    193   intrStackStart = (uint32_t) __rtems_end;
     194  intrStackStart = (uintptr_t) __rtems_end;
    194195  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    195196  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
     
    204205   * Initialize default raw exception handlers.
    205206   */
    206   ppc_exc_initialize(
     207  sc = ppc_exc_initialize(
    207208    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    208209    intrStackStart,
    209210    intrStackSize
    210211  );
     212  if (sc != RTEMS_SUCCESSFUL) {
     213    BSP_panic("cannot initialize exceptions");
     214  }
    211215
    212216  msr_value = 0x2030;
  • c/src/lib/libbsp/powerpc/shared/clock/clock.c

    rcc1e864d r2d2de4eb  
    2424
    2525#include <libcpu/powerpc-utility.h>
    26 #include <libcpu/raw_exception.h>
    27 
    28 #include <bsp/ppc_exc_bspsupp.h>
     26#include <bsp/vectors.h>
    2927
    3028#define RTEMS_STATUS_CHECKS_USE_PRINTK
  • c/src/lib/libbsp/powerpc/shared/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2727#include <bsp/irq_supp.h>
    2828#include <bsp.h>
    29 #include <libcpu/raw_exception.h>
    3029#include <bsp/motorola.h>
    3130#include <rtems/bspIo.h>
  • c/src/lib/libbsp/powerpc/shared/irq/openpic_i8259_irq.c

    rcc1e864d r2d2de4eb  
    2222#endif
    2323#include <bsp/openpic.h>
    24 #include <libcpu/raw_exception.h>
    2524#include <libcpu/io.h>
    2625#include <bsp/vectors.h>
  • c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    141141void bsp_start( void )
    142142{
     143  rtems_status_code sc = RTEMS_SUCCESSFUL;
    143144#if !defined(mvme2100)
    144145  unsigned l2cr;
    145146#endif
    146   uint32_t intrStackStart;
    147   uint32_t intrStackSize;
     147  uintptr_t intrStackStart;
     148  uintptr_t intrStackSize;
    148149  ppc_cpu_id_t myCpu;
    149150  ppc_cpu_revision_t myCpuRevision;
     
    211212   * Initialize the interrupt related settings.
    212213   */
    213   intrStackStart = (uint32_t) __rtems_end;
     214  intrStackStart = (uintptr_t) __rtems_end;
    214215  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    215216
     
    217218   * Initialize default raw exception handlers.
    218219   */
    219   ppc_exc_initialize(
     220  sc = ppc_exc_initialize(
    220221    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    221222    intrStackStart,
    222223    intrStackSize
    223224  );
     225  if (sc != RTEMS_SUCCESSFUL) {
     226    BSP_panic("cannot initialize exceptions");
     227  }
    224228
    225229  select_console(CONSOLE_LOG);
  • c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq.c: Changed exception header file includes.
     5        * startup/bspstart.c: Changed exception header file includes.  Update
     6        for ppc_exc_initialize() changes.
     7
    182009-10-21  Thomas Doerfler  <Thomas.Doerfler@imd-systems.de>
    29
  • c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am

    rcc1e864d r2d2de4eb  
    2323include_bsp_HEADERS = include/tqm.h include/8xx_immap.h \
    2424    include/irq.h include/irq-config.h \
    25     ../../shared/include/irq-generic.h\
    26     spi/spi.h\
    27     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    28     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
     25    ../../shared/include/irq-generic.h \
     26    spi/spi.h
    2927
    3028EXTRA_DIST = times-tqm866
     
    7977    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    8078    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    81     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    8279    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    8380    ../../../libcpu/@RTEMS_CPU@/mpc8xx/console-generic.rel \
  • c/src/lib/libbsp/powerpc/tqm8xx/irq/irq.c

    rcc1e864d r2d2de4eb  
    2727
    2828#include <libcpu/powerpc-utility.h>
    29 #include <libcpu/raw_exception.h>
     29#include <bsp/vectors.h>
    3030
    3131#include <bsp.h>
    3232#include <bsp/irq.h>
    33 #include <bsp/vectors.h>
    34 #include <bsp/ppc_exc_bspsupp.h>
    3533#include <bsp/irq-generic.h>
    3634/*
  • c/src/lib/libbsp/powerpc/tqm8xx/preinstall.am

    rcc1e864d r2d2de4eb  
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/spi.h
    8383
    84 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    85         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    86 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    87 
    88 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    89         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    91 
    9284$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    9385        $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
  • c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    2121 */
    2222
     23#include <stdlib.h>
     24
    2325#include <rtems.h>
    24 #include <stdlib.h>
     26
    2527#include <libcpu/powerpc-utility.h>
    2628
    2729#include <bsp.h>
     30#include <bsp/vectors.h>
    2831#include <bsp/bootcard.h>
    2932#include <bsp/irq-generic.h>
    30 #include <bsp/ppc_exc_bspsupp.h>
    3133
    3234#ifdef BSP_HAS_TQMMON
     
    125127void bsp_start( void)
    126128{
     129  rtems_status_code sc = RTEMS_SUCCESSFUL;
    127130  ppc_cpu_id_t myCpu;
    128131  ppc_cpu_revision_t myCpuRevision;
    129132
    130   uint32_t interrupt_stack_start = (uint32_t) bsp_interrupt_stack_start;
    131   uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size;
     133  uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
     134  uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;
    132135
    133136  /*
     
    178181
    179182  /* Initialize exception handler */
    180   ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    181                      interrupt_stack_start,
    182                      interrupt_stack_size
    183                      );
     183  sc = ppc_exc_initialize(
     184    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     185    interrupt_stack_start,
     186    interrupt_stack_size
     187  );
     188  if (sc != RTEMS_SUCCESSFUL) {
     189    BSP_panic("cannot initialize exceptions");
     190  }
    184191
    185192  /* Initalize interrupt support */
    186   if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    187     BSP_panic("Cannot intitialize interrupt support\n");
     193  sc = bsp_interrupt_initialize();
     194  if (sc != RTEMS_SUCCESSFUL) {
     195    BSP_panic("cannot intitialize interrupts");
    188196  }
    189197
  • c/src/lib/libbsp/powerpc/virtex/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * Makefile.am, preinstall.am: Update for exception support changes.
     4        * irq/irq.c: Changed exception header file includes.
     5        * startup/bspstart.c: Changed exception header file includes.  Update
     6        for ppc_exc_initialize() changes.
     7
    182009-10-21      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
  • c/src/lib/libbsp/powerpc/virtex/Makefile.am

    rcc1e864d r2d2de4eb  
    5454libbsp_a_SOURCES += irq/irq_init.c
    5555
    56 include_bsp_HEADERS +=  \
    57   ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    58   ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
    59 
    6056if HAS_NETWORKING
    6157network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
     
    6965libbsp_a_LIBADD = \
    7066    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    71     ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    7267    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     68    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
    7369    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
    7470    ../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
  • c/src/lib/libbsp/powerpc/virtex/irq/irq_init.c

    rcc1e864d r2d2de4eb  
    2323#include <bsp/irq.h>
    2424#include <bsp.h>
    25 #include <libcpu/raw_exception.h>
    2625#include <rtems/bspIo.h>
    2726#include <rtems/powerpc/powerpc.h>
  • c/src/lib/libbsp/powerpc/virtex/preinstall.am

    rcc1e864d r2d2de4eb  
    8383PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    8484
    85 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    86         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    87 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    88 
    89 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    90         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    91 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    92 
  • c/src/lib/libbsp/powerpc/virtex/startup/bspstart.c

    rcc1e864d r2d2de4eb  
    105105void bsp_start( void )
    106106{
     107  rtems_status_code sc = RTEMS_SUCCESSFUL;
    107108  extern unsigned char IntrStack_start[];
    108109  extern unsigned char IntrStack_end[];
     
    136137   * Initialize default raw exception handlers.
    137138   */
    138   ppc_exc_initialize(
    139         PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    140         (uint32_t)IntrStack_start,
    141         IntrStack_end - IntrStack_start
     139  sc = ppc_exc_initialize(
     140    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     141    (uint32_t)IntrStack_start,
     142    IntrStack_end - IntrStack_start
    142143  );
     144  if (sc != RTEMS_SUCCESSFUL) {
     145    BSP_panic("cannot initialize exceptions");
     146  }
    143147
    144148  /*
  • c/src/lib/libcpu/powerpc/ChangeLog

    rcc1e864d r2d2de4eb  
     12009-10-22      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * new-exceptions/bspsupport/ppc-code-copy.c,
     4        new-exceptions/bspsupport/ppc_exc_address.c,
     5        new-exceptions/bspsupport/ppc_exc_categories.c,
     6        new-exceptions/bspsupport/ppc_exc_global_handler.c,
     7        new-exceptions/bspsupport/ppc_exc_initialize.c,
     8        new-exceptions/bspsupport/ppc_exc_naked.S,
     9        new-exceptions/bspsupport/ppc_exc_prologue.c: New files.
     10        * new-exceptions/bspsupport/irq.c,
     11        new-exceptions/bspsupport/irq_supp.h,
     12        new-exceptions/bspsupport/ppc_exc_asm_macros.h: Changed exception
     13        header file includes.  Fixes for type changes.
     14        * new-exceptions/bspsupport/vectors.h: Reformatted.  Documentation.
     15        Removed parts that belong to the raw exception API.  Added
     16        declarations from files "new-exceptions/raw_exception.h" and
     17        "bspsupport/ppc_exc_bspsupp.h".
     18        * new-exceptions/bspsupport/ppc_exc_hdl.c: Reformatted.  Removed parts
     19        that belong to the raw exception API.
     20        * new-exceptions/bspsupport/ppc_exc_bspsupp.h: Added prologue template.
     21        * new-exceptions/bspsupport/ppc_exc.S: Fixed
     22        ppc_exc_tgpr_clr_prolog_size.
     23        * shared/include/powerpc-utility.h: Reformatted.  Include more files
     24        for ASM.
     25        * shared/include/cpuIdent.h: Added ppc_cpu_current() and ppc_cpu_is().
     26
    1272009-10-22      Ralf Corsépius <ralf.corsepius@rtems.org>
    228
  • c/src/lib/libcpu/powerpc/Makefile.am

    rcc1e864d r2d2de4eb  
    1515
    1616include_libcpu_HEADERS = shared/include/powerpc-utility.h
     17
     18include_bspdir = $(includedir)/bsp
     19
     20include_bsp_HEADERS =
    1721
    1822EXTRA_DIST =
     
    2630
    2731if !mpc5xx
    28 include_libcpu_HEADERS += new-exceptions/raw_exception.h
    29 noinst_PROGRAMS += new-exceptions/raw_exception.rel
    30 new_exceptions_raw_exception_rel_SOURCES = new-exceptions/raw_exception.c \
    31     new-exceptions/asm_utils.S \
    32         new-exceptions/e500_raw_exc_init.c
    33 new_exceptions_raw_exception_rel_CPPFLAGS = $(AM_CPPFLAGS)
    34 new_exceptions_raw_exception_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     32include_bsp_HEADERS += new-exceptions/bspsupport/vectors.h
    3533
    3634noinst_PROGRAMS += new-exceptions/exc_bspsupport.rel
    3735new_exceptions_exc_bspsupport_rel_SOURCES = \
     36    new-exceptions/bspsupport/ppc-code-copy.c \
    3837    new-exceptions/bspsupport/ppc_exc.S \
     38    new-exceptions/bspsupport/ppc_exc_naked.S \
    3939    new-exceptions/bspsupport/ppc_exc_hdl.c \
    40     new-exceptions/bspsupport/vectors_init.c
     40    new-exceptions/bspsupport/ppc_exc_initialize.c \
     41    new-exceptions/bspsupport/ppc_exc_global_handler.c \
     42    new-exceptions/bspsupport/ppc_exc_categories.c \
     43    new-exceptions/bspsupport/ppc_exc_address.c \
     44    new-exceptions/bspsupport/ppc_exc_prologue.c
     45
    4146new_exceptions_exc_bspsupport_rel_CPPFLAGS = $(AM_CPPFLAGS)
    4247new_exceptions_exc_bspsupport_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     
    5156EXTRA_DIST += new-exceptions/bspsupport/vectors.h
    5257EXTRA_DIST += new-exceptions/bspsupport/irq_supp.h
    53 EXTRA_DIST += new-exceptions/bspsupport/ppc_exc_bspsupp.h
    5458EXTRA_DIST += new-exceptions/bspsupport/README
    5559EXTRA_DIST += new-exceptions/bspsupport/nest_irq_test.c
     
    358362
    359363# Includes
    360 include_bspdir = $(includedir)/bsp
    361 
    362 include_bsp_HEADERS = new-exceptions/bspsupport/vectors.h \
    363         new-exceptions/bspsupport/ppc_exc_bspsupp.h
    364 
    365364include_mpc83xxdir = $(includedir)/mpc83xx
    366365
     
    408407
    409408# Includes
    410 include_bspdir = $(includedir)/bsp
    411 
    412 include_bsp_HEADERS = new-exceptions/bspsupport/vectors.h \
    413         new-exceptions/bspsupport/ppc_exc_bspsupp.h \
    414         mpc55xx/include/irq.h
    415 
    416409include_mpc55xxdir = $(includedir)/mpc55xx
    417410
     
    425418        mpc55xx/include/watchdog.h
    426419
     420include_bsp_HEADERS += mpc55xx/include/irq.h
     421
    427422# IRQ
    428423noinst_PROGRAMS += mpc55xx/irq.rel
  • c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c

    rcc1e864d r2d2de4eb  
    2121#include <mpc55xx/regs.h>
    2222
    23 #include <libcpu/raw_exception.h>
    2423#include <libcpu/powerpc-utility.h>
    2524
    2625#include <bsp/irq.h>
     26#include <bsp/vectors.h>
    2727#include <bsp/irq-generic.h>
    28 #include <bsp/ppc_exc_bspsupp.h>
    2928
    3029#define RTEMS_STATUS_CHECKS_USE_PRINTK
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c

    rcc1e864d r2d2de4eb  
    7070#include <bsp.h>
    7171#include <bsp/vectors.h>
    72 #include <libcpu/raw_exception.h>
    7372#endif
    7473#endif
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c

    rcc1e864d r2d2de4eb  
    1717#include "irq_supp.h"
    1818#include <rtems/score/apiext.h>  /* for post ISR signal processing */
    19 #include <libcpu/raw_exception.h>
    20 #include <libcpu/cpuIdent.h>
    21 #include "vectors.h"
    22 #include "ppc_exc_bspsupp.h"
     19#include <bsp/vectors.h>
    2320#include <stdlib.h>
    2421#include <rtems/bspIo.h> /* for printk */
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h

    rcc1e864d r2d2de4eb  
    2525
    2626#include <rtems.h>
    27 #include <stdint.h>
    2827#include <rtems/irq.h>
     28
     29#include <bsp/vectors.h>
    2930
    3031#ifdef __cplusplus
     
    5253extern int  BSP_setup_the_pic(rtems_irq_global_settings* config);
    5354
    54 struct _BSP_Exception_frame;
    55 
    5655/* IRQ dispatcher to be defined by the PIC driver; note that it MUST
    5756 * implement shared interrupts.
     
    6564 *******************************************************************
    6665 */
    67 int C_dispatch_irq_handler (struct _BSP_Exception_frame *frame, unsigned int excNum);
     66int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum);
    6867
    6968/*
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc.S

    rcc1e864d r2d2de4eb  
    6565        bla     wrap_auto
    6666
     67        .global ppc_exc_tgpr_clr_prolog_size
     68ppc_exc_tgpr_clr_prolog_size = . - ppc_exc_tgpr_clr_prolog
     69
    6770/**
    6871 * @brief Use vector offsets with 16 byte boundaries.
     
    7679        mflr    VECTOR_REGISTER
    7780        bla     wrap_auto_packed
    78 
    79         .global ppc_exc_tgpr_clr_prolog_size
    80 ppc_exc_tgpr_clr_prolog_size = . - ppc_exc_tgpr_clr_prolog
    8181
    8282/*
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h

    rcc1e864d r2d2de4eb  
    1313 */
    1414
    15 #include <libcpu/powerpc-utility.h>
    16 #include <libcpu/raw_exception.h>
    17 
    18 #include "vectors.h"
     15#include <bsp/vectors.h>
    1916
    2017#define LT(cr) ((cr)*4+0)
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h

    rcc1e864d r2d2de4eb  
    118118extern void ppc_exc_min_prolog_sync_tmpl_e500_mchk(void);
    119119extern void ppc_exc_min_prolog_async_tmpl_e500_mchk(void);
     120extern void ppc_exc_min_prolog_tmpl_naked(void);
    120121
    121122/* Special prologue for handling register shadowing on 603-style CPUs */
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c

    rcc1e864d r2d2de4eb  
    1111 */
    1212
    13 #include        <stdint.h>
    14 #include        <string.h>
     13#include <rtems.h>
     14#include <rtems/score/apiext.h>
    1515
    16 #include        <rtems.h>
    17 #include        <rtems/score/cpu.h>
    18 #include        <libcpu/raw_exception.h>
    19 #include        <libcpu/spr.h>
    20 #include        <rtems/score/apiext.h>
    21 
    22 #include        "vectors.h"
    23 #include        "ppc_exc_bspsupp.h"
    24 
    25 /* offset into min-prolog where vector # is hardcoded */
    26 #define         PPC_EXC_PROLOG_VEC_OFFSET       2
     16#include <bsp/vectors.h>
    2717
    2818/* Provide temp. storage space for a few registers.
     
    4030uint32_t ppc_exc_lock_mchk = 0;
    4131
    42 uint32_t ppc_exc_vector_register_std     = 0;
    43 uint32_t ppc_exc_vector_register_crit    = 0;
    44 uint32_t ppc_exc_vector_register_mchk    = 0;
     32uint32_t ppc_exc_vector_register_std  = 0;
     33uint32_t ppc_exc_vector_register_crit = 0;
     34uint32_t ppc_exc_vector_register_mchk = 0;
    4535
    4636/* MSR bits to enable once critical status info is saved and the stack
     
    5040 * but is overridden from vectors_init.c
    5141 */
    52 uint32_t ppc_exc_msr_bits     = MSR_IR | MSR_DR | MSR_RI;
     42uint32_t ppc_exc_msr_bits = MSR_IR | MSR_DR | MSR_RI;
    5343
    54 int ppc_exc_handler_default( BSP_Exception_frame *f, unsigned int vector)
     44static int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector)
    5545{
    56         return 1;
     46  return -1;
    5747}
    5848
    5949/* Table of C-handlers */
    6050ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1] = {
    61         [0 ... LAST_VALID_EXC] = ppc_exc_handler_default
     51  [0 ... LAST_VALID_EXC] = ppc_exc_handler_default
    6252};
    6353
    64 ppc_exc_handler_t ppc_exc_get_handler( unsigned vector)
     54ppc_exc_handler_t ppc_exc_get_handler(unsigned vector)
    6555{
    66         ppc_exc_handler_t handler = NULL;
    67         if (vector > LAST_VALID_EXC) {
    68                 return 0;
    69         }
    70         if (ppc_exc_handler_table [vector] != ppc_exc_handler_default) {
    71                 handler = ppc_exc_handler_table [vector];
    72         }
    73         return handler;
     56  if (
     57    vector <= LAST_VALID_EXC
     58      && ppc_exc_handler_table [vector] != ppc_exc_handler_default
     59  ) {
     60    return ppc_exc_handler_table [vector];
     61  } else {
     62    return NULL;
     63  }
    7464}
    7565
    76 int ppc_exc_set_handler( unsigned vector, ppc_exc_handler_t handler)
     66rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t handler)
    7767{
    78         if (vector > LAST_VALID_EXC) {
    79                 return -1;
    80         }
    81         if (handler == NULL) {
    82                 ppc_exc_handler_table [vector] = ppc_exc_handler_default;
    83         } else {
    84                 ppc_exc_handler_table [vector] = handler;
    85         }
    86         return 0;
     68  if (vector <= LAST_VALID_EXC) {
     69    if (handler == NULL) {
     70      ppc_exc_handler_table [vector] = ppc_exc_handler_default;
     71    } else {
     72      ppc_exc_handler_table [vector] = handler;
     73    }
     74
     75    return RTEMS_SUCCESSFUL;
     76  } else {
     77    return RTEMS_INVALID_ID;
     78  }
    8779}
    8880
    89 void
    90 ppc_exc_wrapup( BSP_Exception_frame *f)
     81void ppc_exc_wrapup(BSP_Exception_frame *frame)
    9182{
    92         /* dispatch_disable level is decremented from assembly code.  */
    93         if ( _Context_Switch_necessary ) {
    94                 /* FIXME: I believe it should be OK to re-enable
    95                 *        interrupts around the execution of _Thread_Dispatch();
    96                 */
    97                 _Thread_Dispatch();
    98         } else if ( _ISR_Signals_to_thread_executing ) {
    99                 _ISR_Signals_to_thread_executing = 0;
    100                 /*
    101                 * Process pending signals that have not already been
    102                 * processed by _Thread_Dispatch. This happens quite
    103                 * unfrequently : the ISR must have posted an action
    104                 * to the current running thread.
    105                 */
    106                 if ( _Thread_Do_post_task_switch_extension ||
    107                                 _Thread_Executing->do_post_task_switch_extension ) {
    108                         _Thread_Executing->do_post_task_switch_extension = false;
    109                         _API_extensions_Run_postswitch();
    110                 }
    111         }
     83  /* dispatch_disable level is decremented from assembly code.  */
     84  if ( _Context_Switch_necessary ) {
     85    /* FIXME: I believe it should be OK to re-enable
     86    *        interrupts around the execution of _Thread_Dispatch();
     87    */
     88    _Thread_Dispatch();
     89  } else if ( _ISR_Signals_to_thread_executing ) {
     90    _ISR_Signals_to_thread_executing = 0;
     91    /*
     92    * Process pending signals that have not already been
     93    * processed by _Thread_Dispatch. This happens quite
     94    * unfrequently : the ISR must have posted an action
     95    * to the current running thread.
     96    */
     97    if ( _Thread_Do_post_task_switch_extension ||
     98        _Thread_Executing->do_post_task_switch_extension ) {
     99      _Thread_Executing->do_post_task_switch_extension = false;
     100      _API_extensions_Run_postswitch();
     101    }
     102  }
    112103}
    113 
    114 void
    115 ppc_exc_min_prolog_expand(ppc_exc_min_prolog_t buf, ppc_exc_min_prolog_template_t templ, uint16_t vec)
    116 {
    117         memcpy(&buf[0], templ, sizeof(ppc_exc_min_prolog_t));
    118         /* fixup the vector */
    119         buf[PPC_EXC_PROLOG_VEC_OFFSET] = (buf[PPC_EXC_PROLOG_VEC_OFFSET] & 0xffff8000) | (vec & 0x7fff);
    120 }
    121 
    122 #undef TESTING
    123 #ifdef TESTING
    124 
    125 static void noop(const struct __rtems_raw_except_connect_data__*x) {}
    126 
    127 rtems_raw_except_connect_data exc_conn = {
    128         exceptIndex: ASM_SYS_VECTOR,
    129         hdl        : {
    130                                         vector: ASM_SYS_VECTOR,
    131                                         raw_hdl: 0,
    132                                         raw_hdl_size: 0
    133                      },
    134         on         : noop,
    135         off        : noop,
    136         isOn       : 0  /* never used AFAIK */
    137 };
    138 
    139 void
    140 ppc_exc_raise()
    141 {
    142         asm volatile("li 3, 0xffffdead; sc");
    143 }
    144 
    145 
    146 int
    147 exc_conn_do()
    148 {
    149         exc_conn.hdl.raw_hdl      = ppc_exc_min_prolog_auto;
    150         exc_conn.hdl.raw_hdl_size = 16;
    151         return ppc_set_exception(&exc_conn);
    152 }
    153 #endif
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h

    rcc1e864d r2d2de4eb  
     1/**
     2 * @file
     3 *
     4 * @ingroup ppc_exc
     5 * @ingroup ppc_exc_frame
     6 *
     7 * @brief PowerPC Exceptions API.
     8 */
     9
     10/*                                                               
     11 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)       
     12 *                    Canon Centre Recherche France.             
     13 *
     14 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
     15 *                                                               
     16 * Copyright (C) 2009 embedded brains GmbH.                     
     17 *                                                               
     18 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>           
     19 * to support 603, 603e, 604, 604e exceptions                   
     20 *                                                               
     21 * Moved to "libcpu/powerpc/new-exceptions" and consolidated     
     22 * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>       
     23 * to be common for all PPCs with new exceptions.               
     24 *                                                               
     25 * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h".
     26 * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h".
     27 *                                                                   
     28 * The license and distribution terms for this file may be           
     29 * found in found in the file LICENSE in this distribution or at     
     30 * http://www.rtems.com/license/LICENSE.                             
     31 *                                                                   
     32 * $Id$       
     33 */
     34
     35/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */
     36
     37#ifndef LIBCPU_VECTORS_H
     38#define LIBCPU_VECTORS_H
     39
     40#include <libcpu/powerpc-utility.h>
     41
     42/**
     43 * @defgroup ppc_exc PowerPC Exceptions
     44 *
     45 * @brief XXX
     46 *
     47 * @{
     48 */
     49
     50#define ASM_RESET_VECTOR                     0x01
     51#define ASM_MACH_VECTOR                      0x02
     52#define ASM_PROT_VECTOR                      0x03
     53#define ASM_ISI_VECTOR                       0x04
     54#define ASM_EXT_VECTOR                       0x05
     55#define ASM_ALIGN_VECTOR                     0x06
     56#define ASM_PROG_VECTOR                      0x07
     57#define ASM_FLOAT_VECTOR                     0x08
     58#define ASM_DEC_VECTOR                       0x09
     59#define ASM_SYS_VECTOR                       0x0C
     60#define ASM_TRACE_VECTOR                     0x0D
     61
     62#define ASM_BOOKE_CRIT_VECTOR                0x01
     63/* We could use the std. decrementer vector # on bookE, too,
     64 * but the bookE decrementer has slightly different semantics
     65 * so we use a different vector (which happens to be
     66 * the PIT vector on the 405 which is like the booke decrementer)
     67 */
     68#define ASM_BOOKE_DEC_VECTOR                 0x10
     69#define ASM_BOOKE_ITLBMISS_VECTOR            0x11
     70#define ASM_BOOKE_DTLBMISS_VECTOR            0x12
     71#define ASM_BOOKE_FIT_VECTOR                 0x13
     72#define ASM_BOOKE_WDOG_VECTOR                0x14
     73
     74#define ASM_PPC405_APU_UNAVAIL_VECTOR        ASM_60X_VEC_ASSIST_VECTOR
     75
     76#define ASM_8XX_FLOATASSIST_VECTOR           0x0E
     77#define ASM_8XX_SOFTEMUL_VECTOR              0x10
     78#define ASM_8XX_ITLBMISS_VECTOR              0x11
     79#define ASM_8XX_DTLBMISS_VECTOR              0x12
     80#define ASM_8XX_ITLBERROR_VECTOR             0x13
     81#define ASM_8XX_DTLBERROR_VECTOR             0x14
     82#define ASM_8XX_DBREAK_VECTOR                0x1C
     83#define ASM_8XX_IBREAK_VECTOR                0x1D
     84#define ASM_8XX_PERIFBREAK_VECTOR            0x1E
     85#define ASM_8XX_DEVPORT_VECTOR               0x1F
     86
     87#define ASM_5XX_FLOATASSIST_VECTOR           0x0E
     88#define ASM_5XX_SOFTEMUL_VECTOR              0x10
     89#define ASM_5XX_IPROT_VECTOR                 0x13
     90#define ASM_5XX_DPROT_VECTOR                 0x14
     91#define ASM_5XX_DBREAK_VECTOR                0x1C
     92#define ASM_5XX_IBREAK_VECTOR                0x1D
     93#define ASM_5XX_MEBREAK_VECTOR               0x1E
     94#define ASM_5XX_NMEBREAK_VECTOR              0x1F
     95
     96#define ASM_60X_VEC_VECTOR                   0x0A
     97#define ASM_60X_PERFMON_VECTOR               0x0F
     98#define ASM_60X_IMISS_VECTOR                 0x10
     99#define ASM_60X_DLMISS_VECTOR                0x11
     100#define ASM_60X_DSMISS_VECTOR                0x12
     101#define ASM_60X_ADDR_VECTOR                  0x13
     102#define ASM_60X_SYSMGMT_VECTOR               0x14
     103#define ASM_60X_VEC_ASSIST_VECTOR            0x16
     104#define ASM_60X_ITM_VECTOR                   0x17
     105
     106/* e200 */
     107#define ASM_E200_SPE_UNAVAILABLE_VECTOR      0x15
     108#define ASM_E200_SPE_DATA_VECTOR             0x16
     109#define ASM_E200_SPE_ROUND_VECTOR            0x17
     110
     111/* e300 */
     112#define ASM_E300_CRIT_VECTOR                 0x0A
     113#define ASM_E300_PERFMON_VECTOR              0x0F
     114#define ASM_E300_IMISS_VECTOR                ASM_60X_IMISS_VECTOR  /* Special case: Shadowed GPRs */
     115#define ASM_E300_DLMISS_VECTOR               ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */
     116#define ASM_E300_DSMISS_VECTOR               ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */
     117#define ASM_E300_ADDR_VECTOR                 0x13
     118#define ASM_E300_SYSMGMT_VECTOR              0x14
     119
    1120/*
    2  * vectors.h Exception frame related contant and API.
    3  *
    4  *  This include file describe the data structure and the functions implemented
    5  *  by rtems to handle exceptions.
    6  *
    7  *  CopyRight (C) 1999 valette@crf.canon.fr
    8  *
    9  *  The license and distribution terms for this file may be
    10  *  found in found in the file LICENSE in this distribution or at
    11  *  http://www.rtems.com/license/LICENSE.
    12  *
    13  *  $Id$
    14  */
    15 #ifndef LIBCPU_POWERPC_BSPSUPP_VECTORS_H
    16 #define LIBCPU_POWERPC_BSPSUPP_VECTORS_H
    17 
    18 #include <libcpu/raw_exception.h>
     121 * If you change that number make sure to adjust the wrapper code in ppc_exc.S
     122 * and that ppc_exc_handler_table will be correctly initialized.
     123 */
     124#define LAST_VALID_EXC                       0x1F
     125
     126/* DO NOT USE -- this symbol is DEPRECATED
     127 * (only used by libbsp/shared/vectors/vectors.S
     128 * which should not be used by new BSPs).
     129 */
     130#define ASM_60X_VEC_VECTOR_OFFSET            0xf20
     131
     132#define ASM_PPC405_FIT_VECTOR_OFFSET         0x1010
     133#define ASM_PPC405_WDOG_VECTOR_OFFSET        0x1020
     134#define ASM_PPC405_TRACE_VECTOR_OFFSET       0x2000
     135
     136/** @} */
     137
     138/**
     139 * @defgroup ppc_exc_frame PowerPC Exception Frame
     140 *
     141 * @brief XXX
     142 *
     143 * @{
     144 */
    19145
    20146/*
     
    74200#define EXCEPTION_FRAME_END 176
    75201
     202/** @} */
     203
    76204#ifndef ASM
    77205
    78 #include <stdint.h>
    79 
    80 /* codemove is like memmove, but it also gets the cache line size
    81  * as 4th parameter to synchronize them. If this last parameter is
    82  * zero, it performs more or less like memmove. No copy is performed if
    83  * source and destination addresses are equal. However the caches
    84  * are synchronized. Note that the size is always rounded up to the
    85  * next mutiple of 4.
    86  */
    87 extern void * codemove(void *, const void *, unsigned int, unsigned long);
    88 extern void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
    89 extern int  exception_always_enabled(const rtems_raw_except_connect_data* ptr);
    90 
    91 void ppc_exc_initialize(
     206/**
     207 * @ingroup ppc_exc_frame
     208 *
     209 * @{
     210 */
     211
     212typedef struct {
     213  unsigned EXC_SRR0;
     214  unsigned EXC_SRR1;
     215  unsigned _EXC_number;
     216  unsigned GPR0;
     217  unsigned GPR1;
     218  unsigned GPR2;
     219  unsigned GPR3;
     220  unsigned GPR4;
     221  unsigned GPR5;
     222  unsigned GPR6;
     223  unsigned GPR7;
     224  unsigned GPR8;
     225  unsigned GPR9;
     226  unsigned GPR10;
     227  unsigned GPR11;
     228  unsigned GPR12;
     229  unsigned GPR13;
     230  unsigned GPR14;
     231  unsigned GPR15;
     232  unsigned GPR16;
     233  unsigned GPR17;
     234  unsigned GPR18;
     235  unsigned GPR19;
     236  unsigned GPR20;
     237  unsigned GPR21;
     238  unsigned GPR22;
     239  unsigned GPR23;
     240  unsigned GPR24;
     241  unsigned GPR25;
     242  unsigned GPR26;
     243  unsigned GPR27;
     244  unsigned GPR28;
     245  unsigned GPR29;
     246  unsigned GPR30;
     247  unsigned GPR31;
     248  unsigned EXC_CR;
     249  unsigned EXC_CTR;
     250  unsigned EXC_XER;
     251  unsigned EXC_LR;
     252  unsigned EXC_MSR;
     253  unsigned EXC_DAR;
     254} BSP_Exception_frame;
     255
     256/** @} */
     257
     258/**
     259 * @ingroup ppc_exc
     260 *
     261 * @{
     262 */
     263
     264/**
     265 * @brief Global exception handler type.
     266 */
     267typedef void (*exception_handler_t)(BSP_Exception_frame*);
     268
     269/**
     270 * @brief Global exception handler.
     271 */
     272extern exception_handler_t globalExceptHdl;
     273
     274/**
     275 * @brief Default global exception handler.
     276 */
     277void C_exception_handler(BSP_Exception_frame* excPtr);
     278
     279void BSP_printStackTrace(BSP_Exception_frame *excPtr);
     280
     281/**
     282 * @brief Exception categories.
     283 *
     284 * Exceptions of different categories use different SRR registers to save the
     285 * machine state and do different things in the prologue and epilogue.
     286 *
     287 * For now, the CPU descriptions assume this fits into 8 bits.
     288 */
     289typedef enum {
     290  PPC_EXC_INVALID = 0,
     291  PPC_EXC_ASYNC = 1,
     292  PPC_EXC_CLASSIC = 2,
     293  PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
     294  PPC_EXC_405_CRITICAL = 4,
     295  PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
     296  PPC_EXC_BOOKE_CRITICAL = 6,
     297  PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
     298  PPC_EXC_E500_MACHCHK  = 8,
     299  PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC,
     300  PPC_EXC_NAKED = 10
     301} ppc_exc_category;
     302
     303/**
     304 * @brief Categorie set type.
     305 */
     306typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1];
     307
     308static inline bool ppc_exc_is_valid_category(ppc_exc_category category)
     309{
     310  return (unsigned) category <= (unsigned) PPC_EXC_NAKED;
     311}
     312
     313/**
     314 * @brief Indicates if exception entry table resides in a writable memory.
     315 *
     316 * This variable is initialized to 'TRUE' by default;
     317 * BSPs which have their vectors in ROM should set it
     318 * to FALSE prior to initializing raw exceptions.
     319 *
     320 * I suspect the only candidate is the simulator.
     321 * After all, the value of this variable is used to
     322 * determine where to install the prologue code and
     323 * installing to ROM on anyting that's real ROM
     324 * will fail anyways.
     325 *
     326 * This should probably go away... (T.S. 2007/11/30)
     327 */
     328extern bool bsp_exceptions_in_RAM;
     329
     330/**
     331 * @brief Vector base address for CPUs (for example e200 and e500) with IVPR
     332 * and IVOR registers.
     333 */
     334extern uint32_t ppc_exc_vector_base;
     335
     336/**
     337 * @brief Returns the entry address of the vector @a vector.
     338 */
     339void *ppc_exc_vector_address(unsigned vector);
     340
     341/**
     342 * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if
     343 * there is no category set available for this CPU.
     344 */
     345const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu);
     346
     347/**
     348 * @brief Returns the category set for the current CPU, or @c NULL if there is
     349 * no category set available for this CPU.
     350 */
     351static inline const ppc_exc_categories *ppc_exc_current_categories(void)
     352{
     353  return ppc_exc_categories_for_cpu(ppc_cpu_current());
     354}
     355
     356/**
     357 * @brief Returns the category for the vector @a vector using the category set
     358 * @a categories.
     359 */
     360ppc_exc_category ppc_exc_category_for_vector(
     361  const ppc_exc_categories *categories,
     362  unsigned vector
     363);
     364
     365/**
     366 * @brief Makes a minimal prologue for the vector @a vector with the category
     367 * @a category.
     368 *
     369 * The minimal prologue will be copied to @a prologue.  Not more than @a
     370 * prologue_size bytes will be copied.  Returns the actual minimal prologue
     371 * size in bytes in @a prologue_size.
     372 *
     373 * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made.
     374 * @retval RTEMS_INVALID_ID Invalid vector number.
     375 * @retval RTEMS_INVALID_NUMBER Invalid category.
     376 * @retval RTEMS_INVALID_SIZE Prologue size to small.
     377 */
     378rtems_status_code ppc_exc_make_prologue(
     379  unsigned vector,
     380  ppc_exc_category category,
     381  uint32_t *prologue,
     382  size_t *prologue_size
     383);
     384
     385/**
     386 * @brief Initializes the exception handling.
     387 *
     388 * @retval RTEMS_SUCCESSFUL Successful initialization.
     389 * @retval RTEMS_NOT_IMPLEMENTED No category set available for the current CPU.
     390 * @retval RTEMS_NOT_CONFIGURED Register r13 does not point to the small data
     391 * area anchor required by SVR4/EABI.
     392 * @retval RTEMS_INTERNAL_ERROR Minimal prologue creation failed.
     393 */
     394rtems_status_code ppc_exc_initialize(
    92395  uint32_t interrupt_disable_mask,
    93   uint32_t interrupt_stack_start,
    94   uint32_t interrupt_stack_size
     396  uintptr_t interrupt_stack_begin,
     397  uintptr_t interrupt_stack_size
    95398);
    96399
    97 typedef struct _BSP_Exception_frame {
    98   unsigned      EXC_SRR0;
    99   unsigned      EXC_SRR1;
    100   unsigned      _EXC_number;
    101   unsigned      GPR0;
    102   unsigned      GPR1;
    103   unsigned      GPR2;
    104   unsigned      GPR3;
    105   unsigned      GPR4;
    106   unsigned      GPR5;
    107   unsigned      GPR6;
    108   unsigned      GPR7;
    109   unsigned      GPR8;
    110   unsigned      GPR9;
    111   unsigned      GPR10;
    112   unsigned      GPR11;
    113   unsigned      GPR12;
    114   unsigned      GPR13;
    115   unsigned      GPR14;
    116   unsigned      GPR15;
    117   unsigned      GPR16;
    118   unsigned      GPR17;
    119   unsigned      GPR18;
    120   unsigned      GPR19;
    121   unsigned      GPR20;
    122   unsigned      GPR21;
    123   unsigned      GPR22;
    124   unsigned      GPR23;
    125   unsigned      GPR24;
    126   unsigned      GPR25;
    127   unsigned      GPR26;
    128   unsigned      GPR27;
    129   unsigned      GPR28;
    130   unsigned      GPR29;
    131   unsigned      GPR30;
    132   unsigned      GPR31;
    133   unsigned      EXC_CR;
    134   unsigned      EXC_CTR;
    135   unsigned      EXC_XER;
    136   unsigned      EXC_LR;
    137   unsigned      EXC_MSR;
    138   unsigned      EXC_DAR;
    139 } BSP_Exception_frame;
    140 
    141 typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
    142 extern exception_handler_t globalExceptHdl;
     400/**
     401 * @brief High-level exception handler type.
     402 *
     403 * Exception handlers should return zero if the exception was handled and
     404 * normal execution may resume.
     405 *
     406 * They should return minus one to reject the exception resulting in the
     407 * globalExcHdl() being called.
     408 *
     409 * Other return values are reserved.
     410 */
     411typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector);
     412
     413/**
     414 * @brief Bits for MSR update.
     415 *
     416 * Bits in MSR that are enabled during execution of exception handlers / ISRs
     417 * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should
     418 * be set to 0 during initialization)
     419 *
     420 * By default, the setting of these bits that is in effect when exception
     421 * handling is initialized is used.
     422 */
     423extern uint32_t ppc_exc_msr_bits;
     424
     425/**
     426 * @brief Cache write back check flag.
     427 *
     428 * (See README under CAVEATS). During initialization
     429 * a check is performed to assert that write-back
     430 * caching is enabled for memory accesses. If a BSP
     431 * runs entirely without any caching then it should
     432 * set this variable to zero prior to initializing
     433 * exceptions in order to skip the test.
     434 * NOTE: The code does NOT support mapping memory
     435 *       with cache-attributes other than write-back
     436 *       (unless the entire cache is physically disabled)
     437 */
     438extern uint32_t ppc_exc_cache_wb_check;
     439
     440/**
     441 * @brief Set high-level exception handler.
     442 *
     443 * Hook C exception handlers.
     444 *  - handlers for asynchronous exceptions run on the ISR stack
     445 *    with thread-dispatching disabled.
     446 *  - handlers for synchronous exceptions run on the task stack
     447 *    with thread-dispatching enabled.
     448 *
     449 * If a particular slot is NULL then the traditional 'globalExcHdl' is used.
     450 *
     451 * ppc_exc_set_handler() registers a handler (returning 0 on success,
     452 * -1 if the vector argument is too big).
     453 *
     454 * It is legal to set a NULL handler. This leads to the globalExcHdl
     455 * being called if an exception for 'vector' occurs.
     456 */
     457rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl);
     458
     459/**
     460 * @brief Returns the currently active high-level exception handler.
     461 */
     462ppc_exc_handler_t ppc_exc_get_handler(unsigned vector);
     463
     464/**
     465 * @brief Function for DAR access.
     466 *
     467 * CPU support may store the address of a function here
     468 * that can be used by the default exception handler to
     469 * obtain fault-address info which is helpful. Unfortunately,
     470 * the SPR holding this information is not uniform
     471 * across PPC families so we need assistance from
     472 * CPU support
     473 */
     474extern uint32_t (*ppc_exc_get_DAR)(void);
     475
     476void
     477ppc_exc_wrapup(BSP_Exception_frame *f);
     478
     479/** @} */
     480
    143481/*
    144482 * Compatibility with pc386
     
    147485typedef exception_handler_t cpuExcHandlerType;
    148486
    149 /*
    150  * dummy functions for exception interface
    151  */
    152 void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
    153 int exception_always_enabled(const rtems_raw_except_connect_data* ptr);
    154 
    155487#endif /* ASM */
    156488
    157 #endif /* LIBCPU_POWERPC_BSPSUPP_VECTORS_H */
     489#endif /* LIBCPU_VECTORS_H */
  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c

    rcc1e864d r2d2de4eb  
    5252
    5353#ifdef BSP_PPC403_CLOCK_HOOK_EXCEPTION
    54 #include <libcpu/raw_exception.h>
    5554#include <bsp/vectors.h>
    56 #include <bsp/ppc_exc_bspsupp.h>
    5755#define PPC_HAS_CLASSIC_EXCEPTIONS FALSE
    5856#else
  • c/src/lib/libcpu/powerpc/preinstall.am

    rcc1e864d r2d2de4eb  
    5050PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/powerpc-utility.h
    5151
     52$(PROJECT_INCLUDE)/bsp/$(dirstamp):
     53        @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
     54        @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     55PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     56
    5257if !mpc5xx
    53 $(PROJECT_INCLUDE)/libcpu/raw_exception.h: new-exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    54         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h
    55 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/raw_exception.h
     58$(PROJECT_INCLUDE)/bsp/vectors.h: new-exceptions/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     59        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
     60PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    5661endif
    5762if shared
     
    211216endif
    212217if mpc83xx
    213 $(PROJECT_INCLUDE)/bsp/$(dirstamp):
    214         @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
    215         @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    216 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    217 
    218 $(PROJECT_INCLUDE)/bsp/vectors.h: new-exceptions/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    219         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    220 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    221 
    222 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: new-exceptions/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    223         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    224 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    225 
    226218$(PROJECT_INCLUDE)/mpc83xx/$(dirstamp):
    227219        @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc83xx
     
    250242endif
    251243if mpc55xx
    252 $(PROJECT_INCLUDE)/bsp/$(dirstamp):
    253         @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
    254         @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    255 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    256 
    257 $(PROJECT_INCLUDE)/bsp/vectors.h: new-exceptions/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    258         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    259 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
    260 
    261 $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h: new-exceptions/bspsupport/ppc_exc_bspsupp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    262         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    263 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    264 
    265 $(PROJECT_INCLUDE)/bsp/irq.h: mpc55xx/include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    266         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
    267 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    268 
    269244$(PROJECT_INCLUDE)/mpc55xx/$(dirstamp):
    270245        @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc55xx
     
    303278        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
    304279PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
    305 endif
     280
     281$(PROJECT_INCLUDE)/bsp/irq.h: mpc55xx/include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     282        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     283PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
     284endif
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h

    rcc1e864d r2d2de4eb  
    107107_PPC_FEAT_DECL(has_ivpr_and_ivor)
    108108
     109#undef _PPC_FEAT_DECL
     110
     111static inline ppc_cpu_id_t ppc_cpu_current(void)
     112{
     113        return current_ppc_cpu;
     114}
     115
    109116static inline bool ppc_cpu_is_e300()
    110117{
    111         if (current_ppc_cpu == PPC_UNKNOWN) {
     118        if (ppc_cpu_current() == PPC_UNKNOWN) {
    112119                get_ppc_cpu_type();
    113120        }
    114         return current_ppc_cpu == PPC_e300c1
    115                 || current_ppc_cpu == PPC_e300c2
    116                 || current_ppc_cpu == PPC_e300c3;
     121        return ppc_cpu_current() == PPC_e300c1
     122                || ppc_cpu_current() == PPC_e300c2
     123                || ppc_cpu_current() == PPC_e300c3;
    117124}
    118125
    119 #undef _PPC_FEAT_DECL
     126static inline bool ppc_cpu_is(ppc_cpu_id_t cpu)
     127{
     128        return ppc_cpu_current() == cpu;
     129}
     130
    120131#endif /* ASM */
    121132
  • c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h

    rcc1e864d r2d2de4eb  
    3030#define LIBCPU_POWERPC_UTILITY_H
    3131
     32#ifndef ASM
     33  #include <rtems.h>
     34#endif
     35
     36#include <rtems/score/cpu.h>
    3237#include <rtems/powerpc/registers.h>
     38#include <rtems/powerpc/powerpc.h>
    3339
    3440#ifndef ASM
    35 
    36 #include <stdint.h>
    3741
    3842#include <rtems/bspIo.h>
    3943#include <rtems/system.h>
    40 #include <rtems/score/cpu.h>
    4144
    4245#include <libcpu/cpuIdent.h>
    4346
    44 #define LINKER_SYMBOL( sym) extern char sym []
     47#define LINKER_SYMBOL(sym) extern char sym []
    4548
    4649/**
    4750 * @brief Read one byte from @a src.
    4851 */
    49 static inline uint8_t ppc_read_byte( const volatile void *src)
    50 {
    51         uint8_t value;
    52 
    53         asm volatile (
    54                 "lbz %0, 0(%1)"
    55                 : "=r" (value)
    56                 : "b" (src)
    57         );
    58 
    59         return value;
     52static inline uint8_t ppc_read_byte(const volatile void *src)
     53{
     54  uint8_t value;
     55
     56  asm volatile (
     57    "lbz %0, 0(%1)"
     58    : "=r" (value)
     59    : "b" (src)
     60  );
     61
     62  return value;
    6063}
    6164
     
    6366 * @brief Read one half word from @a src.
    6467 */
    65 static inline uint16_t ppc_read_half_word( const volatile void *src)
    66 {
    67         uint16_t value;
    68 
    69         asm volatile (
    70                 "lhz %0, 0(%1)"
    71                 : "=r" (value)
    72                 : "b" (src)
    73         );
    74 
    75         return value;
     68static inline uint16_t ppc_read_half_word(const volatile void *src)
     69{
     70  uint16_t value;
     71
     72  asm volatile (
     73    "lhz %0, 0(%1)"
     74    : "=r" (value)
     75    : "b" (src)
     76  );
     77
     78  return value;
    7679}
    7780
     
    7982 * @brief Read one word from @a src.
    8083 */
    81 static inline uint32_t ppc_read_word( const volatile void *src)
    82 {
    83         uint32_t value;
    84 
    85         asm volatile (
    86                 "lwz %0, 0(%1)"
    87                 : "=r" (value)
    88                 : "b" (src)
    89         );
    90 
    91         return value;
     84static inline uint32_t ppc_read_word(const volatile void *src)
     85{
     86  uint32_t value;
     87
     88  asm volatile (
     89    "lwz %0, 0(%1)"
     90    : "=r" (value)
     91    : "b" (src)
     92  );
     93
     94  return value;
    9295}
    9396
     
    9598 * @brief Write one byte @a value to @a dest.
    9699 */
    97 static inline void ppc_write_byte( uint8_t value, volatile void *dest)
    98 {
    99         asm volatile (
    100                 "stb %0, 0(%1)"
    101                 :
    102                 : "r" (value), "b" (dest)
    103         );
     100static inline void ppc_write_byte(uint8_t value, volatile void *dest)
     101{
     102  asm volatile (
     103    "stb %0, 0(%1)"
     104    :
     105    : "r" (value), "b" (dest)
     106  );
    104107}
    105108
     
    107110 * @brief Write one half word @a value to @a dest.
    108111 */
    109 static inline void ppc_write_half_word( uint16_t value, volatile void *dest)
    110 {
    111         asm volatile (
    112                 "sth %0, 0(%1)"
    113                 :
    114                 : "r" (value), "b" (dest)
    115         );
     112static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
     113{
     114  asm volatile (
     115    "sth %0, 0(%1)"
     116    :
     117    : "r" (value), "b" (dest)
     118  );
    116119}
    117120
     
    119122 * @brief Write one word @a value to @a dest.
    120123 */
    121 static inline void ppc_write_word( uint32_t value, volatile void *dest)
    122 {
    123         asm volatile (
    124                 "stw %0, 0(%1)" :
    125                 : "r" (value), "b" (dest)
    126         );
    127 }
    128 
    129 
    130 static inline void *ppc_stack_pointer()
    131 {
    132         void *sp;
    133 
    134         asm volatile (
    135                 "mr %0, 1"
    136                 : "=r" (sp)
    137         );
    138 
    139         return sp;
    140 }
    141 
    142 static inline void ppc_set_stack_pointer( void *sp)
    143 {
    144         asm volatile (
    145                 "mr 1, %0"
    146                 :
    147                 : "r" (sp)
    148         );
    149 }
    150 
    151 static inline void *ppc_link_register()
    152 {
    153         void *lr;
    154 
    155         asm volatile (
    156                 "mflr %0"
    157                 : "=r" (lr)
    158         );
    159 
    160         return lr;
    161 }
    162 
    163 static inline void ppc_set_link_register( void *lr)
    164 {
    165         asm volatile (
    166                 "mtlr %0"
    167                 :
    168                 : "r" (lr)
    169         );
    170 }
    171 
    172 static inline uint32_t ppc_machine_state_register()
    173 {
    174         uint32_t msr;
    175 
    176         asm volatile (
    177                 "mfmsr %0"
    178                 : "=r" (msr)
    179         );
    180 
    181         return msr;
    182 }
    183 
    184 static inline void ppc_set_machine_state_register( uint32_t msr)
    185 {
    186         asm volatile (
    187                 "mtmsr %0"
    188                 :
    189                 : "r" (msr)
    190         );
     124static inline void ppc_write_word(uint32_t value, volatile void *dest)
     125{
     126  asm volatile (
     127    "stw %0, 0(%1)" :
     128    : "r" (value), "b" (dest)
     129  );
     130}
     131
     132
     133static inline void *ppc_stack_pointer(void)
     134{
     135  void *sp;
     136
     137  asm volatile (
     138    "mr %0, 1"
     139    : "=r" (sp)
     140  );
     141
     142  return sp;
     143}
     144
     145static inline void ppc_set_stack_pointer(void *sp)
     146{
     147  asm volatile (
     148    "mr 1, %0"
     149    :
     150    : "r" (sp)
     151  );
     152}
     153
     154static inline void *ppc_link_register(void)
     155{
     156  void *lr;
     157
     158  asm volatile (
     159    "mflr %0"
     160    : "=r" (lr)
     161  );
     162
     163  return lr;
     164}
     165
     166static inline void ppc_set_link_register(void *lr)
     167{
     168  asm volatile (
     169    "mtlr %0"
     170    :
     171    : "r" (lr)
     172  );
     173}
     174
     175static inline uint32_t ppc_machine_state_register(void)
     176{
     177  uint32_t msr;
     178
     179  asm volatile (
     180    "mfmsr %0"
     181    : "=r" (msr)
     182  );
     183
     184  return msr;
     185}
     186
     187static inline void ppc_set_machine_state_register(uint32_t msr)
     188{
     189  asm volatile (
     190    "mtmsr %0"
     191    :
     192    : "r" (msr)
     193  );
     194}
     195
     196static inline void ppc_synchronize_data(void)
     197{
     198  RTEMS_COMPILER_MEMORY_BARRIER();
     199
     200  asm volatile ("sync");
     201}
     202
     203static inline void ppc_synchronize_instructions(void)
     204{
     205  RTEMS_COMPILER_MEMORY_BARRIER();
     206
     207  asm volatile ("isync");
    191208}
    192209
     
    197214 * machine state with ppc_external_exceptions_disable() later.
    198215 */
    199 static inline uint32_t ppc_external_exceptions_enable()
    200 {
    201         uint32_t current_msr;
    202         uint32_t new_msr;
    203 
    204         RTEMS_COMPILER_MEMORY_BARRIER();
    205 
    206         asm volatile (
    207                 "mfmsr %0;"
    208                 "ori %1, %0, 0x8000;"
    209                 "mtmsr %1"
    210                 : "=r" (current_msr), "=r" (new_msr)
    211         );
    212 
    213         return current_msr;
     216static inline uint32_t ppc_external_exceptions_enable(void)
     217{
     218  uint32_t current_msr;
     219  uint32_t new_msr;
     220
     221  RTEMS_COMPILER_MEMORY_BARRIER();
     222
     223  asm volatile (
     224    "mfmsr %0;"
     225    "ori %1, %0, 0x8000;"
     226    "mtmsr %1"
     227    : "=r" (current_msr), "=r" (new_msr)
     228  );
     229
     230  return current_msr;
    214231}
    215232
     
    219236 * @see ppc_external_exceptions_enable()
    220237 */
    221 static inline void ppc_external_exceptions_disable( uint32_t msr)
    222 {
    223         ppc_set_machine_state_register( msr);
    224 
    225         RTEMS_COMPILER_MEMORY_BARRIER();
    226 }
    227 
    228 static inline uint32_t ppc_decrementer_register()
    229 {
    230         uint32_t dec;
    231 
    232         PPC_Get_decrementer( dec);
    233 
    234         return dec;
    235 }
    236 
    237 static inline void ppc_set_decrementer_register( uint32_t dec)
    238 {
    239         PPC_Set_decrementer( dec);
     238static inline void ppc_external_exceptions_disable(uint32_t msr)
     239{
     240  ppc_set_machine_state_register(msr);
     241
     242  RTEMS_COMPILER_MEMORY_BARRIER();
     243}
     244
     245static inline uint32_t ppc_decrementer_register(void)
     246{
     247  uint32_t dec;
     248
     249  PPC_Get_decrementer(dec);
     250
     251  return dec;
     252}
     253
     254static inline void ppc_set_decrementer_register(uint32_t dec)
     255{
     256  PPC_Set_decrementer(dec);
    240257}
    241258
     
    243260 * @brief Preprocessor magic for stringification of @a x.
    244261 */
    245 #define PPC_STRINGOF( x) #x
     262#define PPC_STRINGOF(x) #x
    246263
    247264/**
     
    250267 * @note This macro uses a GNU C extension.
    251268 */
    252 #define PPC_SPECIAL_PURPOSE_REGISTER( spr) \
    253         ( { \
    254                 uint32_t val; \
    255                 asm volatile ( \
    256                         "mfspr %0, " PPC_STRINGOF( spr) \
    257                         : "=r" (val) \
    258                 ); \
    259                 val;\
    260         } )
     269#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
     270  ({ \
     271    uint32_t val; \
     272    asm volatile (\
     273      "mfspr %0, " PPC_STRINGOF(spr) \
     274      : "=r" (val) \
     275    ); \
     276    val;\
     277  } )
    261278
    262279/**
     
    264281 * @a val.
    265282 */
    266 #define PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
    267         do { \
    268                 asm volatile ( \
    269                         "mtspr " PPC_STRINGOF( spr) ", %0" \
    270                         : \
    271                         : "r" (val) \
    272                 ); \
    273         } while (0)
     283#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \
     284  do { \
     285    asm volatile (\
     286      "mtspr " PPC_STRINGOF(spr) ", %0" \
     287      : \
     288      : "r" (val) \
     289    ); \
     290  } while (0)
    274291
    275292/**
     
    279296 * Interrupts are disabled throughout this operation.
    280297 */
    281 #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \
    282         do { \
    283                 rtems_interrupt_level level; \
    284                 uint32_t val; \
    285                 uint32_t mybits = bits; \
    286                 rtems_interrupt_disable( level); \
    287                 val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
    288                 val |= mybits; \
    289                 PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
    290                 rtems_interrupt_enable( level); \
    291         } while (0)
     298#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \
     299  do { \
     300    rtems_interrupt_level level; \
     301    uint32_t val; \
     302    uint32_t mybits = bits; \
     303    rtems_interrupt_disable(level); \
     304    val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
     305    val |= mybits; \
     306    PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
     307    rtems_interrupt_enable(level); \
     308  } while (0)
    292309
    293310/**
     
    298315 * Interrupts are disabled throughout this operation.
    299316 */
    300 #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( spr, bits, mask) \
    301         do { \
    302                 rtems_interrupt_level level; \
    303                 uint32_t val; \
    304                 uint32_t mybits = bits; \
    305                 uint32_t mymask = mask; \
    306                 rtems_interrupt_disable( level); \
    307                 val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
    308                 val &= ~mymask; \
    309                 val |= mybits; \
    310                 PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
    311                 rtems_interrupt_enable( level); \
    312         } while (0)
     317#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \
     318  do { \
     319    rtems_interrupt_level level; \
     320    uint32_t val; \
     321    uint32_t mybits = bits; \
     322    uint32_t mymask = mask; \
     323    rtems_interrupt_disable(level); \
     324    val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
     325    val &= ~mymask; \
     326    val |= mybits; \
     327    PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
     328    rtems_interrupt_enable(level); \
     329  } while (0)
    313330
    314331/**
     
    318335 * Interrupts are disabled throughout this operation.
    319336 */
    320 #define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \
    321         do { \
    322                 rtems_interrupt_level level; \
    323                 uint32_t val; \
    324                 uint32_t mybits = bits; \
    325                 rtems_interrupt_disable( level); \
    326                 val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
    327                 val &= ~mybits; \
    328                 PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
    329                 rtems_interrupt_enable( level); \
    330         } while (0)
     337#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \
     338  do { \
     339    rtems_interrupt_level level; \
     340    uint32_t val; \
     341    uint32_t mybits = bits; \
     342    rtems_interrupt_disable(level); \
     343    val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
     344    val &= ~mybits; \
     345    PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
     346    rtems_interrupt_enable(level); \
     347  } while (0)
    331348
    332349/**
     
    337354 * @note This macro uses a GNU C extension.
    338355 */
    339 #define PPC_DEVICE_CONTROL_REGISTER( dcr) \
    340         ( { \
    341                 uint32_t val; \
    342                 asm volatile ( \
    343                         "mfdcr %0, " PPC_STRINGOF( dcr) \
    344                         : "=r" (val) \
    345                 ); \
    346                 val;\
    347         } )
     356#define PPC_DEVICE_CONTROL_REGISTER(dcr) \
     357  ({ \
     358    uint32_t val; \
     359    asm volatile (\
     360      "mfdcr %0, " PPC_STRINGOF(dcr) \
     361      : "=r" (val) \
     362    ); \
     363    val;\
     364  } )
    348365
    349366/**
     
    353370 * The PowerPC 4XX family has Device Control Registers.
    354371 */
    355 #define PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val) \
    356         do { \
    357                 asm volatile ( \
    358                         "mtdcr " PPC_STRINGOF( dcr) ", %0" \
    359                         : \
    360                         : "r" (val) \
    361                 ); \
    362         } while (0)
     372#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \
     373  do { \
     374    asm volatile (\
     375      "mtdcr " PPC_STRINGOF(dcr) ", %0" \
     376      : \
     377      : "r" (val) \
     378    ); \
     379  } while (0)
    363380
    364381/**
     
    368385 * Interrupts are disabled throughout this operation.
    369386 */
    370 #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \
    371         do { \
    372                 rtems_interrupt_level level; \
    373                 uint32_t val; \
    374                 uint32_t mybits = bits; \
    375                 rtems_interrupt_disable( level); \
    376                 val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
    377                 val |= mybits; \
    378                 PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
    379                 rtems_interrupt_enable( level); \
    380         } while (0)
     387#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \
     388  do { \
     389    rtems_interrupt_level level; \
     390    uint32_t val; \
     391    uint32_t mybits = bits; \
     392    rtems_interrupt_disable(level); \
     393    val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
     394    val |= mybits; \
     395    PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
     396    rtems_interrupt_enable(level); \
     397  } while (0)
    381398
    382399/**
     
    387404 * Interrupts are disabled throughout this operation.
    388405 */
    389 #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED( dcr, bits, mask) \
    390         do { \
    391                 rtems_interrupt_level level; \
    392                 uint32_t val; \
    393                 uint32_t mybits = bits; \
    394                 uint32_t mymask = mask; \
    395                 rtems_interrupt_disable( level); \
    396                 val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
    397                 val &= ~mymask; \
    398                 val |= mybits; \
    399                 PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
    400                 rtems_interrupt_enable( level); \
    401         } while (0)
     406#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \
     407  do { \
     408    rtems_interrupt_level level; \
     409    uint32_t val; \
     410    uint32_t mybits = bits; \
     411    uint32_t mymask = mask; \
     412    rtems_interrupt_disable(level); \
     413    val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
     414    val &= ~mymask; \
     415    val |= mybits; \
     416    PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
     417    rtems_interrupt_enable(level); \
     418  } while (0)
    402419
    403420/**
     
    407424 * Interrupts are disabled throughout this operation.
    408425 */
    409 #define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \
    410         do { \
    411                 rtems_interrupt_level level; \
    412                 uint32_t val; \
    413                 uint32_t mybits = bits; \
    414                 rtems_interrupt_disable( level); \
    415                 val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
    416                 val &= ~mybits; \
    417                 PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
    418                 rtems_interrupt_enable( level); \
    419         } while (0)
    420 
    421 static inline uint32_t ppc_time_base()
    422 {
    423         uint32_t val;
    424 
    425         CPU_Get_timebase_low( val);
    426 
    427         return val;
    428 }
    429 
    430 static inline void ppc_set_time_base( uint32_t val)
    431 {
    432         PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWL, val);
    433 }
    434 
    435 static inline uint32_t ppc_time_base_upper()
    436 {
    437         return PPC_SPECIAL_PURPOSE_REGISTER( TBRU);
    438 }
    439 
    440 static inline void ppc_set_time_base_upper( uint32_t val)
    441 {
    442         PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWU, val);
    443 }
    444 
    445 static inline uint64_t ppc_time_base_64()
    446 {
    447         return PPC_Get_timebase_register();
    448 }
    449 
    450 static inline void ppc_set_time_base_64( uint64_t val)
    451 {
    452         PPC_Set_timebase_register( val);
    453 }
     426#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \
     427  do { \
     428    rtems_interrupt_level level; \
     429    uint32_t val; \
     430    uint32_t mybits = bits; \
     431    rtems_interrupt_disable(level); \
     432    val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
     433    val &= ~mybits; \
     434    PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
     435    rtems_interrupt_enable(level); \
     436  } while (0)
     437
     438static inline uint32_t ppc_time_base(void)
     439{
     440  uint32_t val;
     441
     442  CPU_Get_timebase_low(val);
     443
     444  return val;
     445}
     446
     447static inline void ppc_set_time_base(uint32_t val)
     448{
     449  PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val);
     450}
     451
     452static inline uint32_t ppc_time_base_upper(void)
     453{
     454  return PPC_SPECIAL_PURPOSE_REGISTER(TBRU);
     455}
     456
     457static inline void ppc_set_time_base_upper(uint32_t val)
     458{
     459  PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val);
     460}
     461
     462static inline uint64_t ppc_time_base_64(void)
     463{
     464  return PPC_Get_timebase_register();
     465}
     466
     467static inline void ppc_set_time_base_64(uint64_t val)
     468{
     469  PPC_Set_timebase_register(val);
     470}
     471
     472void ppc_code_copy(void *dest, const void *src, size_t n);
    454473
    455474#else /* ASM */
     
    524543.endm
    525544
    526 #define LINKER_SYMBOL( sym) .extern sym
     545#define LINKER_SYMBOL(sym) .extern sym
    527546
    528547#endif /* ASM */
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