Changeset 2bd440e in rtems


Ignore:
Timestamp:
Aug 22, 2013, 12:18:14 PM (6 years ago)
Author:
Ric Claus <claus@…>
Branches:
4.11, master
Children:
842d63ba
Parents:
2f0d5e4
git-author:
Ric Claus <claus@…> (08/22/13 12:18:14)
git-committer:
Sebastian Huber <sebastian.huber@…> (08/26/13 07:53:06)
Message:

bsp/xilinx-zynq: Add cache support

Location:
c/src/lib
Files:
1 added
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am

    r2f0d5e4 r2bd440e  
    124124# Cache
    125125libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    126 libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
    127 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     126libbsp_a_SOURCES += include/cache_.h
     127libbsp_a_CPPFLAGS += -I$(srcdir)/include
    128128
    129129# Start hooks
  • c/src/lib/libcpu/shared/src/cache_manager.c

    r2f0d5e4 r2bd440e  
    2020 *  rtems/c/src/lib/libcpu/CPU/cache_.h
    2121 *
     22 *  The cache implementation header file can define
     23 *  CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
     24 *  if it provides cache maintenance functions which operate on multiple lines.
     25 *  Otherwise a generic loop with single line operations will be used.
     26 *
    2227 *  The functions below are implemented with CPU dependent inline routines
    2328 *  found in the cache.c files for each CPU. In the event that a CPU does
     
    4752{
    4853#if defined(CPU_DATA_CACHE_ALIGNMENT)
     54#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
     55  _CPU_cache_flush_data_range( d_addr, n_bytes );
     56#else
    4957  const void * final_address;
    5058
     
    6674  }
    6775#endif
     76#endif
    6877}
    6978
     
    7988{
    8089#if defined(CPU_DATA_CACHE_ALIGNMENT)
     90#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
     91  _CPU_cache_invalidate_data_range( d_addr, n_bytes );
     92#else
    8193  const void * final_address;
    8294
     
    98110  }
    99111#endif
     112#endif
    100113}
    101114
     
    205218rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
    206219{
    207 #if CPU_INSTRUCTION_CACHE_ALIGNMENT
     220#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
     221#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
     222  _CPU_cache_invalidate_instruction_range( i_addr, n_bytes );
     223#else
    208224  const void * final_address;
    209225
     
    225241  }
    226242#endif
     243#endif
    227244}
    228245
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