Index: bsps/powerpc/mpc8260ads/headers.am
===================================================================
--- bsps/powerpc/mpc8260ads/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/mpc8260ads/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,10 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/bsp/irq.h
Index: bsps/powerpc/mpc8260ads/include/bsp.h
===================================================================
--- bsps/powerpc/mpc8260ads/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/mpc8260ads/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,86 @@
+/*
+ *  This include file contains all board IO definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2014.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC8260ADS_BSP_H
+#define LIBBSP_POWERPC_MPC8260ADS_BSP_H
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <mpc8260.h>
+#include <mpc8260/cpm.h>
+#include <mpc8260/mmu.h>
+#include <mpc8260/console.h>
+#include <bsp/irq.h>
+#include <bsp/vectors.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Board configuration registers
+ */
+
+typedef struct bcsr
+
+{
+    uint32_t          bcsr0; /* Board Control and Status Register */
+    uint32_t          bcsr1;
+    uint32_t          bcsr2;
+    uint32_t          bcsr3;
+
+} BCSR;
+
+/*
+ * Network driver configuration
+ */
+struct rtems_bsdnet_ifconfig;
+extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching);
+#define RTEMS_BSP_NETWORK_DRIVER_NAME	"eth1"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_enet_driver_attach
+
+/* miscellaneous stuff assumed to exist */
+
+/*
+ * We need to decide how much memory will be non-cacheable. This
+ * will mainly be memory that will be used in DMA (network and serial
+ * buffers).
+ */
+/*
+#define NOCACHE_MEM_SIZE 512*1024
+*/
+
+/* functions */
+
+#if 0
+void M8260ExecuteRISC( uint32_t         command );
+void *M8260AllocateBufferDescriptors( int count );
+void *M8260AllocateRiscTimers( int count );
+extern char M8260DefaultWatchdogFeeder;
+#endif
+
+/*
+ * Prototypes for items shared across file boundaries in the BSP
+ */
+extern uint32_t bsp_serial_per_sec;
+void *bsp_idle_thread( uintptr_t ignored );
+void  cpu_init(void);
+int mbx8xx_console_get_configuration(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: bsps/powerpc/mpc8260ads/include/bsp/irq.h
===================================================================
--- bsps/powerpc/mpc8260ads/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/mpc8260ads/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,193 @@
+/* irq.h
+ *
+ *  This include file describe the data structure and the functions implemented
+ *  by rtems to write interrupt handlers.
+ *
+ *  CopyRight (C) 1999 valette@crf.canon.fr
+ *
+ *  This code is heavilly inspired by the public specification of STREAM V2
+ *  that can be found at :
+ *
+ *      <http://www.chorus.com/Documentation/index.html> by following
+ *  the STREAM API Specification Document link.
+ *
+ *  Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>
+ *  Surrey Satellite Technology Limited
+ *    The interrupt handling on the mpc8260 seems quite different from
+ *    the 860 (I don't know the 860 well).  Although some interrupts
+ *    are routed via the CPM irq and some are direct to the SIU they all
+ *    appear logically the same.  Therefore I removed the distinction
+ *    between SIU and CPM interrupts.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_IRQ_H
+#define LIBBSP_POWERPC_IRQ_H
+#include <rtems/irq.h>
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+extern volatile unsigned int ppc_cached_irq_mask;
+*/
+
+/*
+ * Symblolic IRQ names and related definitions.
+ */
+
+  /*
+   * CPM IRQ handlers related definitions
+   * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
+   */
+#define BSP_CPM_IRQ_NUMBER		(64)
+#define BSP_CPM_IRQ_LOWEST_OFFSET	(0)
+#define BSP_CPM_IRQ_MAX_OFFSET		(BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1)
+  /*
+   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
+   * handler might be connected
+   */
+#define BSP_PROCESSOR_IRQ_NUMBER	(1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+  /*
+   * Summary
+   */
+#define BSP_IRQ_NUMBER		 	(BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
+#define BSP_LOWEST_OFFSET		(BSP_CPM_IRQ_LOWEST_OFFSET)
+#define BSP_MAX_OFFSET			(BSP_PROCESSOR_IRQ_MAX_OFFSET)
+
+  /*
+   * Some SIU IRQ symbolic name definition. Please note that
+   * INT IRQ are defined but a single one will be used to
+   * redirect all CPM interrupt.
+   *
+   * On the mpc8260 all this seems to be transparent.  Although the
+   * CPM, PIT and TMCNT interrupt may well be the only interrupts routed
+   * to the SIU at the hardware level all of them appear as CPM interupts
+   * to software apart from the registers for setting priority.
+   *
+   * The MPC8260 User Manual seems shot through with inconsistencies
+   * about this whole area.
+   */
+
+  /*
+   * Some CPM IRQ symbolic name definition
+   */
+#define BSP_CPM_IRQ_ERROR		(BSP_CPM_IRQ_LOWEST_OFFSET + 0)
+#define BSP_CPM_IRQ_I2C			(BSP_CPM_IRQ_LOWEST_OFFSET + 1)
+#define BSP_CPM_IRQ_SPI			(BSP_CPM_IRQ_LOWEST_OFFSET + 2)
+#define BSP_CPM_IRQ_RISC_TIMERS		(BSP_CPM_IRQ_LOWEST_OFFSET + 3)
+#define BSP_CPM_IRQ_SMC1		(BSP_CPM_IRQ_LOWEST_OFFSET + 4)
+#define BSP_CPM_IRQ_SMC2		(BSP_CPM_IRQ_LOWEST_OFFSET + 5)
+#define BSP_CPM_IRQ_IDMA1		(BSP_CPM_IRQ_LOWEST_OFFSET + 6)
+#define BSP_CPM_IRQ_IDMA2		(BSP_CPM_IRQ_LOWEST_OFFSET + 7)
+#define BSP_CPM_IRQ_IDMA3		(BSP_CPM_IRQ_LOWEST_OFFSET + 8)
+#define BSP_CPM_IRQ_IDMA4		(BSP_CPM_IRQ_LOWEST_OFFSET + 9)
+#define BSP_CPM_IRQ_SDMA		(BSP_CPM_IRQ_LOWEST_OFFSET + 10)
+
+#define BSP_CPM_IRQ_TIMER_1		(BSP_CPM_IRQ_LOWEST_OFFSET + 12)
+#define BSP_CPM_IRQ_TIMER_2		(BSP_CPM_IRQ_LOWEST_OFFSET + 13)
+#define BSP_CPM_IRQ_TIMER_3		(BSP_CPM_IRQ_LOWEST_OFFSET + 14)
+#define BSP_CPM_IRQ_TIMER_4		(BSP_CPM_IRQ_LOWEST_OFFSET + 15)
+#define BSP_CPM_IRQ_TMCNT		(BSP_CPM_IRQ_LOWEST_OFFSET + 16)
+#define BSP_CPM_IRQ_PIT			(BSP_CPM_IRQ_LOWEST_OFFSET + 17)
+
+#define BSP_CPM_IRQ_IRQ1		(BSP_CPM_IRQ_LOWEST_OFFSET + 19)
+#define BSP_CPM_IRQ_IRQ2		(BSP_CPM_IRQ_LOWEST_OFFSET + 20)
+#define BSP_CPM_IRQ_IRQ3		(BSP_CPM_IRQ_LOWEST_OFFSET + 21)
+#define BSP_CPM_IRQ_IRQ4		(BSP_CPM_IRQ_LOWEST_OFFSET + 22)
+#define BSP_CPM_IRQ_IRQ5		(BSP_CPM_IRQ_LOWEST_OFFSET + 23)
+#define BSP_CPM_IRQ_IRQ6		(BSP_CPM_IRQ_LOWEST_OFFSET + 24)
+#define BSP_CPM_IRQ_IRQ7		(BSP_CPM_IRQ_LOWEST_OFFSET + 25)
+
+#define BSP_CPM_IRQ_FCC1		(BSP_CPM_IRQ_LOWEST_OFFSET + 32)
+#define BSP_CPM_IRQ_FCC2		(BSP_CPM_IRQ_LOWEST_OFFSET + 33)
+#define BSP_CPM_IRQ_FCC3		(BSP_CPM_IRQ_LOWEST_OFFSET + 34)
+#define BSP_CPM_IRQ_MCC1		(BSP_CPM_IRQ_LOWEST_OFFSET + 36)
+#define BSP_CPM_IRQ_MCC2		(BSP_CPM_IRQ_LOWEST_OFFSET + 37)
+
+#define BSP_CPM_IRQ_SCC1		(BSP_CPM_IRQ_LOWEST_OFFSET + 40)
+#define BSP_CPM_IRQ_SCC2		(BSP_CPM_IRQ_LOWEST_OFFSET + 41)
+#define BSP_CPM_IRQ_SCC3		(BSP_CPM_IRQ_LOWEST_OFFSET + 42)
+#define BSP_CPM_IRQ_SCC4		(BSP_CPM_IRQ_LOWEST_OFFSET + 43)
+
+#define BSP_CPM_IRQ_PC15		(BSP_CPM_IRQ_LOWEST_OFFSET + 48)
+#define BSP_CPM_IRQ_PC14		(BSP_CPM_IRQ_LOWEST_OFFSET + 49)
+#define BSP_CPM_IRQ_PC13		(BSP_CPM_IRQ_LOWEST_OFFSET + 50)
+#define BSP_CPM_IRQ_PC12		(BSP_CPM_IRQ_LOWEST_OFFSET + 51)
+#define BSP_CPM_IRQ_PC11		(BSP_CPM_IRQ_LOWEST_OFFSET + 52)
+#define BSP_CPM_IRQ_PC10		(BSP_CPM_IRQ_LOWEST_OFFSET + 53)
+#define BSP_CPM_IRQ_PC9			(BSP_CPM_IRQ_LOWEST_OFFSET + 54)
+#define BSP_CPM_IRQ_PC8			(BSP_CPM_IRQ_LOWEST_OFFSET + 55)
+#define BSP_CPM_IRQ_PC7			(BSP_CPM_IRQ_LOWEST_OFFSET + 56)
+#define BSP_CPM_IRQ_PC6			(BSP_CPM_IRQ_LOWEST_OFFSET + 57)
+#define BSP_CPM_IRQ_PC5			(BSP_CPM_IRQ_LOWEST_OFFSET + 58)
+#define BSP_CPM_IRQ_PC4			(BSP_CPM_IRQ_LOWEST_OFFSET + 59)
+#define BSP_CPM_IRQ_PC3			(BSP_CPM_IRQ_LOWEST_OFFSET + 60)
+#define BSP_CPM_IRQ_PC2			(BSP_CPM_IRQ_LOWEST_OFFSET + 61)
+#define BSP_CPM_IRQ_PC1			(BSP_CPM_IRQ_LOWEST_OFFSET + 62)
+#define BSP_CPM_IRQ_PC0			(BSP_CPM_IRQ_LOWEST_OFFSET + 63)
+
+    /*
+     * Some Processor exception handled as rtems IRQ symbolic name definition
+     */
+#define BSP_DECREMENTER			(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+#define BSP_PERIODIC_TIMER		(BSP_DECREMENTER)
+
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+#define CPM_INTERRUPT
+
+/*-------------------------------------------------------------------------+
+| Function Prototypes.
++--------------------------------------------------------------------------*/
+/*
+ * ------------------------ PPC CPM Mngt Routines -------
+ */
+
+/*
+ * function to disable a particular irq. After calling
+ * this function, even if the device asserts the interrupt line it will
+ * not be propagated further to the processor
+ */
+int BSP_irq_disable_at_cpm        (const rtems_irq_number irqLine);
+/*
+ * function to enable a particular irq. After calling
+ * this function, if the device asserts the interrupt line it will
+ * be propagated further to the processor
+ */
+int BSP_irq_enable_at_cpm		(const rtems_irq_number irqLine);
+/*
+ * function to acknoledge a particular irq. After calling
+ * this function, if a device asserts an enabled interrupt line it will
+ * be propagated further to the processor. Mainly usefull for people
+ * writting raw handlers as this is automagically done for rtems managed
+ * handlers.
+ */
+int BSP_irq_ack_at_cpm              	(const rtems_irq_number irqLine);
+/*
+ * function to check if a particular irq is enabled. After calling
+ */
+int BSP_irq_enabled_at_cpm     	(const rtems_irq_number irqLine);
+
+extern void BSP_rtems_irq_mng_init(unsigned cpuId);
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Now that we have defined some basics, include the generic support */
+#include <bsp/irq-generic.h>
+
+#endif
+
+#endif
Index: bsps/powerpc/mpc8260ads/include/tm27.h
===================================================================
--- bsps/powerpc/mpc8260ads/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/mpc8260ads/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,46 @@
+/*
+ * @file
+ * @ingroup powerpc_mpc8260ads
+ * @brief Implementations for interrupt mechanisms for Time Test 27
+ */
+
+/*
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <rtems/powerpc/powerpc.h>
+
+/*
+ *  Stuff for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) \
+   do { \
+	static rtems_irq_connect_data scIrqData = { \
+	  PPC_IRQ_SCALL, \
+	  (rtems_irq_hdl) handler, \
+	  NULL, \
+	  NULL, \
+	  NULL  \
+	}; \
+	BSP_install_rtems_irq_handler (&scIrqData); \
+   } while(0)
+
+#define Cause_tm27_intr() __asm__ volatile ("sc")
+
+#define Clear_tm27_intr() /* empty */
+
+#define Lower_tm27_intr() /* empty */
+
+#endif
