Index: bsps/powerpc/gen83xx/include/bsp.h
===================================================================
--- bsps/powerpc/gen83xx/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/gen83xx/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,163 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains board specific definitions                   |
+\*===============================================================*/
+
+
+#ifndef LIBBSP_POWERPC_GEN83XX_BSP_H
+#define LIBBSP_POWERPC_GEN83XX_BSP_H
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#include <bspopts.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp/hwreg_vals.h>
+
+/*
+ * Some symbols defined in the linker command file.
+ */
+
+LINKER_SYMBOL(bsp_ram_start);
+LINKER_SYMBOL(bsp_ram_end);
+LINKER_SYMBOL(bsp_ram_size);
+
+LINKER_SYMBOL(bsp_rom_start);
+LINKER_SYMBOL(bsp_rom_end);
+LINKER_SYMBOL(bsp_rom_size);
+
+LINKER_SYMBOL(bsp_section_text_start);
+LINKER_SYMBOL(bsp_section_text_end);
+LINKER_SYMBOL(bsp_section_text_size);
+
+LINKER_SYMBOL(bsp_section_data_start);
+LINKER_SYMBOL(bsp_section_data_end);
+LINKER_SYMBOL(bsp_section_data_size);
+
+LINKER_SYMBOL(bsp_section_bss_start);
+LINKER_SYMBOL(bsp_section_bss_end);
+LINKER_SYMBOL(bsp_section_bss_size);
+
+LINKER_SYMBOL(bsp_interrupt_stack_start);
+LINKER_SYMBOL(bsp_interrupt_stack_end);
+LINKER_SYMBOL(bsp_interrupt_stack_size);
+
+LINKER_SYMBOL(bsp_work_area_start);
+
+LINKER_SYMBOL(IMMRBAR);
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <bsp/vectors.h>
+#include <bsp/irq.h>
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * indicate, that BSP has no IDE driver
+ */
+#undef RTEMS_BSP_HAS_IDE_DRIVER
+
+/* misc macros */
+#define BSP_ARRAY_CNT(arr) (sizeof(arr)/sizeof(arr[0]))
+
+void *bsp_idle_thread( uintptr_t ignored );
+#define BSP_IDLE_TASK_BODY bsp_idle_thread
+
+/* functions */
+rtems_status_code bsp_register_i2c(void);
+rtems_status_code bsp_register_spi(void);
+
+/*
+ * Network driver configuration
+ */
+struct rtems_bsdnet_ifconfig;
+extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	BSP_tsec_attach
+
+#ifdef MPC83XX_BOARD_MPC8313ERDB
+  #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec2"
+  #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec1"
+#else
+  #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1"
+  #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2"
+#endif
+
+#if defined(MPC83XX_BOARD_MPC8349EAMDS)
+/*
+ * i2c EEPROM device name
+ */
+#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
+#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
+
+/*
+ * SPI Flash device name
+ */
+#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash"
+#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash"
+#endif /* defined(MPC83XX_BOARD_MPC8349EAMDS) */
+
+#if defined(MPC83XX_BOARD_HSC_CM01)
+/*
+ * i2c EEPROM device name
+ */
+#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
+#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
+
+/*
+ * SPI FRAM device name
+ */
+#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram"
+#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram"
+#endif /* defined(MPC83XX_BOARD_HSC_CM01) */
+
+extern unsigned int BSP_bus_frequency;
+
+extern uint32_t bsp_clicks_per_usec;
+
+/*
+ *  Convert decrementer value to tenths of microseconds (used by shared timer
+ *  driver).
+ */
+#define BSP_Convert_decrementer( _value ) \
+  ((int) (((_value) * 10) / bsp_clicks_per_usec))
+
+void mpc83xx_zero_4( void *dest, size_t n);
+
+void cpu_init( void);
+
+void bsp_restart(void *addr);
+
+#if defined(HAS_UBOOT)
+  /* Routine to obtain U-Boot environment variables */
+  const char *bsp_uboot_getenv(
+    const char *name
+  );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#endif /* GEN83xx */
Index: bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h
===================================================================
--- bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,381 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains board specific definitions                   |
+\*===============================================================*/
+
+
+#ifndef __GEN83xx_HWREG_VALS_h
+#define __GEN83xx_HWREG_VALS_h
+
+#include <mpc83xx/mpc83xx.h>
+#include <bsp.h>
+
+#ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0
+  #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND)
+#else
+  #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY)
+#endif
+
+/*
+ * distinguish board characteristics
+ */
+#if defined(MPC83XX_BOARD_MPC8349EAMDS)
+/*
+ * for Freescale MPC8349 EAMDS
+ */
+/*
+ * two DUART channels supported
+ */
+#define GEN83xx_DUART_AVAIL_MASK 0x03
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+/*
+ * clocking infos
+ */
+#define BSP_CLKIN_FRQ 66000000L
+#define RCFG_SYSPLL_MF 4
+#define RCFG_COREPLL_MF 4
+
+/*
+ * Reset configuration words
+ */
+#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |	\
+			  RCWLR_DDRCM_1_1  |	\
+			  RCWLR_SPMF(RCFG_SYSPLL_MF)    |	\
+			  RCWLR_COREPLL(RCFG_COREPLL_MF))
+
+#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
+			  RCWHR_PCI_32       |	\
+			  RCWHR_PCI1ARB_EN   |	\
+			  RCWHR_PCI2ARB_EN   |	\
+			  RCWHR_CORE_EN      |	\
+			  RCWHR_BMS_LOW      |	\
+			  RCWHR_BOOTSEQ_NONE |	\
+			  RCWHR_SW_DIS       |	\
+			  MPC83XX_RCWHR_BOOT_DEVICE | \
+			  RCWHR_TSEC1M_GMII  |	\
+			  RCWHR_TSEC2M_GMII  |	\
+			  RCWHR_ENDIAN_BIG   |	\
+			  RCWHR_LALE_NORM    |	\
+			  RCWHR_LDP_PAR)
+#elif defined(MPC83XX_BOARD_HSC_CM01)
+/*
+ * for JPK HSC_CM01
+ */
+/*
+ * one DUART channel (UART1) supported
+ */
+#define GEN83xx_DUART_AVAIL_MASK 0x01
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+/*
+ * clocking infos
+ */
+#define BSP_CLKIN_FRQ 30000000L
+#define RCFG_SYSPLL_MF 11
+#define RCFG_COREPLL_MF 4
+/*
+ * Reset configuration words
+ */
+#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |	\
+			  RCWLR_DDRCM_1_1  |	\
+			  RCWLR_SPMF(RCFG_SYSPLL_MF)    |	\
+			  RCWLR_COREPLL(RCFG_COREPLL_MF))
+
+#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
+			  RCWHR_PCI_32       |	\
+			  RCWHR_PCI1ARB_DIS  |	\
+			  RCWHR_PCI2ARB_DIS  |	\
+			  RCWHR_CORE_EN      |	\
+			  RCWHR_BMS_LOW      |	\
+			  RCWHR_BOOTSEQ_NONE |	\
+			  RCWHR_SW_DIS       |	\
+			  MPC83XX_RCWHR_BOOT_DEVICE | \
+			  RCWHR_TSEC1M_RGMII |	\
+			  RCWHR_TSEC2M_GMII  |	\
+			  RCWHR_ENDIAN_BIG   |	\
+			  RCWHR_LALE_EARLY   |	\
+			  RCWHR_LDP_SPC)
+
+#elif defined(MPC83XX_BOARD_BR_UID)
+/*
+ * for BR UID
+ */
+/*
+ * one DUART channel (UART1) supported
+ */
+#define GEN83xx_DUART_AVAIL_MASK 0x01
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+/*
+ * clocking infos
+ */
+#define BSP_CLKIN_FRQ 25000000L
+#define RCFG_SYSPLL_MF  5
+#define RCFG_COREPLL_MF 5
+/*
+ * Reset configuration words
+ */
+#define RESET_CONF_WRD_L \
+  (RCWLR_LBIUCM_1_1							\
+   | RCWLR_DDRCM_2_1							\
+   | RCWLR_SPMF(RCFG_SYSPLL_MF)    					\
+   | RCWLR_COREPLL(RCFG_COREPLL_MF)					\
+   | RCWLR_CEVCOD_1_2 							\
+   | RCWLR_CEPMF(8)							\
+   )
+
+#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
+			  RCWHR_PCI_32       |	\
+			  RCWHR_PCI1ARB_DIS  |	\
+			  RCWHR_CORE_EN      |	\
+			  RCWHR_BMS_LOW      |	\
+			  RCWHR_BOOTSEQ_NONE |	\
+			  RCWHR_SW_DIS       |	\
+			  MPC83XX_RCWHR_BOOT_DEVICE |	\
+			  RCWHR_ENDIAN_BIG)
+
+#elif defined( HAS_UBOOT)
+
+/* TODO */
+
+#else
+
+#error "board type not defined"
+
+#endif
+
+#if defined(MPC83XX_BOARD_MPC8349EAMDS)
+/**************************
+ * for Freescale MPC83XX_BOARD_MPC8349EAMDS
+ */
+
+/*
+ * working values for various registers, used in start/start.S
+ */
+
+/*
+ * Local Access Windows
+ * FIXME: decode bit settings
+ */
+#define LBLAWBAR0_VAL  0xFE000000
+#define LBLAWAR0_VAL   0x80000016
+#define LBLAWBAR1_VAL  0xF8000000
+#define LBLAWAR1_VAL   0x8000000E
+#define LBLAWBAR2_VAL  0xF0000000
+#define LBLAWAR2_VAL   0x80000019
+#define DDRLAWBAR0_VAL 0x00000000
+#define DDRLAWAR0_VAL  0x8000001B
+/*
+ * Local Bus (Memory) Controller
+ * FIXME: decode bit settings
+ */
+#define BR0_VAL 0xFE001001
+#define OR0_VAL 0xFF806FF7
+#define BR1_VAL 0xF8000801
+#define OR1_VAL 0xFFFFE8F0
+#define BR2_VAL 0xF0001861
+#define OR2_VAL 0xFC006901
+/*
+ * SDRAM registers
+ * FIXME: decode bit settings
+ */
+#define MRPTR_VAL 0x20000000
+#define LSRT_VAL  0x32000000
+#define LSDMR_VAL 0x4062D733
+#define LCRR_VAL  0x80000004
+
+/*
+ * DDR-SDRAM registers
+ * FIXME: decode bit settings
+ */
+#define CS2_BNDS_VAL                 0x00000007
+#define CS3_BNDS_VAL                 0x0008000F
+#define CS2_CONFIG_VAL               0x80000101
+#define CS3_CONFIG_VAL               0x80000101
+#define TIMING_CFG_1_VAL             0x36333321
+#define TIMING_CFG_2_VAL             0x00000800
+#define DDR_SDRAM_CFG_VAL            0xC2000000
+#define DDR_SDRAM_MODE_VAL           0x00000022
+#define DDR_SDRAM_INTTVL_VAL         0x045B0100
+#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
+
+#elif defined(MPC83XX_BOARD_HSC_CM01)
+/**************************
+ * for JPK HSC_CM01
+ */
+
+/* fpga BCSR register */
+#define FPGA_START 0xF8000000
+#define FPGA_SIZE  0x8000
+#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
+
+/*
+ * working values for various registers, used in start/start.S
+ */
+
+/* fpga config 16 MB size */
+#define FPGA_CONFIG_START       0xF8000000
+#define FPGA_CONFIG_SIZE        0x01000000
+/* fpga register 8 MB size */
+#define FPGA_REGISTER_START     0xF9000000
+#define FPGA_REGISTER_SIZE      0x00800000
+/* fpga fifo 8 MB size */
+#define FPGA_FIFO_START         0xF9800000
+#define FPGA_FIFO_SIZE          0x00800000
+
+#define FPGA_START (FPGA_CONFIG_START)
+// fpga window size 32 MByte
+#define FPGA_SIZE  (0x02000000)
+#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
+
+/*
+ * Local Access Windows
+ * FIXME: decode bit settings
+ */
+
+#define LBLAWBAR0_VAL  bsp_rom_start
+#define LBLAWAR0_VAL   0x80000018
+#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
+#define LBLAWAR1_VAL   0x80000018
+#define DDRLAWBAR0_VAL bsp_ram_start
+#define DDRLAWAR0_VAL  0x8000001B
+/*
+ * Local Bus (Memory) Controller
+ * FIXME: decode bit settings
+ */
+#define BR0_VAL (0xFE000000 | 0x01001)
+#define OR0_VAL 0xFE000E54
+// fpga config access range (UPM_A) (32 kByte)
+#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
+#define OR2_VAL 0xFFFF9100
+
+// fpga register access range (UPM_B) (8 MByte)
+#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
+#define OR3_VAL 0xFF801100
+
+// fpga fifo access range (UPM_C) (8 MByte)
+#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
+#define OR4_VAL 0xFF801100
+
+/*
+ * SDRAM registers
+ */
+#define MRPTR_VAL 0x20000000
+#define LSRT_VAL  0x32000000
+#define LSDMR_VAL 0x4062D733
+#define LCRR_VAL  0x80010004
+
+/*
+ * DDR-SDRAM registers
+ * FIXME: decode bit settings
+ */
+#define DDRCDR_VAL                   0x00000001
+#define CS0_BNDS_VAL                 0x0000000F
+#define CS0_CONFIG_VAL               0x80810102
+#define TIMING_CFG_0_VAL             0x00420802
+#define TIMING_CFG_1_VAL             0x3735A322
+#define TIMING_CFG_2_VAL             0x2F9044C7
+#define DDR_SDRAM_CFG_2_VAL          0x00401000
+#define DDR_SDRAM_MODE_VAL           0x44521632
+#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
+#define DDR_SDRAM_CFG_VAL            0x63000008
+
+#define DDR_ERR_DISABLE_VAL          0x0000008D
+#define DDR_ERR_DISABLE_VAL2         0x00000089
+#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
+#define DDR_SDRAM_INIT_ADDR_VAL      0
+#define DDR_SDRAM_INTERVAL_VAL       0x05080000
+
+#elif defined(MPC83XX_BOARD_BR_UID)
+/**************************
+ * for BR UID
+ */
+
+/*
+ * working values for various registers, used in start/start.S
+ */
+
+/*
+ * Local Access Windows
+ * FIXME: decode bit settings
+ */
+
+#define LBLAWBAR0_VAL  bsp_rom_start
+#define LBLAWAR0_VAL   0x80000018
+#define DDRLAWBAR0_VAL bsp_ram_start
+#define DDRLAWAR0_VAL  0x8000001B
+
+
+/*
+ * clocking for local bus:
+ * ALE active for 1 clock
+ * local bus clock = 1/2 csb clock
+ */
+#define LCRR_VAL  0x80010002
+
+/*
+ * DDR-SDRAM registers
+ * FIXME: decode bit settings
+ */
+#define DDRCDR_VAL                   0x00000001
+#define CS0_BNDS_VAL                 0x0000000F
+#define CS0_CONFIG_VAL               0x80014202
+#define TIMING_CFG_0_VAL             0x00220802
+#define TIMING_CFG_1_VAL             0x26259222
+#define TIMING_CFG_2_VAL             0x111048C7
+#define DDR_SDRAM_CFG_2_VAL          0x00401000
+#define DDR_SDRAM_MODE_VAL           0x200F1632
+#define DDR_SDRAM_MODE_2_VAL         0x40006000
+#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
+#define DDR_SDRAM_CFG_VAL            0x43100008
+
+#define DDR_ERR_DISABLE_VAL          0x0000008D
+#define DDR_ERR_DISABLE_VAL2         0x00000089
+#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
+#define DDR_SDRAM_INIT_ADDR_VAL      0
+#define DDR_SDRAM_INTERVAL_VAL       0x01E8222E
+
+#elif defined( HAS_UBOOT)
+
+/* TODO */
+
+#else
+
+#error "board type not defined"
+
+#endif
+
+/**************************
+ * derived values for all boards
+ */
+/* value of input clock divider (derived from pll mode reg) */
+#if MPC83XX_CHIP_TYPE != 8309
+  #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
+#else
+  /* On the MPC8309 this bit is reserved */
+  #define BSP_SYSPLL_CKID 1
+#endif
+/* value of system pll (derived from pll mode reg) */
+#define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f)
+/* value of system pll (derived from pll mode reg) */
+#define BSP_COREPLL_MF   ((mpc83xx.clk.spmr>>(31-15))&0x7f)
+
+#endif /* __GEN83xx_HWREG_VALS_h */
Index: bsps/powerpc/gen83xx/include/bsp/irq.h
===================================================================
--- bsps/powerpc/gen83xx/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/gen83xx/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,184 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007, 2010                     |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file declares constants of the interrupt controller        |
+\*===============================================================*/
+
+
+#ifndef GEN83xx_IRQ_IRQ_H
+#define GEN83xx_IRQ_IRQ_H
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#include <bspopts.h>
+
+/*
+ * the following definitions specify the indices used
+ * to interface the interrupt handler API
+ */
+
+/*
+ * Peripheral IRQ handlers related definitions
+ */
+#define BSP_IPIC_PER_IRQ_NUMBER	        128
+#define BSP_IPIC_IRQ_LOWEST_OFFSET        0
+#define BSP_IPIC_IRQ_MAX_OFFSET      (BSP_IPIC_IRQ_LOWEST_OFFSET\
+                                         +BSP_IPIC_PER_IRQ_NUMBER-1)
+
+#define BSP_IS_IPIC_IRQ(irqnum)				\
+          (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) &&	\
+	   ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET))
+/*
+ * Processor IRQ handlers related definitions
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER        1
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET	(BSP_IPIC_IRQ_MAX_OFFSET+1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
+                                         +BSP_PROCESSOR_IRQ_NUMBER-1)
+
+#define BSP_IS_PROCESSOR_IRQ(irqnum)				\
+          (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) &&	\
+	   ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
+#define BSP_LOWEST_OFFSET		BSP_IPIC_IRQ_LOWEST_OFFSET
+#define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
+
+#define BSP_IS_VALID_IRQ(irqnum) 	\
+          (BSP_IS_PROCESSOR_IRQ(irqnum)	\
+           || BSP_IS_IPIC_IRQ(irqnum))
+
+#ifndef ASM
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * index table for the module specific handlers, a few entries are only placeholders
+ */
+  typedef enum {
+    BSP_IPIC_IRQ_FIRST     = BSP_IPIC_IRQ_LOWEST_OFFSET,
+    BSP_IPIC_IRQ_ERROR     = BSP_IPIC_IRQ_LOWEST_OFFSET +  0,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_DMA1      = BSP_IPIC_IRQ_LOWEST_OFFSET +  3,
+    BSP_IPIC_IRQ_UART      = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
+    BSP_IPIC_IRQ_FLEXCAN   = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
+#else
+    BSP_IPIC_IRQ_UART1     = BSP_IPIC_IRQ_LOWEST_OFFSET +  9,
+    BSP_IPIC_IRQ_UART2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 10,
+    BSP_IPIC_IRQ_SEC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 11,
+#endif
+    BSP_IPIC_IRQ_I2C1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 14,
+    BSP_IPIC_IRQ_I2C2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 15,
+    BSP_IPIC_IRQ_SPI       = BSP_IPIC_IRQ_LOWEST_OFFSET + 16,
+    BSP_IPIC_IRQ_IRQ1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 17,
+    BSP_IPIC_IRQ_IRQ2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 18,
+    BSP_IPIC_IRQ_IRQ3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 19,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_QUICC_HI  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
+    BSP_IPIC_IRQ_QUICC_LO  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
+#else
+    BSP_IPIC_IRQ_IRQ4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 20,
+    BSP_IPIC_IRQ_IRQ5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 21,
+    BSP_IPIC_IRQ_IRQ6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 22,
+    BSP_IPIC_IRQ_IRQ7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 23,
+    BSP_IPIC_IRQ_TSEC1_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 32,
+    BSP_IPIC_IRQ_TSEC1_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 33,
+    BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34,
+    BSP_IPIC_IRQ_TSEC2_TX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 35,
+    BSP_IPIC_IRQ_TSEC2_RX  = BSP_IPIC_IRQ_LOWEST_OFFSET + 36,
+    BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37,
+#endif
+    BSP_IPIC_IRQ_USB_DR    = BSP_IPIC_IRQ_LOWEST_OFFSET + 38,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_ESDHC     = BSP_IPIC_IRQ_LOWEST_OFFSET + 42,
+#else
+    BSP_IPIC_IRQ_USB_MPH   = BSP_IPIC_IRQ_LOWEST_OFFSET + 39,
+#endif
+    BSP_IPIC_IRQ_IRQ0      = BSP_IPIC_IRQ_LOWEST_OFFSET + 48,
+    BSP_IPIC_IRQ_RTC_SEC   = BSP_IPIC_IRQ_LOWEST_OFFSET + 64,
+    BSP_IPIC_IRQ_PIT       = BSP_IPIC_IRQ_LOWEST_OFFSET + 65,
+    BSP_IPIC_IRQ_PCI1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 66,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_MSIR1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
+#else
+    BSP_IPIC_IRQ_PCI2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 67,
+#endif
+    BSP_IPIC_IRQ_RTC_ALR   = BSP_IPIC_IRQ_LOWEST_OFFSET + 68,
+    BSP_IPIC_IRQ_MU        = BSP_IPIC_IRQ_LOWEST_OFFSET + 69,
+    BSP_IPIC_IRQ_SBA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 70,
+    BSP_IPIC_IRQ_DMA       = BSP_IPIC_IRQ_LOWEST_OFFSET + 71,
+    BSP_IPIC_IRQ_GTM4      = BSP_IPIC_IRQ_LOWEST_OFFSET + 72,
+    BSP_IPIC_IRQ_GTM8      = BSP_IPIC_IRQ_LOWEST_OFFSET + 73,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_QUICC_PORTS = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
+    BSP_IPIC_IRQ_GPIO      = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
+#else
+    BSP_IPIC_IRQ_GPIO1     = BSP_IPIC_IRQ_LOWEST_OFFSET + 74,
+    BSP_IPIC_IRQ_GPIO2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 75,
+#endif
+    BSP_IPIC_IRQ_DDR       = BSP_IPIC_IRQ_LOWEST_OFFSET + 76,
+    BSP_IPIC_IRQ_LBC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 77,
+    BSP_IPIC_IRQ_GTM2      = BSP_IPIC_IRQ_LOWEST_OFFSET + 78,
+    BSP_IPIC_IRQ_GTM6      = BSP_IPIC_IRQ_LOWEST_OFFSET + 79,
+    BSP_IPIC_IRQ_PMC       = BSP_IPIC_IRQ_LOWEST_OFFSET + 80,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_MSIR2     = BSP_IPIC_IRQ_LOWEST_OFFSET + 81,
+    BSP_IPIC_IRQ_MSIR3     = BSP_IPIC_IRQ_LOWEST_OFFSET + 82,
+#else
+    BSP_IPIC_IRQ_GTM3      = BSP_IPIC_IRQ_LOWEST_OFFSET + 84,
+    BSP_IPIC_IRQ_GTM7      = BSP_IPIC_IRQ_LOWEST_OFFSET + 85,
+#endif
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_MSIR4     = BSP_IPIC_IRQ_LOWEST_OFFSET + 86,
+    BSP_IPIC_IRQ_MSIR5     = BSP_IPIC_IRQ_LOWEST_OFFSET + 87,
+    BSP_IPIC_IRQ_MSIR6     = BSP_IPIC_IRQ_LOWEST_OFFSET + 88,
+    BSP_IPIC_IRQ_MSIR7     = BSP_IPIC_IRQ_LOWEST_OFFSET + 89,
+#endif
+    BSP_IPIC_IRQ_GTM1      = BSP_IPIC_IRQ_LOWEST_OFFSET + 90,
+    BSP_IPIC_IRQ_GTM5      = BSP_IPIC_IRQ_LOWEST_OFFSET + 91,
+#if MPC83XX_CHIP_TYPE / 10 == 830
+    BSP_IPIC_IRQ_DMA1_ERR  = BSP_IPIC_IRQ_LOWEST_OFFSET + 94,
+    BSP_IPIC_IRQ_DPTC      = BSP_IPIC_IRQ_LOWEST_OFFSET + 95,
+#endif
+
+    BSP_IPIC_IRQ_LAST     = BSP_IPIC_IRQ_MAX_OFFSET,
+  } rtems_irq_symbolic_name;
+
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask);
+
+#define MPC83XX_IPIC_INTERRUPT_NORMAL 0
+
+#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1
+
+#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2
+
+rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ASM */
+
+#endif /* GEN83XX_IRQ_IRQ_H */
Index: bsps/powerpc/gen83xx/include/bsp/tsec-config.h
===================================================================
--- bsps/powerpc/gen83xx/include/bsp/tsec-config.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/gen83xx/include/bsp/tsec-config.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H
+#define LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define TSEC_COUNT 2
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H */
Index: bsps/powerpc/gen83xx/include/bsp/u-boot-config.h
===================================================================
--- bsps/powerpc/gen83xx/include/bsp/u-boot-config.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/gen83xx/include/bsp/u-boot-config.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H
+#define LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H
+
+#define CONFIG_MPC83xx
+#define CONFIG_HAS_ETH1
+
+#endif /* LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H */
Index: bsps/powerpc/gen83xx/include/tm27.h
===================================================================
--- bsps/powerpc/gen83xx/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/gen83xx/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,62 @@
+/**
+ * @file
+ *
+ * @brief Support file for Timer Test 27.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+  #error "This is an RTEMS internal file you must not include directly."
+#endif /* _RTEMS_TMTEST27 */
+
+#ifndef TMTESTS_TM27_H
+#define TMTESTS_TM27_H
+
+#include <libcpu/powerpc-utility.h>
+#include <bsp/vectors.h>
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+static void (*tm27_interrupt_handler)(rtems_vector_number);
+
+static int tm27_exception_handler( BSP_Exception_frame *frame, unsigned number)
+{
+	(*tm27_interrupt_handler)( 0);
+
+	return 0;
+}
+
+void Install_tm27_vector( void (*handler)(rtems_vector_number))
+{
+  int rv = 0;
+
+  tm27_interrupt_handler = handler;
+
+  rv = ppc_exc_set_handler( ASM_DEC_VECTOR, tm27_exception_handler);
+  if (rv < 0) {
+    printk( "Error installing clock interrupt handler!\n");
+  }
+}
+
+#define Cause_tm27_intr() \
+  ppc_set_decrementer_register( 8)
+
+#define Clear_tm27_intr() \
+  ppc_set_decrementer_register( UINT32_MAX)
+
+#define Lower_tm27_intr() \
+  (void) ppc_external_exceptions_enable()
+
+#endif /* TMTESTS_TM27_H */
