Index: bsps/powerpc/beatnik/headers.am
===================================================================
--- bsps/powerpc/beatnik/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,22 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/VMEConfig.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gt_timer.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gti2creg.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtintrreg.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtpcireg.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtreg.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_em_pub.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_mve_pub.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/irq.h
Index: bsps/powerpc/beatnik/include/bsp.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,297 @@
+/*
+ *  bsp.h  -- contain BSP API definition.
+ */
+
+/*
+ *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
+ *
+ *  Modified for the 'beatnik' BSP by T. Straumann, 2005-2007.
+ */
+
+#ifndef LIBBSP_BEATNIK_BSP_H
+#define LIBBSP_BEATNIK_BSP_H
+
+#ifndef ASM
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/io.h>
+#include <bsp/vectors.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Board type */
+typedef enum {
+  Unknown = 0,
+  MVME5500,
+  MVME6100
+} BSP_BoardType;
+
+BSP_BoardType BSP_getBoardType(void);
+
+/* Discovery Version */
+
+typedef enum {
+  unknown    = 0,
+  GT_64260_A,      /* Revision 0x10 */
+  GT_64260_B,      /* Revision 0x20 */
+  MV_64360,
+} DiscoveryVersion;
+
+/* Determine the type of discovery chip on this board; info
+ * is cached and repeated calls just return the cached value.
+ *
+ * If a non-zero argument is passed, the routine panics
+ * (rtems_panic) if no recognized bridge is found;
+ */
+DiscoveryVersion BSP_getDiscoveryVersion(int assertion);
+
+/*
+ *  confdefs.h overrides for this BSP:
+ *   - Interrupt stack space is not minimum if defined.
+ */
+#define BSP_INTERRUPT_STACK_SIZE          (16 * 1024)
+
+/*
+ *  base address definitions for several devices
+ */
+#define BSP_MV64x60_BASE        (0xf1000000)
+#define BSP_MV64x60_DEV1_BASE   (0xf1100000)
+#define BSP_UART_IOBASE_COM1    ((BSP_MV64x60_DEV1_BASE)+0x20000)
+#define BSP_UART_IOBASE_COM2    ((BSP_MV64x60_DEV1_BASE)+0x21000)
+#define BSP_UART_USE_SHARED_IRQS
+
+#define BSP_NVRAM_BASE_ADDR      (0xf1110000)
+#define BSP_NVRAM_END_ADDR       (0xf1117fff)
+#define BSP_NVRAM_RTC_START      (0xf1117ff8)
+
+#define BSP_NVRAM_BOOTPARMS_START  (0xf1111000)
+#define BSP_NVRAM_BOOTPARMS_END    (0xf1111fff)
+
+
+/* This is only active/used during early init. It defines
+ * the hose0 base for the shared/generic pci code.
+ * Our own BSP specific pci initialization will then
+ * override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize)
+ */
+
+#define PCI_CONFIG_ADDR        (BSP_MV64x60_BASE + 0xcf8)
+#define PCI_CONFIG_DATA        (BSP_MV64x60_BASE + 0xcfc)
+
+/* our wonderful PCI initialization remaps everything to CPU addresses
+ * - before calling BSP_pci_initialize() this is NOT VALID, however
+ * and the deprecated inl()/outl() etc won't work!
+ */
+#define _IO_BASE          0x00000000
+/* wonderful MotLoad has the base address as seen from the
+ * CPU programmed into config space :-)
+ */
+#define PCI_MEM_BASE               0
+#define PCI_MEM_BASE_ADJUSTMENT    0
+#define PCI_DRAM_OFFSET            0
+
+extern void BSP_motload_pci_fixup(void);
+
+/* PCI <-> local address mapping - no sophisticated windows
+ * (i.e., no support for cached regions etc. you read a BAR
+ * from config space and that's 1:1 where the CPU sees it).
+ * Our memory is mapped 1:1 to PCI also.
+ */
+#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a))
+#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a))
+
+#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS  32
+
+#define BSP_CONSOLE_PORT      BSP_UART_COM1
+#define BSP_UART_BAUD_BASE    115200
+
+/* I2C Devices */
+/* Note that the i2c addresses stated in the manual are
+ * left-shifted by one bit.
+ */
+#define BSP_VPD_I2C_ADDR      (0xA8>>1)    /* the VPD EEPROM  */
+#define BSP_USR_I2C_ADDR      (0xAA>>1)    /* the user EEPROM */
+#define BSP_THM_I2C_ADDR      (0x90>>1)    /* the DS1621 temperature sensor & thermostat */
+
+#define BSP_I2C_BUS_DESCRIPTOR    gt64260_i2c_bus_descriptor
+
+#define BSP_I2C_BUS0_NAME             "/dev/i2c0"
+
+#define BSP_I2C_VPD_EEPROM_NAME       "vpd-eeprom"
+#define BSP_I2C_USR_EEPROM_NAME       "usr-eeprom"
+#define BSP_I2C_DS1621_NAME           "ds1621"
+#define BSP_I2C_THM_NAME              BSP_I2C_DS1621_NAME
+#define BSP_I2C_DS1621_RAW_NAME       "ds1621-raw"
+
+#define  BSP_I2C_VPD_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME)
+#define  BSP_I2C_USR_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME)
+#define  BSP_I2C_DS1621_DEV_NAME          (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME)
+#define BSP_I2C_THM_DEV_NAME              BSP_I2C_DS1621_DEV_NAME
+#define  BSP_I2C_DS1621_RAW_DEV_NAME      (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME)
+
+
+/* Initialize the I2C driver and register all devices 
+ * RETURNS 0 on success, -1 on error.
+ *
+ * Access to the VPD and user EEPROMS as well
+ * as the ds1621 temperature sensor is possible
+ * by means of file nodes
+ *
+ *   /dev/i2c0.vpd-eeprom   (read-only)
+ *   /dev/i2c0.usr-eeprom   (read-write)
+ *   /dev/i2c0.ds1621       (read-only; one byte: board-temp in degC)
+ *   /dev/i2c0.ds1621-raw   (read-write; transfer bytes to/from the ds1621)
+ */
+int BSP_i2c_initialize(void);
+
+/* Networking; */
+#if defined(RTEMS_NETWORKING)
+#include <bsp/bsp_bsdnet_attach.h>
+#endif
+
+/* NOT FOR PUBLIC USE BELOW HERE */
+#define BSP_PCI_HOSE0_MEM_BASE    0x80000000  /* must be aligned to size */
+#define BSP_PCI_HOSE0_MEM_SIZE    0x20000000
+
+#define BSP_PCI_HOSE1_MEM_BASE    0xe0000000
+
+#define BSP_DEV_AND_PCI_IO_BASE   0xf0000000
+#define BSP_DEV_AND_PCI_IO_SIZE   0x10000000
+
+/* maintain coherency between CPU and GT64340 Ethernet
+ * (andpossibly other Discovery components).
+ */
+#define BSP_RW_PAGE_ATTRIBUTES  TRIV121_ATTR_M
+
+extern unsigned BSP_pci_hose1_bus_base;
+
+void BSP_pci_initialize(void);
+
+/* Exception Handling */
+
+/* Use a task notepad to attach user exception handler info;
+ * may be changed by application startup code (EPICS uses 11)
+ */
+#define BSP_EXCEPTION_NOTEPAD    14
+  
+#ifndef ASM
+
+#define outport_byte(port,value) outb(value,port)
+#define outport_word(port,value) outw(value,port)
+#define outport_long(port,value) outl(value,port)
+
+#define inport_byte(port,value) (value = inb(port))
+#define inport_word(port,value) (value = inw(port))
+#define inport_long(port,value) (value = inl(port))
+/*
+ * Vital Board data Start using DATA RESIDUAL
+ */
+/*
+ * Total memory using RESIDUAL DATA
+ */
+extern unsigned int BSP_mem_size;
+/*
+ * Start of the heap
+ */
+extern unsigned int BSP_heap_start;
+/*
+ * PCI Bus Frequency
+ */
+extern unsigned int BSP_bus_frequency;
+/*
+ * processor clock frequency
+ */
+extern unsigned int BSP_processor_frequency;
+/*
+ * Time base divisior (how many tick for 1 second).
+ */
+extern unsigned int BSP_time_base_divisor;
+
+extern char BSP_productIdent[20];
+extern char BSP_serialNumber[20];
+
+extern char BSP_enetAddr0[7];
+extern char BSP_enetAddr1[7];
+
+/*
+ * The commandline as passed from the bootloader.
+ */
+extern char *BSP_commandline_string;
+
+
+#define BSP_Convert_decrementer( _value ) \
+  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
+
+extern rtems_configuration_table  BSP_Configuration;
+extern void bsp_reset(void);
+extern int BSP_disconnect_clock_handler (void);
+extern int BSP_connect_clock_handler (void);
+
+/* clear hostbridge errors
+ *
+ * enableMCP: whether to enable MCP checkstop / machine check interrupts
+ *            on the hostbridge and in HID0.
+ *
+ *            NOTE: The 5500 and 6100 boards have NO PHYSICAL CONNECTION
+ *                  to MCP so 'enableMCP' will always fail!
+ *
+ * quiet    : be silent
+ *
+ * RETURNS  : PCI status (hose 0 in byte 0, host 1 in byte 1) and
+ *            VME bridge status (upper 16 bits).
+ *            Zero if no errors were found.
+ */
+extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
+
+/* clear vme bridge errors and return (bridge-dependent) 16-bit status
+ *
+ * quiet    : be silent
+ *
+ * RETURNS  : 0 if there were no errors, non-zero, bridge-dependent
+ *            16-bit error status on error.
+ *
+ */
+extern unsigned short (*_BSP_clear_vmebridge_errors)(int);
+
+/*
+ * Prototypes for debug helpers
+ */
+void discovery_pic_set_debug_irq(int on);
+void discovery_pic_install_debug_irq(void);
+
+/*
+ * Prototypes for methods called only from .S for dependency tracking
+ */
+char *save_boot_params(
+  void *r3,
+  void *r4,
+  void *r5,
+  char *cmdline_start,
+  char *cmdline_end
+);
+void zero_bss(void);
+
+/*
+ * Prototypes for methods in the BSP that cross file boundaries
+ */
+uint32_t probeMemoryEnd(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/VMEConfig.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/VMEConfig.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/VMEConfig.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,114 @@
+#ifndef RTEMS_BSP_VME_CONFIG_H
+#define RTEMS_BSP_VME_CONFIG_H
+
+/* BSP specific address space configuration parameters */
+
+/* 
+ * Authorship
+ * ----------
+ * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
+ *     created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
+ *      Stanford Linear Accelerator Center, Stanford University.
+ * 
+ * Acknowledgement of sponsorship
+ * ------------------------------
+ * The 'beatnik' BSP was produced by
+ *     the Stanford Linear Accelerator Center, Stanford University,
+ *      under Contract DE-AC03-76SFO0515 with the Department of Energy.
+ * 
+ * Government disclaimer of liability
+ * ----------------------------------
+ * Neither the United States nor the United States Department of Energy,
+ * nor any of their employees, makes any warranty, express or implied, or
+ * assumes any legal liability or responsibility for the accuracy,
+ * completeness, or usefulness of any data, apparatus, product, or process
+ * disclosed, or represents that its use would not infringe privately owned
+ * rights.
+ * 
+ * Stanford disclaimer of liability
+ * --------------------------------
+ * Stanford University makes no representations or warranties, express or
+ * implied, nor assumes any liability for the use of this software.
+ * 
+ * Stanford disclaimer of copyright
+ * --------------------------------
+ * Stanford University, owner of the copyright, hereby disclaims its
+ * copyright and all other rights in this software.  Hence, anyone may
+ * freely use it for any purpose without restriction.  
+ * 
+ * Maintenance of notices
+ * ----------------------
+ * In the interest of clarity regarding the origin and status of this
+ * SLAC software, this and all the preceding Stanford University notices
+ * are to remain affixed to any copy or derivative of this software made
+ * or distributed by the recipient and are to be affixed to any copy of
+ * software made or distributed by the recipient that contains a copy or
+ * derivative of this software.
+ * 
+ * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
+ */ 
+
+#define _VME_DRIVER_TSI148
+#define _VME_DRIVER_UNIVERSE
+
+/* 
+ * NOTE: the BSP (startup/bspstart.c) uses
+ * hardcoded window lengths that match this
+ * layout when setting BATs:
+ */
+#define _VME_A32_WIN0_ON_PCI  0x90000000
+/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate
+ * CSR for space.
+ */
+#define _VME_CSR_ON_PCI      0x9e000000
+#define _VME_A24_ON_PCI      0x9f000000
+#define _VME_A16_ON_PCI      0x9fff0000
+
+/* start of the A32 window on the VME bus
+ * TODO: this should perhaps be a configuration option
+ */
+#define _VME_A32_WIN0_ON_VME  0x20000000
+
+/* if _VME_DRAM_OFFSET is defined, the BSP
+ * will map our RAM onto the VME bus, starting
+ * at _VME_DRAM_OFFSET
+ */
+#define _VME_DRAM_OFFSET    0x90000000
+
+extern int BSP_VMEInit(void);
+extern int BSP_VMEIrqMgrInstall(void);
+
+#define BSP_VME_INSTALL_IRQ_MGR(err)  \
+  do { \
+    err = -1; \
+    switch (BSP_getBoardType()) { \
+      case MVME6100: \
+	err = theOps->install_irq_mgr( \
+	      VMETSI148_IRQ_MGR_FLAG_SHARED, \
+	      0, BSP_IRQ_GPP_0 + 20, \
+	      1, BSP_IRQ_GPP_0 + 21, \
+	      2, BSP_IRQ_GPP_0 + 22, \
+	      3, BSP_IRQ_GPP_0 + 23, \
+	      -1); \
+	break; \
+\
+      case MVME5500: \
+	err = theOps->install_irq_mgr( \
+	      VMEUNIVERSE_IRQ_MGR_FLAG_SHARED | \
+	      VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND, \
+	      0, BSP_IRQ_GPP_0 + 12, \
+	      1, BSP_IRQ_GPP_0 + 13, \
+	      2, BSP_IRQ_GPP_0 + 14, \
+	      3, BSP_IRQ_GPP_0 + 15, \
+	      -1); \
+	break; \
+\
+      default: \
+	printk("WARNING: unknown board; "); \
+	break; \
+    } \
+    if ( err ) \
+      printk("VME interrupt manager NOT INSTALLED (error: %i)\n", err); \
+  } while (0)
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,79 @@
+#ifndef BSP_BSDNET_ATTACH_INFO_H
+#define BSP_BSDNET_ATTACH_INFO_H
+
+/* Author: Till Straumann, 2005; see ../../LICENSE */
+
+/* Rationale: traditionally, BSPs only supported a single networking interface
+ *            the BSP defined RTEMS_NETWORK_DRIVER_NAME & friends macros
+ *            for applications to use.
+ *            If more than one interface is present, this simple approach is
+ *            not enough.
+ *            Hence, this BSP exports a routine declaring all available interfaces
+ *            so the application can make a choice.
+ */
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+/* Fwd. decl just in case */
+struct rtems_bsdnet_ifconfig;
+
+typedef struct {
+							/* name of the interface */
+		const char *name;		
+							/* optional description (to be used by chooser 'help' function etc.) */
+		const char *description;
+							/* driver 'attach' function */
+		int			(*attach_fn)(struct rtems_bsdnet_ifconfig*, int);
+} BSP_NetIFDescRec, *BSP_NetIFDesc;
+
+/* Return a pointer to the (static) list of network interface descriptions
+ * of this board.
+ *
+ * NOTES: A NULL value is returned if e.g., the board type cannot be determined
+ *        or for other reasons.
+ *        The 'description' field is optional, i.e., may be NULL.
+ *        The list is terminated by an element with a NULL name field.
+ *        The interfaces are listed in the order they are labelled.
+ */
+
+BSP_NetIFDesc
+BSP_availableNetIFs();
+
+/* Define this macro so applications can conditionally compile this API */
+#define BSP_HAS_MULTIPLE_NETIFS(x)	BSP_availableNetIFs()	
+
+/* Legacy macro; applications should use BSP_Available_NetIfs() to choose
+ * an interface and attach function.
+ */
+extern char BSP_auto_network_driver_name[20];
+#define RTEMS_BSP_NETWORK_DRIVER_NAME	BSP_auto_network_driver_name
+
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	BSP_auto_enet_attach
+
+/* This routine checks the name field passed in the 'ifconfig'.
+ * If the name is NULL or points to the BSP_auto_network_driver_name
+ * array, the routine checks all interfaces for an active link and
+ * attaches the first alive one.
+ * It also updates 'ifconfig' to reflect the chosen interface's name
+ * and attach function.
+ *
+ * If another name is passed in, the routine scans
+ * the available interfaces for that name and uses it, if found.
+ * Eventually, a default interface is chosen (provided that
+ * the board type is successfully detected).
+ *
+ * Note that only ONE interface chained into rtems_bsdnet_config
+ * may use the "auto" name.
+ *
+ */
+
+int
+BSP_auto_enet_attach(struct rtems_bsdnet_ifconfig *ifconfig, int attaching);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,30 @@
+#ifndef BSP_EARLY_ENET_LINK_STATUS_H
+#define BSP_EARLY_ENET_LINK_STATUS_H
+
+/* Determine link status of ethernet device before network is initialized */
+
+/* T. Straumann, 2005; see ../../LICENSE */
+
+#include <rtems.h>
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+typedef struct {
+	int				(*init)(int idx);	/* perform enough initialization to access (default) phy */
+	int 			(*read_phy)(int idx, unsigned reg);
+	int 			(*write_phy)(int idx, unsigned reg, unsigned val);
+	const char 		*name;				/* driver name */
+	unsigned char 	num_slots;			/* max number of supported devices */
+	unsigned char	initialized;		/* must be initialized to 0;       */
+} rtems_bsdnet_early_link_check_ops;
+
+int
+BSP_early_check_link_status(int unit, rtems_bsdnet_early_link_check_ops *ops);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/gt_timer.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/gt_timer.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/gt_timer.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,133 @@
+#ifndef BSP_GT_TIMER_H
+#define BSP_GT_TIMER_H
+
+/* Support for hardware timers in the discovery bridge */
+
+/* 
+ * Authorship
+ * ----------
+ * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
+ *     created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
+ * 	   Stanford Linear Accelerator Center, Stanford University.
+ * 
+ * Acknowledgement of sponsorship
+ * ------------------------------
+ * The 'beatnik' BSP was produced by
+ *     the Stanford Linear Accelerator Center, Stanford University,
+ * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
+ * 
+ * Government disclaimer of liability
+ * ----------------------------------
+ * Neither the United States nor the United States Department of Energy,
+ * nor any of their employees, makes any warranty, express or implied, or
+ * assumes any legal liability or responsibility for the accuracy,
+ * completeness, or usefulness of any data, apparatus, product, or process
+ * disclosed, or represents that its use would not infringe privately owned
+ * rights.
+ * 
+ * Stanford disclaimer of liability
+ * --------------------------------
+ * Stanford University makes no representations or warranties, express or
+ * implied, nor assumes any liability for the use of this software.
+ * 
+ * Stanford disclaimer of copyright
+ * --------------------------------
+ * Stanford University, owner of the copyright, hereby disclaims its
+ * copyright and all other rights in this software.  Hence, anyone may
+ * freely use it for any purpose without restriction.  
+ * 
+ * Maintenance of notices
+ * ----------------------
+ * In the interest of clarity regarding the origin and status of this
+ * SLAC software, this and all the preceding Stanford University notices
+ * are to remain affixed to any copy or derivative of this software made
+ * or distributed by the recipient and are to be affixed to any copy of
+ * software made or distributed by the recipient that contains a copy or
+ * derivative of this software.
+ * 
+ * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
+ */ 
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+/* Obtain the number of hardware timers present
+ * The 'timer' argument in the routines below addresses
+ * one of 0..(BSP_timer_instances()-1)
+ */
+int BSP_timer_instances(void);
+
+/* Setup timer but don't start yet; interrupts are enabled if an isr argument is passed
+ * no interrupts are generated otherwise.
+ *
+ * If 'reload' is nonzero then the period is automatically restarted.
+ *
+ * RETURNS: 0 on success, nonzero on error (argument error)
+ *
+ * NOTE: If an ISR is already connected, it must be removed by passing a NULL isr first.
+ */
+int      BSP_timer_setup(uint32_t timer, void (*isr)(void *arg), void *arg, int reload);
+
+/* Stop timer;
+ *
+ * RETURNS: 0 on success, nonzero on argument error
+ */
+int      BSP_timer_stop(uint32_t timer);
+
+/* Start timer with 'period' (in ticks)
+ *
+ * RETURNS: 0 on success, nonzero on argument error
+ */
+int      BSP_timer_start(uint32_t timer, uint32_t period);
+
+/* read decrementing timer on the fly
+ *
+ * RETURNS: current count in ticks
+ */
+uint32_t BSP_timer_read(uint32_t timer);
+
+/* get clock rate in Hz */
+uint32_t BSP_timer_clock_get(uint32_t timer);
+
+/* Initialize timer facility -- to be used by BSP implementors only
+ *
+ * RETURNS: 0 on success, nonzero if ISR wrapper couldn't be installed
+ */
+int	BSP_timers_initialize(void);
+
+/* WATCHDOG TIMER (resets board if enabled and not 'petted' for
+ * some time).
+ */
+
+/* Enable watchdog and set a timeout (in us)
+ * RETURNS 0 on success
+ */
+int BSP_watchdog_enable(uint32_t timeout_us);
+
+/* Disable watchdog
+ * RETURNS 0 on success
+ */
+int BSP_watchdog_disable(void);
+
+/* Check status -- unfortunately there seems to be no way
+ * to read the running value...
+ *
+ * RETURNS nonzero if enabled/running, zero if disabled/stopped
+ */
+int BSP_watchdog_status(void);
+
+/* Pet the watchdog (rearm to configured timeout)
+ * RETURNS: 0 on success, nonzero on failure (watchdog
+ * currently not running).
+ */
+int BSP_watchdog_pet(void);
+
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,62 @@
+#ifndef GT_64260_BUS_DRIVER_H
+#define GT_64260_BUS_DRIVER_H
+/* 
+ * Authorship
+ * ----------
+ * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
+ *     created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
+ * 	   Stanford Linear Accelerator Center, Stanford University.
+ * 
+ * Acknowledgement of sponsorship
+ * ------------------------------
+ * The 'beatnik' BSP was produced by
+ *     the Stanford Linear Accelerator Center, Stanford University,
+ * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
+ * 
+ * Government disclaimer of liability
+ * ----------------------------------
+ * Neither the United States nor the United States Department of Energy,
+ * nor any of their employees, makes any warranty, express or implied, or
+ * assumes any legal liability or responsibility for the accuracy,
+ * completeness, or usefulness of any data, apparatus, product, or process
+ * disclosed, or represents that its use would not infringe privately owned
+ * rights.
+ * 
+ * Stanford disclaimer of liability
+ * --------------------------------
+ * Stanford University makes no representations or warranties, express or
+ * implied, nor assumes any liability for the use of this software.
+ * 
+ * Stanford disclaimer of copyright
+ * --------------------------------
+ * Stanford University, owner of the copyright, hereby disclaims its
+ * copyright and all other rights in this software.  Hence, anyone may
+ * freely use it for any purpose without restriction.  
+ * 
+ * Maintenance of notices
+ * ----------------------
+ * In the interest of clarity regarding the origin and status of this
+ * SLAC software, this and all the preceding Stanford University notices
+ * are to remain affixed to any copy or derivative of this software made
+ * or distributed by the recipient and are to be affixed to any copy of
+ * software made or distributed by the recipient that contains a copy or
+ * derivative of this software.
+ * 
+ * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
+ */ 
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+#include <rtems.h>
+#include <rtems/libi2c.h>
+
+/* for registration with libi2c */
+extern rtems_libi2c_bus_t *gt64260_i2c_bus_descriptor;
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/gti2creg.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/gti2creg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/gti2creg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,83 @@
+/*	$NetBSD: gti2creg.h,v 1.2 2005/02/27 00:27:21 perry Exp $	*/
+
+/*
+ * Copyright (c) 2005 Brocade Communcations, inc.
+ * All rights reserved.
+ *
+ * Written by Matt Thomas for Brocade Communcations, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of Brocade Communications, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_MARVELL_GTI2CREG_H_
+#define	_DEV_MARVELL_GTI2CREG_H_
+
+#define	I2C_REG_SlaveAddr	0xc000
+#define	I2C_REG_ExtSlaveAddr	0xc010
+#define	I2C_REG_Data		0xc004
+#define	I2C_REG_Control		0xc008
+#define	I2C_REG_Status		0xc00c
+#define	I2C_REG_BaudRate	0xc00c
+#define	I2C_REG_SoftReset	0xc01c
+
+#define	I2C_SlaveAddr_GCE	0x0001	/* Act as Slave */
+#define	I2C_SlaveAddr_SAddr	0x7E
+
+#define	I2C_Control_ACK		0x04
+#define	I2C_Control_IFlg	0x08
+#define	I2C_Control_Stop	0x10
+#define	I2C_Control_Start	0x20
+#define	I2C_Control_TWSIEn	0x40
+#define	I2C_Control_IntEn	0x80
+
+/*
+ * F(I2C) = F(Tclk) / ( 10 * (M + 1) * (2^(N+1)))
+ * For Tclk = 100MHz, M =  4, N = 4: F = 62.5KHz
+ * For Tclk = 100MHz, M = 13, N = 3: F = 96.2KHz
+ */
+#define	I2C_BaudRate(M, N)	(((M) << 3) | (N))
+#define	I2C_BaudRate_62_5K	I2C_BaudRate(4, 4)
+#define	I2C_BaudRate_96_2K	I2C_BaudRate(13, 3)
+
+#define	I2C_Status_BusError	0x00	/* Bus error */
+#define I2C_Status_Started	0x08	/* Start condition xmitted */
+#define	I2C_Status_ReStarted	0x10	/* Repeated start condition xmitted */
+#define	I2C_Status_AddrWriteAck	0x18	/* Adr + wr bit xmtd, ack rcvd */
+#define	I2C_Status_AddrWriteNoAck 0x20	/* Adr + wr bit xmtd, NO ack rcvd */
+#define	I2C_Status_MasterWriteAck 0x28	/* Master xmtd data byte, ack rcvd */
+#define	I2C_Status_MasterWriteNoAck 0x30 /* Master xmtd data byte, NO ack rcvd*/
+#define	I2C_Status_MasterLostArb 0x38	/* Master lost arbitration during
+					   address or data transfer */
+#define	I2C_Status_AddrReadAck	0x40	/* Adr + rd bit xmtd, ack rcvd */
+#define	I2C_Status_AddrReadNoAck 0x48	/* Adr + rd bit xmtd, NO ack rcvd */
+#define	I2C_Status_MasterReadAck 0x50	/* Master rcvd data bye, ack rcvd */
+#define	I2C_Status_MasterReadNoAck 0x58	/* Master rcvd data bye, NO ack rcvd */
+#define	I2C_Status_2ndAddrWriteAck 0xd0	/* 2nd adr + wr bit xmid, ack rcvd */
+#define	I2C_Status_2ndAddrWriteNoAck 0xd8 /* 2nd adr + wr bit xmid, NO ack rcvd */
+#define	I2C_Status_2ndAddrReadAck 0xe0	/* 2nd adr + rd bit xmid, ack rcvd */
+#define	I2C_Status_2ndAddrReadNoAck 0xe8 /* 2nd adr + rd bit xmtd, NO ack rcvd */
+#define	I2C_Status_Idle		0xf8	/* Idle */
+
+#endif /* _DEV_MARVELL_GTI2CREG_H_ */
Index: bsps/powerpc/beatnik/include/bsp/gtintrreg.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/gtintrreg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/gtintrreg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,257 @@
+/*	$NetBSD: gtintrreg.h,v 1.3 2005/02/27 00:27:21 perry Exp $	*/
+
+/*
+ * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Allegro Networks, Inc., and Wasabi Systems, Inc.
+ * 4. The name of Allegro Networks, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ * 5. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
+ * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * gt64260intr.h: defines for GT-64260 system controller interrupts
+ *
+ * creation	Sun Jan  7 18:05:59 PST 2001	cliff
+ *
+ * NOTE:
+ *	Galileo GT-64260 manual bit defines assume Little Endian
+ *	ordering of bits within bytes, i.e.
+ *		bit #0 --> 0x01
+ *	vs. Motorola Big Endian bit numbering where
+ *		bit #0 --> 0x80
+ *	Consequently we define bits in Little Endian format and plan
+ *	to swizzle bytes during programmed I/O by using lwbrx/swbrx
+ *	to load/store GT-64260 registers.
+ */
+
+
+#ifndef _DISCOVERY_GT64260INTR_H
+#define _DISCOVERY_GT64260INTR_H
+
+#define BIT(n)  (1<<(n))
+
+
+/*
+ * GT-64260 Interrupt Controller Register Map
+ */
+#define ICR_260_MIC_LO	0xc18	/* main interrupt cause low */
+#define ICR_260_MIC_HI	0xc68	/* main interrupt cause high */
+#define ICR_260_CIM_LO	0xc1c	/* CPU interrupt mask low */
+#define ICR_260_CIM_HI	0xc6c	/* CPU interrupt mask high */
+#define ICR_260_CSC		0xc70	/* CPU select cause */
+#define ICR_260_P0IM_LO	0xc24	/* PCI_0 interrupt mask low */
+#define ICR_260_P0IM_HI	0xc64	/* PCI_0 interrupt mask high */
+#define ICR_260_P0SC	0xc74	/* PCI_0 select cause */
+#define ICR_260_P1IM_LO	0xca4	/* PCI_1 interrupt mask low */
+#define ICR_260_P1IM_HI	0xce4	/* PCI_1 interrupt mask high */
+#define ICR_260_P1SC	0xcf4	/* PCI_1 select cause */
+#define ICR_260_CI0M	0xe60	/* CPU int[0] mask */
+#define ICR_260_CI1M	0xe64	/* CPU int[1] mask */
+#define ICR_260_CI2M	0xe68	/* CPU int[2] mask */
+#define ICR_260_CI3M	0xe6c	/* CPU int[3] mask */
+
+/*
+ * MV64360 Interrupt Controller Register Map
+ */
+#define ICR_360_MIC_LO	0x004	/* main interrupt cause low */
+#define ICR_360_MIC_HI	0x00c	/* main interrupt cause high */
+#define ICR_360_C0IM_LO	0x014	/* CPU 0 interrupt mask low */
+#define ICR_360_C0IM_HI	0x01c	/* CPU 0 interrupt mask high */
+#define ICR_360_C0SC	0x024	/* CPU 0 select cause */
+#define ICR_360_C1IM_LO	0x034	/* CPU 1 interrupt mask low */
+#define ICR_360_C1IM_HI	0x03c	/* CPU 1 interrupt mask high */
+#define ICR_360_C1SC	0x044	/* CPU 1 select cause */
+#define ICR_360_I0M_LO	0x014	/* Int 0 mask low */
+#define ICR_360_I0M_HI	0x01c	/* Int 0 mask high */
+#define ICR_360_I0SC	0x024	/* Int 0 select cause */
+#define ICR_360_I1M_LO	0x034	/* Int 1 mask low */
+#define ICR_360_I1M_HI	0x03c	/* Int 1 mask high */
+#define ICR_360_C1SC	0x044	/* Int 1 select cause */
+
+
+/*
+ * IRQs:
+ * we define IRQs based on bit number in the
+ * ICU_LEN dimensioned hardware portion of the imask_t bit vector
+ * which consists of 64 bits of Main Cause and Mask register pairs
+ * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI)
+ * as well as 32 bits in GPP registers (see intr.h):
+ *
+ *      IRQs:
+ *	31.............................0  63.............................32
+ *                                     |   |                             |
+ *      imask_t index:                 |   |                             |
+ *      |                              |   |                             |
+ *      ^--------- IM_PIC_LO ----------^   ^------ IM_PIC_HI ------------^
+ *                                     |   |                             |
+ *	Bitmasks:                      |   |                             |
+ *      |                              |   |                             |
+ *      ^--------- IML_* --------------^   ^------ IMH_* ----------------^
+ *                                     |   |                             |
+ *      Registers:                     |   |                             |
+ *      |                              |   |                             |
+ *      ^--------- ICR_MIC_LO ---------^   ^------ ICR_MIC_HI -----------^
+ *      ^--------- ICR_CIM_LO ---------^   ^------ ICR_CIM_HI -----------^
+ *
+ *      IRQs:
+ *	95............................64  127............................96
+ *                                     |   |                             |
+ *      imask_t index:                 |   |                             |
+ *      |                              |   |                             |
+ *      ^-------- IMASK_GPP  ----------^   ^-----  IMASK_SOFTINT --------^
+ *                                     |   |                             |
+ *	Bitmasks:                      |   |                             |
+ *      |                              |   |                             |
+ *      ^--------- GPP_* --------------^   ^------ SIBIT(irq) -----------^
+ *                                     |   |                             |
+ *      Registers:                     |   |                             |
+ *      |                              |   |                             |
+ *      ^--- GT_GPP_Interrupt_Cause ---^   ^-------  (none)   -----------^
+ *      ^--- GT_GPP_Interrupt_Mask  ---^
+ *
+ *
+ * Note that GPP interrupts are summarized in the Main Cause Register.
+ *
+ * Some IRQs are "resvered" undefined due to gaps in HW register utilization.
+ */
+#define IRQ_DEV		1	/* device interface interrupt */
+#define IRQ_DMA		2	/* DMA addres error interrupt */
+#define IRQ_CPU		3	/* CPU interface interrupt */
+#define IRQ_IDMA0_1	4	/* IDMA ch. 0..1 complete interrupt */
+#define IRQ_IDMA2_3	5	/* IDMA ch. 2..3 complete interrupt */
+#define IRQ_IDMA4_5	6	/* IDMA ch. 4..5 complete interrupt */
+#define IRQ_IDMA6_7	7	/* IDMA ch. 6..7 complete interrupt */
+#define IRQ_TIME0_1	8	/* Timer 0..1 interrupt */
+#define IRQ_TIME2_3	9	/* Timer 2..3 interrupt */
+#define IRQ_TIME4_5	10	/* Timer 4..5 interrupt */
+#define IRQ_TIME6_7	11	/* Timer 6..7 interrupt */
+#define IRQ_PCI0_0	12	/* PCI 0 interrupt 0 summary */
+#define IRQ_PCI0_1	13	/* PCI 0 interrupt 1 summary */
+#define IRQ_PCI0_2	14	/* PCI 0 interrupt 2 summary */
+#define IRQ_PCI0_3	15	/* PCI 0 interrupt 3 summary */
+#define IRQ_PCI1_0	16	/* PCI 1 interrupt 0 summary */
+#define IRQ_ECC		17	/* ECC error interrupt */
+#define IRQ_PCI1_1	18	/* PCI 1 interrupt 1 summary */
+#define IRQ_PCI1_2	19	/* PCI 1 interrupt 2 summary */
+#define IRQ_PCI1_3	20	/* PCI 1 interrupt 3 summary */
+#define IRQ_PCI0OUT_LO	21	/* PCI 0 outbound interrupt summary */
+#define IRQ_PCI0OUT_HI	22	/* PCI 0 outbound interrupt summary */
+#define IRQ_PCI1OUT_LO	23	/* PCI 1 outbound interrupt summary */
+#define IRQ_PCI1OUT_HI	24	/* PCI 1 outbound interrupt summary */
+#define IRQ_PCI0IN_LO	26	/* PCI 0 inbound interrupt summary */
+#define IRQ_PCI0IN_HI	27	/* PCI 0 inbound interrupt summary */
+#define IRQ_PCI1IN_LO	28	/* PCI 1 inbound interrupt summary */
+#define IRQ_PCI1IN_HI	29	/* PCI 1 inbound interrupt summary */
+#define IRQ_ETH0	(32+0)	/* Ethernet controller 0 interrupt */
+#define IRQ_ETH1	(32+1)	/* Ethernet controller 1 interrupt */
+#define IRQ_ETH2	(32+2)	/* Ethernet controller 2 interrupt */
+#define IRQ_SDMA	(32+4)	/* SDMA interrupt */
+#define IRQ_I2C		(32+5)	/* I2C interrupt */
+#define IRQ_BRG		(32+7)	/* Baud Rate Generator interrupt */
+#define IRQ_MPSC0	(32+8)	/* MPSC 0 interrupt */
+#define IRQ_MPSC1	(32+10)	/* MPSC 1 interrupt */
+#define IRQ_COMM	(32+11)	/* Comm unit interrupt */
+#define IRQ_GPP7_0	(32+24)	/* GPP[7..0] interrupt */
+#define IRQ_GPP15_8	(32+25)	/* GPP[15..8] interrupt */
+#define IRQ_GPP23_16	(32+26)	/* GPP[23..16] interrupt */
+#define IRQ_GPP31_24	(32+27)	/* GPP[31..24] interrupt */
+
+/*
+ * low word interrupt mask register bits
+ */
+#define IML_SUM		BIT(0)
+#define IML_DEV		BIT(IRQ_DEV)
+#define IML_DMA		BIT(IRQ_DMA)
+#define IML_CPU		BIT(IRQ_CPU)
+#define IML_IDMA0_1	BIT(IRQ_IDMA0_1)
+#define IML_IDMA2_3	BIT(IRQ_IDMA2_3)
+#define IML_IDMA4_5	BIT(IRQ_IDMA4_5)
+#define IML_IDMA6_7	BIT(IRQ_IDMA6_7)
+#define IML_TIME0_1	BIT(IRQ_TIME0_1)
+#define IML_TIME2_3	BIT(IRQ_TIME2_3)
+#define IML_TIME4_5	BIT(IRQ_TIME4_5)
+#define IML_TIME6_7	BIT(IRQ_TIME6_7)
+#define IML_PCI0_0	BIT(IRQ_PCI0_0)
+#define IML_PCI0_1	BIT(IRQ_PCI0_1)
+#define IML_PCI0_2	BIT(IRQ_PCI0_2)
+#define IML_PCI0_3	BIT(IRQ_PCI0_3)
+#define IML_PCI1_0	BIT(IRQ_PCI1_0)
+#define IML_ECC		BIT(IRQ_ECC)
+#define IML_PCI1_1	BIT(IRQ_PCI1_1)
+#define IML_PCI1_2	BIT(IRQ_PCI1_2)
+#define IML_PCI1_3	BIT(IRQ_PCI1_3)
+#define IML_PCI0OUT_LO	BIT(IRQ_PCI0OUT_LO)
+#define IML_PCI0OUT_HI	BIT(IRQ_PCI0OUT_HI)
+#define IML_PCI1OUT_LO	BIT(IRQ_PCI1OUT_LO)
+#define IML_PCI1OUT_HI	BIT(IRQ_PCI1OUT_HI)
+#define IML_PCI0IN_LO	BIT(IRQ_PCI0IN_LO)
+#define IML_PCI0IN_HI	BIT(IRQ_PCI0IN_HI)
+#define IML_PCI1IN_LO	BIT(IRQ_PCI1IN_LO)
+#define IML_PCI1IN_HI	BIT(IRQ_PCI1IN_HI)
+#define IML_RES		(BIT(25)|BIT(30)|BIT(31))
+
+/*
+ * high word interrupt mask register bits
+ */
+#define IMH_ETH0	BIT(IRQ_ETH0-32)
+#define IMH_ETH1	BIT(IRQ_ETH1-32)
+#define IMH_ETH2	BIT(IRQ_ETH2-32)
+#define IMH_SDMA	BIT(IRQ_SDMA-32)
+#define IMH_I2C		BIT(IRQ_I2C-32)
+#define IMH_BRG		BIT(IRQ_BRG-32)
+#define IMH_MPSC0	BIT(IRQ_MPSC0-32)
+#define IMH_MPSC1	BIT(IRQ_MPSC1-32)
+#define IMH_COMM	BIT(IRQ_COMM-32)
+#define IMH_GPP7_0	BIT(IRQ_GPP7_0-32)
+#define IMH_GPP15_8	BIT(IRQ_GPP15_8-32)
+#define IMH_GPP23_16	BIT(IRQ_GPP23_16-32)
+#define IMH_GPP31_24	BIT(IRQ_GPP31_24-32)
+#define IMH_GPP_SUM	(IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24)
+#define IMH_RES		(BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \
+			|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \
+			|BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \
+			|BIT(31))
+
+/*
+ * ICR_CSC "Select Cause" register bits
+ */
+#define CSC_SEL		BIT(30)		/* HI/LO select */
+#define CSC_STAT	BIT(31)		/* ? "irq active" : "irq none"  */
+#define CSC_CAUSE	~(CSC_SEL|CSC_STAT)
+
+
+/*
+ * CPU Int[n] Mask bit(s)
+ */
+#define CPUINT_SEL	0x80000000	/* HI/LO select */
+
+#endif	/*  _DISCOVERY_GT64260INTR_H */
Index: bsps/powerpc/beatnik/include/bsp/gtpcireg.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/gtpcireg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/gtpcireg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,964 @@
+/*	$NetBSD: gtpcireg.h,v 1.4 2005/12/11 12:22:16 christos Exp $	*/
+
+/*
+ * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Allegro Networks, Inc., and Wasabi Systems, Inc.
+ * 4. The name of Allegro Networks, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ * 5. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
+ * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_GTPCIREG_H
+#define	_DEV_GTPCIREG_H
+
+#define PCI__BIT(bit)			(1U << (bit))
+#define PCI__MASK(bit)			(PCI__BIT(bit) - 1)
+#define PCI__GEN(bus, off, num)		(((off)^((bus) << 7))+((num) << 4))
+#define	PCI__EXT(data, bit, len)	(((data) >> (bit)) & PCI__MASK(len))
+#define	PCI__CLR(data, bit, len)	((data) &= ~(PCI__MASK(len) << (bit)))
+#define	PCI__INS(bit, new)		((new) << (bit))
+
+#define	PCI_SYNC_REG(bus)		(0xc0 | ((bus) << 3))
+
+/*
+ * Table 185: PCI Slave ADDRess Decoding Register Map
+ */
+#define PCI_SCS0_BAR_SIZE(bus)				PCI__GEN(bus, 0x0c08, 0)
+#define PCI_SCS2_BAR_SIZE(bus)				PCI__GEN(bus, 0x0c0c, 0)
+#define PCI_CS0_BAR_SIZE(bus)				PCI__GEN(bus, 0x0c10, 0)
+#define PCI_CS3_BAR_SIZE(bus)				PCI__GEN(bus, 0x0c14, 0)
+#define PCI_SCS1_BAR_SIZE(bus)				PCI__GEN(bus, 0x0d08, 0)
+#define PCI_SCS3_BAR_SIZE(bus)				PCI__GEN(bus, 0x0d0c, 0)
+#define PCI_CS1_BAR_SIZE(bus)				PCI__GEN(bus, 0x0d10, 0)
+#define PCI_BOOTCS_BAR_SIZE(bus)			PCI__GEN(bus, 0x0d14, 0)
+#define PCI_CS2_BAR_SIZE(bus)				PCI__GEN(bus, 0x0d18, 0)
+#define PCI_P2P_MEM0_BAR_SIZE(bus)			PCI__GEN(bus, 0x0d1c, 0)
+#define PCI_P2P_MEM1_BAR_SIZE(bus)			PCI__GEN(bus, 0x0d20, 0)
+#define PCI_P2P_IO_BAR_SIZE(bus)			PCI__GEN(bus, 0x0d24, 0)
+#define PCI_CPU_BAR_SIZE(bus)				PCI__GEN(bus, 0x0d28, 0)
+#define PCI_EXPANSION_ROM_BAR_SIZE(bus)			PCI__GEN(bus, 0x0d2c, 0)
+#define PCI_DAC_SCS0_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e00, 0)
+#define PCI_DAC_SCS1_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e04, 0)
+#define PCI_DAC_SCS2_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e08, 0)
+#define PCI_DAC_SCS3_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e0c, 0)
+#define PCI_DAC_CS0_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e10, 0)
+#define PCI_DAC_CS1_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e14, 0)
+#define PCI_DAC_CS2_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e18, 0)
+#define PCI_DAC_CS3_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e1c, 0)
+#define PCI_DAC_BOOTCS_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e20, 0)
+#define PCI_DAC_P2P_MEM0_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e24, 0)
+#define PCI_DAC_P2P_MEM1_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e28, 0)
+#define PCI_DAC_CPU_BAR_SIZE(bus)			PCI__GEN(bus, 0x0e2c, 0)
+#define PCI_BASE_ADDR_REGISTERS_ENABLE(bus)		PCI__GEN(bus, 0x0c3c, 0)
+#define PCI_SCS0_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0c48, 0)
+#define PCI_SCS1_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d48, 0)
+#define PCI_SCS2_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0c4c, 0)
+#define PCI_SCS3_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d4c, 0)
+#define PCI_CS0_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0c50, 0)
+#define PCI_CS1_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d50, 0)
+#define PCI_CS2_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d58, 0)
+#define PCI_CS3_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0c54, 0)
+#define PCI_ADDR_DECODE_CONTROL(bus)			PCI__GEN(bus, 0x0d3c, 0)
+#define PCI_BOOTCS_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d54, 0)
+#define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus)		PCI__GEN(bus, 0x0d5c, 0)
+#define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus)		PCI__GEN(bus, 0x0d60, 0)
+#define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus)		PCI__GEN(bus, 0x0d64, 0)
+#define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus)		PCI__GEN(bus, 0x0d68, 0)
+#define PCI_P2P_IO_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d6c, 0)
+#define PCI_CPU_BASE_ADDR_REMAP(bus)			PCI__GEN(bus, 0x0d70, 0)
+#define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f00, 0)
+#define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f04, 0)
+#define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f08, 0)
+#define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f0c, 0)
+#define PCI_DAC_CS0_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f10, 0)
+#define PCI_DAC_CS1_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f14, 0)
+#define PCI_DAC_CS2_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f18, 0)
+#define PCI_DAC_CS3_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f1c, 0)
+#define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f20, 0)
+#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus)	PCI__GEN(bus, 0x0f24, 0)
+#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus)	PCI__GEN(bus, 0x0f28, 0)
+#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus)	PCI__GEN(bus, 0x0f2c, 0)
+#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus)	PCI__GEN(bus, 0x0f30, 0)
+#define PCI_DAC_CPU_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f34, 0)
+#define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus)		PCI__GEN(bus, 0x0f38, 0)
+
+/*
+ * Table 186: PCI Control Register Map
+ */
+#define PCI_COMMAND(bus)				PCI__GEN(bus, 0x0c00, 0)
+#define PCI_MODE(bus)					PCI__GEN(bus, 0x0d00, 0)
+#define PCI_TIMEOUT_RETRY(bus)				PCI__GEN(bus, 0x0c04, 0)
+#define PCI_READ_BUFFER_DISCARD_TIMER(bus)		PCI__GEN(bus, 0x0d04, 0)
+#define PCI_MSI_TRIGGER_TIMER(bus)			PCI__GEN(bus, 0x0c38, 0)
+#define PCI_ARBITER_CONTROL(bus)			PCI__GEN(bus, 0x1d00, 0)
+#define PCI_INTERFACE_XBAR_CONTROL_LOW(bus)		PCI__GEN(bus, 0x1d08, 0)
+#define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus)		PCI__GEN(bus, 0x1d0c, 0)
+#define PCI_INTERFACE_XBAR_TIMEOUT(bus)			PCI__GEN(bus, 0x1d04, 0)
+#define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus)		PCI__GEN(bus, 0x1d18, 0)
+#define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus)	PCI__GEN(bus, 0x1d1c, 0)
+#define PCI_SYNC_BARRIER(bus)				PCI__GEN(bus, 0x1d10, 0)
+#define PCI_P2P_CONFIGURATION(bus)			PCI__GEN(bus, 0x1d14, 0)
+#define PCI_P2P_SWAP_CONTROL(bus)			PCI__GEN(bus, 0x1d54, 0)
+#define PCI_ACCESS_CONTROL_BASE_LOW(bus, n)		PCI__GEN(bus, 0x1e00, n)
+#define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n)		PCI__GEN(bus, 0x1e04, n)
+#define PCI_ACCESS_CONTROL_TOP(bus, n)			PCI__GEN(bus, 0x1e08, n)
+
+
+/*
+ * Table 187: PCI Snoop Control Register Map
+ */
+#define PCI_SNOOP_CONTROL_BASE_LOW(bus, n)		PCI__GEN(bus, 0x1f00, n)
+#define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n)		PCI__GEN(bus, 0x1f04, n)
+#define PCI_SNOOP_CONTROL_TOP(bus, n)			PCI__GEN(bus, 0x1f08, n)
+
+/*
+ * Table 188: PCI Configuration ACCESS_Register Map
+ */
+#define PCI_CONFIG_ADDR(bus)				PCI__GEN(bus, 0x0cf8, 0)
+#define PCI_CONFIG_DATA(bus)				PCI__GEN(bus, 0x0cfc, 0)
+#define PCI_INTR_ACK(bus)				PCI__GEN(bus, 0x0c34, 0)
+
+/*
+ * Table 189: PCI ERROR Report Register Map
+ */
+#define PCI_SERR_MASK(bus)				PCI__GEN(bus, 0x0c28, 0)
+#define PCI_ERROR_ADDRESS_LOW(bus)			PCI__GEN(bus, 0x1d40, 0)
+#define PCI_ERROR_ADDRESS_HIGH(bus)			PCI__GEN(bus, 0x1d44, 0)
+#define PCI_ERROR_DATA_LOW(bus)				PCI__GEN(bus, 0x1d48, 0)
+#define PCI_ERROR_DATA_HIGH(bus)			PCI__GEN(bus, 0x1d4c, 0)
+#define PCI_ERROR_COMMAND(bus)				PCI__GEN(bus, 0x1d50, 0)
+#define PCI_ERROR_CAUSE(bus)				PCI__GEN(bus, 0x1d58, 0)
+#define PCI_ERROR_MASK(bus)				PCI__GEN(bus, 0x1d5c, 0)
+
+
+
+/*
+ * Table 223: PCI Base Address Registers Enable
+ * If a bit is clear, the BAR is enabled.  If set, disabled.  The GT64260]
+ * prevents disabling both memory mapped and I/O mapped BARs (bits 9 and 10
+ * cannot simultaneously be set to 1).
+ */
+#define PCI_BARE_SCS0En		PCI__BIT(0)	/* SCS[0]* BAR Enable */
+#define PCI_BARE_SCS1En		PCI__BIT(1)	/* SCS[1]* BAR Enable */
+#define PCI_BARE_SCS2En		PCI__BIT(2)	/* SCS[2]* BAR Enable */
+#define PCI_BARE_SCS3En		PCI__BIT(3)	/* SCS[3]* BAR Enable */
+#define PCI_BARE_CS0En		PCI__BIT(4)	/* CS[0]* BAR Enable */
+#define PCI_BARE_CS1En		PCI__BIT(5)	/* CS[1]* BAR Enable */
+#define PCI_BARE_CS2En		PCI__BIT(6)	/* CS[2]* BAR Enable */
+#define PCI_BARE_CS3En		PCI__BIT(7)	/* CS[3]* BAR Enable */
+#define PCI_BARE_BootCSEn	PCI__BIT(8)	/* BootCS* BAR Enable */
+#define PCI_BARE_IntMemEn	PCI__BIT(9)	/* Memory Mapped Internal
+						 * Registers BAR Enable */
+#define PCI_BARE_IntIOEn	PCI__BIT(10)	/* I/O Mapped Internal
+						 * Registers BAR Enable */
+#define PCI_BARE_P2PMem0En	PCI__BIT(11)	/* P2P Mem0 BAR Enable */
+#define PCI_BARE_P2PMem1En	PCI__BIT(12)	/* P2P Mem1 BAR Enable */
+#define PCI_BARE_P2PIOEn	PCI__BIT(13)	/* P2P IO BAR Enable */
+#define PCI_BARE_CPUEn		PCI__BIT(14)	/* CPU BAR Enable */
+#define PCI_BARE_DSCS0En	PCI__BIT(15)	/* DAC SCS[0]* BAR Enable */
+#define PCI_BARE_DSCS1En	PCI__BIT(16)	/* DAC SCS[1]* BAR Enable */
+#define PCI_BARE_DSCS2En	PCI__BIT(17)	/* DAC SCS[2]* BAR Enable */
+#define PCI_BARE_DSCS3En	PCI__BIT(18)	/* DAC SCS[3]* BAR Enable */
+#define PCI_BARE_DCS0En		PCI__BIT(19)	/* DAC CS[0]* BAR Enable */
+#define PCI_BARE_DCS1En		PCI__BIT(20)	/* DAC CS[1]* BAR Enable */
+#define PCI_BARE_DCS2En		PCI__BIT(21)	/* DAC CS[2]* BAR Enable */
+#define PCI_BARE_DCS3En		PCI__BIT(22)	/* DAC CS[3]* BAR Enable */
+#define PCI_BARE_DBootCSEn	PCI__BIT(23)	/* DAC BootCS* BAR Enable */
+#define PCI_BARE_DP2PMem0En	PCI__BIT(24)	/* DAC P2P Mem0 BAR Enable */
+#define PCI_BARE_DP2PMem1En	PCI__BIT(25)	/* DAC P2P Mem1 BAR Enable */
+#define PCI_BARE_DCPUEn		PCI__BIT(26)	/* DAC CPU BAR Enable */
+
+/*
+ * Table 254: PCI Address Decode Control
+ * Bits 7:4 and 31:25 are reserved
+ * 00:00 RemapWrDis		Address Remap Registers Write Disable
+ * 				0: Writes to a BAR result in updating the
+ * 				   corresponding remap register with the BAR's
+ * 				   new value.
+ * 				1: Writes to a BAR have no affect on the
+ * 				   corresponding Remap register value.
+ * 01:01 ExpRomDev		Expansion ROM Device (0: CS[3]; 1: BootCS)
+ * 02:02 VPDDev			VPD Device (0: CS[3]; 1: BootCS)
+ * 03:03 MsgAcc			Messaging registers access
+ * 				0: Messaging unit registers are accessible on
+ * 				   lowest 4Kbyte of SCS[0] BAR space.
+ * 				1: Messaging unit registers are only accessible
+ * 				   as part of the GT64260 internal space.
+ * 07:04 Reserved
+ * 24:08 VPDHighAddr		VPD High Address bits
+ * 				[31:15] of VPD the address.
+ * 31:25 Reserved
+ */
+#define	PCI_ADC_RemapWrDis		PCI__BIT(0)
+#define PCI_ADC_ExpRomDev		PCI__BIT(1)
+#define PCI_ADC_VPDDev			PCI__BIT(2)
+#define PCI_ADC_MsgAcc			PCI__BIT(3)
+#define	PCI_ADC_VPDHighAddr_GET(v)	PCI__EXT(v, 8, 16)
+
+
+/*
+ * Table 255: PCI Command
+ * 00:00 MByteSwap	PCI Master Byte Swap
+ *				NOTE: GT-64120 and GT-64130 compatible.
+ *			When set to 0, the GTO64260 PCI master swaps the bytes
+ *			of the incoming and outgoing PCI data (swap the 8 bytes
+ *			of a longword).
+ * 01:01 Reserved
+ * 02:02 Reserved	Must be 0.
+ * 03:03 Reserved
+ * 04:04 MWrCom		PCI Master Write Combine Enable
+ *			When set to 1, write combining is enabled.
+ * 05:05 MRdCom		PCI Master Read Combine Enable
+ *			When set to 1, read combining is enabled.
+ * 06:06 MWrTrig	PCI Master Write Trigger
+ *			0: Accesses the PCI bus only when the whole burst is
+ *			   written into the master write buffer.
+ *			1: Accesses the PCI bus when the first data is written
+ *			   into the master write buffer.
+ * 07:07 MRdTrig	PCI Master Read Trigger
+ *			0: Returns read data to the initiating unit only when
+ *			   the whole burst is written into master read buffer.
+ *			1: Returns read data to the initiating unit when the
+ *			   first read data is written into master read buffer.
+ * 08:08 MRdLine	PCI Master Memory Read Line Enable
+ *			(0: Disable; 1: Enable)
+ * 09:09 MRdMul		PCI Master Memory Read Multiple Enable
+ *			(0: Disable; 1: Enable)
+ * 10:10 MWordSwap	PCI Master Word Swap
+ *				NOTE: GT-64120 and GT-64130 compatible.
+ *			When set to 1, the GT64260 PCI master swaps the 32-bit
+ *			words of the incoming and outgoing PCI data.
+ * 11:11 SWordSwap	PCI Slave Word Swap
+ *				NOTE: GT-64120 and GT-64130 compatible.
+ *			When set to 1, the GT64260 PCI slave swaps the 32-bit
+ *			words of the incoming and outgoing PCI data.
+ * 12:12 IntBusCtl	PCI Interface Unit Internal Bus Control
+ *				NOTE: Reserved for Galileo Technology usage
+ *			0: Enable internal bus sharing between master and
+ *			   slave interfaces.
+ *			1: Disable internal bus sharing between master and
+ *			   slave interfaces.
+ * 13:13 SBDis		PCI Slave Sync Barrier Disable
+ *			When set to 1, the PCI configuration read transaction
+ *			will stop act as sync barrier transaction.
+ * 14:14 Reserved	Must be 0
+ * 15:15 MReq64		PCI Master REQ64* Enable (0: Disable; 1: Enable)
+ * 16:16 SByteSwap	PCI Slave Byte Swap
+ *				NOTE: GT-64120 and GT-64130 compatible.
+ *			When set to 0, the GT64260 PCI slave swaps the bytes of
+ *			the incoming and outgoing PCI data (swap the 8 bytes of
+ *			a long-word).
+ * 17:17 MDACEn		PCI Master DAC Enable
+ *			0: Disable (The PCI master never drives the DAC cycle)
+ *			1: Enable (In case the upper 32-bit address is not 0,
+ *			   the PCI master drives the DAC cycle)
+ * 18:18 M64Allign	PCI Master REQ64* assertion on non-aligned
+ *			0: Disable (The master asserts REQ64* only if
+ *			   the address is 64-bit aligned)
+ *			1: Enable (The master asserts REQ64* even if
+ *			   the address is not 64-bit aligned)
+ * 19:19 PErrProp	Parity/ECC Errors Propagation Enable
+ *			0: Disable (The PCI interface always drives
+ *			   correct parity on the PAR signal)
+ *			1: Enable (In case of slave read bad ECC from
+ *			   SDRAM, or master write with bad parity/ECC
+ *			   indication from the initiator, the PCI interface
+ *			   drives bad parity on the PAR signal)
+ * 20:20 SSwapEn	PCI Slave Swap Enable
+ *				NOTE: Even if the SSwapEn bit is set to 1 and
+ *				the PCI address does not match any of the
+ *				Access Control registers, slave data swapping
+ *				works according to SByteSwap and SWordSwap bits.
+ *			0: PCI slave data swapping is determined via
+ *			   SByteSwap and SWordSwap bits (bits 16 and 11),
+ *			   as in the GT-64120/130.
+ *			1: PCI slave data swapping is determined via PCISwap
+ *			   bits [25:24] in the PCI Access Control registers.
+ * 21:21 MSwapEn	PCI Master Swap Enable
+ *			0: PCI master data swapping is determined via
+ *			   MByteSwap and MWordSwap bits (bits 0 and 10),
+ *			   as in the GT-64120/130.
+ *			1: PCI master data swapping is determined via
+ *			   PCISwap bits in CPU to PCI Address Decoding
+ *			   registers.
+ * 22:22 MIntSwapEn	PCI Master Configuration Transactions Data Swap Enable
+ *				NOTE: Reserved for Galileo Technology usage.
+ *			0: Disable (The PCI master configuration transaction
+ *			   to the PCI bus is always in Little Endian convention)
+ *			1: Enable (The PCI master configuration transaction to
+ *			   the PCI bus is determined according to the setting
+ *			   of MSwapEn bit)
+ * 23:23 LBEn		PCI Loop Back Enable
+ *				NOTE: Reserved for Galileo Technology usage.
+ *			0: Disable (The PCI slave does not respond to
+ *			   transactions initiated by the PCI master)
+ *			1: Enable (The PCI slave does respond to
+ *			   transactions initiated by the PCI master,
+ *			   if targeted to the slave (address match)
+ * 26:24 SIntSwap	PCI Slave data swap control on PCI accesses to the
+ *			GT64260 internal and configuration registers.
+ *			Bits encoding are the same as bits[26:24] in PCI Access
+ *			Control registers.
+ * 27:27 Reserved	Must be 0.
+ * 31:28 Reserved	Read only.
+ */
+#define	PCI_CMD_MByteSwap	PCI__BIT(0)
+#define	PCI_CMD_MBZ0_2		PCI__BIT(2)
+#define	PCI_CMD_MWrCom		PCI__BIT(4)
+#define	PCI_CMD_MRdCom		PCI__BIT(5)
+#define	PCI_CMD_MWrTrig		PCI__BIT(6)
+#define	PCI_CMD_MRdTrig		PCI__BIT(7)
+#define	PCI_CMD_MRdLine		PCI__BIT(8)
+#define	PCI_CMD_MRdMul		PCI__BIT(9)
+#define	PCI_CMD_MWordSwap	PCI__BIT(10)
+#define	PCI_CMD_SWordSwap	PCI__BIT(11)
+#define	PCI_CMD_IntBusCtl	PCI__BIT(12)
+#define	PCI_CMD_SBDis		PCI__BIT(13)
+#define	PCI_CMD_MBZ0_14		PCI__BIT(14)
+#define	PCI_CMD_MReq64		PCI__BIT(15)
+#define	PCI_CMD_SByteSwap	PCI__BIT(16)
+#define	PCI_CMD_MDCAEn		PCI__BIT(17)
+#define	PCI_CMD_M64Allign	PCI__BIT(18)
+#define	PCI_CMD_PErrProp	PCI__BIT(19)
+#define	PCI_CMD_SSwapEn		PCI__BIT(20)
+#define	PCI_CMD_MSwapEn		PCI__BIT(21)
+#define	PCI_CMD_MIntSwapEn	PCI__BIT(22)
+#define	PCI_CMD_LBEn		PCI__BIT(23)
+#define	PCI_CMD_SIntSwap_GET(v)	PCI__EXT(v, 24, 3)
+#define	PCI_CMD_MBZ0_27		PCI__BIT(27)
+
+
+/*
+ * Table 256: PCI Mode
+ * 00:00 PciID		PCI Interface ID -- Read Only (PCI_0: 0x0; PCI_1: 0x1)
+ * 01:01 Reserved
+ * 02:02 Pci64		64-bit PCI Interface -- Read Only
+ *			When set to 1, the PCI interface is configured to a
+ *			64 bit interface.
+ * 07:03 Reserved
+ * 08:08 ExpRom		Expansion ROM Enable -- Read Only from PCI
+ *			When set to 1, the expansion ROM BAR is enabled.
+ * 09:09 VPD		VPD Enable -- Read Only from PCI
+ *			When set to 1, VPD is supported.
+ * 10:10 MSI		MSI Enable -- Read Only from PCI
+ *			When set to 1, MSI is supported.
+ * 11:11 PMG		Power Management Enable -- Read Only from PCI
+ *			When set to 1, PMG is supported.
+ * 12:12 HotSwap	CompactPCI Hot Swap Enable -- Read Only from PCI
+ *			When set to 1, HotSwap is supported.
+ * 13:13 BIST		BIST Enable -- Read only from PCI
+ *			If set to 1, BIST is enabled.
+ * 30:14 Reserved
+ * 31:31 PRst		PCI Interface Reset Indication -- Read Only
+ *			Set to 0 as long as the RST* pin is asserted.
+ */
+#define	PCI_MODE_PciID_GET(v)	PCI__EXT(v, 0, 1)
+#define	PCI_MODE_Pci64		PCI__BIT(2)
+#define	PCI_MODE_ExpRom		PCI__BIT(8)
+#define	PCI_MODE_VPD		PCI__BIT(9)
+#define	PCI_MODE_MSI		PCI__BIT(10)
+#define	PCI_MODE_PMG		PCI__BIT(11)
+#define	PCI_MODE_HotSwap	PCI__BIT(12)
+#define	PCI_MODE_BIST		PCI__BIT(13)
+#define	PCI_MODE_PRst		PCI__BIT(31)
+
+/*
+ * Table 257: PCI Timeout and Retry
+ * 07:00 Timeout0	Specifies the number of PClk cycles the GT64260 slave
+ *			holds the PCI bus before terminating a transaction
+ *			with RETRY.
+ * 15:08 Timeout1	Specifies the number of PClk cycles the GT64260 slave
+ *			holds the PCI bus before terminating a transaction
+ *			with DISCONNECT.
+ * 23:16 RetryCtr	Retry Counter
+ *			Specifies the number of retries of the GT64260 Master.
+ *			The GT64260 generates an interrupt when this timer
+ *			expires.  A 0x00 value means a retry forever.
+ * 31:24 Reserved
+ */
+#define	PCI_TMORTRY_Timeout0_GET(v)	PCI__EXT(v, 0, 8)
+#define	PCI_TMORTRY_Timeout1_GET(v)	PCI__EXT(v, 8, 8)
+#define	PCI_TMORTRY_RetryCtr_GET(v)	PCI__EXT(v, 16, 8)
+
+
+/*
+ * Table 258: PCI Read Buffer Discard Timer
+ * 15:00 Timer		Specifies the number of PClk cycles the GT64260
+ *			slave keeps an non-accessed read buffers (non com-
+ *			pleted delayed read) before invalidating the buffer.
+ * 23:16 RdBufEn	Slave Read Buffers Enable
+ *			Each bit corresponds to one of the eight read buffers.
+ *			If set to 1, buffer is enabled.
+ * 31:24 Reserved
+ */
+#define	PCI_RdBufDisTmr_Timer_GET(v)	PCI__EXT(v, 0, 16)
+#define	PCI_RdBufDisTmr_RdBufEn_GET(v)	PCI__EXT(v, 16, 8)
+#define	PCI_RdBufDisTmr_RdBufEn0(v)	PCI__BIT(16)
+#define	PCI_RdBufDisTmr_RdBufEn1(v)	PCI__BIT(17)
+#define	PCI_RdBufDisTmr_RdBufEn2(v)	PCI__BIT(18)
+#define	PCI_RdBufDisTmr_RdBufEn3(v)	PCI__BIT(19)
+#define	PCI_RdBufDisTmr_RdBufEn4(v)	PCI__BIT(20)
+#define	PCI_RdBufDisTmr_RdBufEn5(v)	PCI__BIT(21)
+#define	PCI_RdBufDisTmr_RdBufEn6(v)	PCI__BIT(22)
+#define	PCI_RdBufDisTmr_RdBufEn7(v)	PCI__BIT(23)
+
+/*
+ * Table 259: MSI Trigger Timer
+ * 15:00 Timer		Specifies the number of TClk cycles between consecutive
+ *			MSI requests.
+ * 31:16 Reserved
+ */
+#define	PCI_MSITrigger_Timer_GET(v)	PCI__EXT(v, 0, 16)
+
+/*
+ * Table 260: PCI Arbiter Control
+ *	NOTE:	If HPPV (bits [28:21]) is set to 0 and PAEn is set to 1,
+ *		priority scheme is reversed. This means that high priority
+ *		requests are granted if no low priority request is pending.
+ * 00:00 Reserved	Must be 0. 0x0
+ * 01:01 BDEn		Broken Detection Enable
+ *			If set to 1, broken master detection is enabled. A mas-
+ *			ter is said to be broken if it fails to respond to grant
+ *			assertion within a window specified in BV (bits [6:3]).
+ * 02:02 PAEn		Priority Arbitration Enable
+ *			0: Low priority requests are granted only when no high
+ *			   priority request is pending
+ *			1: Weighted round robin arbitration is performed
+ *			   between high priority and low priority groups.
+ * 06:03 BV		Broken Value
+ *			This value sets the maximum number of cycles that the
+ *			arbiter waits for a PCI master to respond to its grant
+ *			assertion. If a PCI master fails to assert FRAME* within
+ *			this time, the PCI arbiter aborts the transaction and
+ *			performs a new arbitration cycle and a maskable
+ *			interrupt is generated. Must be greater than 0.
+ *			NOTE:	The PCI arbiter waits for the current
+ *				transaction to end before starting to
+ *				count the wait-for-broken cycles.
+ *			Must be greater than 1 for masters that performs address
+ *			stepping (such as the GTO 64260 PCI master), since they
+ *			require GNT* assertion for two cycles.
+ * 13:07 P[6:0]		Priority
+ *			These bits assign priority levels to the requests
+ *			connected to the PCI arbiter. When a PM bit is set to
+ *			1, priority of the associated request is high.  The
+ *			mapping between P[6:0] bits and the request/grant pairs
+ *			are as follows:
+ *			 P[0]: internal PCI master	P[1]: external REQ0/GNT0
+ *			 P[2]: external REQ1/GNT1	P[3]: external REQ2/GNT2
+ *			 P[4]: external REQ3/GNT3	P[5]: external REQ4/GNT4
+ *			 P[6]: external REQ5/GNT5
+ * 20:14 PD[6:0]	Parking Disable
+ *			Use these bits to disable parking on any of the PCI
+ *			masters.  When a PD bit is set to 1, parking on the
+ *			associated PCI master is disabled.
+ *			NOTE:	The arbiter parks on the last master granted
+ *				unless disabled through the PD bit. Also, if
+ *				PD bits are all 1, the PCI arbiter parks on
+ *				the internal PCI master.
+ * 28:21 HPPV		High Priority Preset Value
+ *			This is the preset value of the high priority counter
+ *			(High_cnt). This counter decrements each time a high
+ *			priority request is granted. When the counter reaches
+ *			zero, it reloads with this preset value.  The counter
+ *			reloads when a low priority request is granted.
+ * 30:29 Reserved
+ * 31:31 EN		Enable
+ *			Setting this bit to 1 enables operation of the arbiter.
+ */
+#define	PCI_ARBCTL_MBZ0_0		PCI__BIT(0)
+#define	PCI_ARBCTL_BDEn			PCI__BIT(1)
+#define	PCI_ARBCTL_PAEn			PCI__BIT(2)
+#define	PCI_ARBCTL_BV_GET(v)		PCI__EXT(v, 3, 4)
+#define	PCI_ARBCTL_P_GET(v)		PCI__EXT(v, 7, 7)
+#define	PCI_ARBCTL_PD_GET(v)		PCI__EXT(v, 14, 7)
+#define	PCI_ARBCTL_HPPV_GET(v)		PCI__EXT(v, 21, 7)
+#define	PCI_ARBCTL_EN			PCI__BIT(31)
+
+#define	PCI_ARBPRI_IntPci		PCI__BIT(0)
+#define	PCI_ARBPRI_ExtReqGnt0		PCI__BIT(1)
+#define	PCI_ARBPRI_ExtReqGnt1		PCI__BIT(2)
+#define	PCI_ARBPRI_EXtReqGnt2		PCI__BIT(3)
+#define	PCI_ARBPRI_EXtReqGnt3		PCI__BIT(4)
+#define	PCI_ARBPRI_EXtReqGnt4		PCI__BIT(5)
+#define	PCI_ARBPRI_EXtReqGnt5		PCI__BIT(6)
+
+/*
+ * Table 261: PCI Interface Crossbar Control (Low)
+ * 03:00 Arb0		Slice 0 of PCI master pizza arbiter.
+ * 07:04 Arb1		Slice 1 of PCI master pizza arbiter.
+ * 11:08 Arb2		Slice 2 of PCI master pizza arbiter.
+ * 15:12 Arb3		Slice 3 of PCI master pizza arbiter.
+ * 19:16 Arb4		Slice 4 of PCI master pizza arbiter.
+ * 23:20 Arb5		Slice 5 of PCI master pizza arbiter.
+ * 27:24 Arb6		Slice 6 of PCI master pizza arbiter.
+ * 31:28 Arb7		Slice 7 of PCI master pizza arbiter.
+ */
+#define	PCI_IFXBRCTL_GET_SLICE(v, n)	PCI__EXT(v, (n) * 4, 4)
+#define	PCI_IFXBRCTL_SET_SLICE(v, n, s)	((void)(PCI__CLR(v, (n)*4, 4),\
+						(v) |= PCI__INS((n)*4, s)))
+
+/*
+ * Table 262: PCI Interface Crossbar Control (High)
+ * 03:00 Arb8		Slice 8 of PCI master pizza arbiter.
+ * 07:04 Arb9		Slice 9 of PCI master pizza arbiter.
+ * 11:08 Arb10		Slice 10 of PCI master pizza arbiter.
+ * 15:12 Arb11		Slice 11 of PCI master pizza arbiter.
+ * 19:16 Arb12		Slice 12 of PCI master pizza arbiter.
+ * 23:20 Arb13		Slice 13 of PCI master pizza arbiter.
+ * 27:24 Arb14		Slice 14 of PCI master pizza arbiter.
+ * 31:28 Arb15		Slice 15 of PCI master pizza arbiter.
+ */
+#define	PCI_IFXBRCH_GET_SLICE(v, n)	PCI__EXT(v, ((n) - 8) * 4, 4)
+#define	PCI_IFXBRCH_SET_SLICE(v, n, s)	((void)(PCI__CLR(v, ((n)*-8)4, 4),\
+						(v) |= PCI__INS(((n)-8)*4, s)))
+
+/*
+ * Table 263: PCI Interface Crossbar Timeout
+		(NOTE: Reserved for Galileo Technology usage.)
+ * 07:00 Timeout	Crossbar Arbiter Timeout Preset Value
+ * 15:08 Reserved
+ * 16:16 TimeoutEn	Crossbar Arbiter Timer Enable (1: Disable)
+ * 31:17 Reserved
+ */
+#define PCI_IFXBRTMO_Timeout_GET(v)	PCI__EXT(v, 0, 8)
+#define PCI_IFXBRTMO_TimeoutEn		PCI__BIT(16)
+
+/*
+ * Table 264: PCI Read Response Crossbar Control (Low)
+ * 03:00 Arb0		Slice 0 of PCI slave pizza arbiter.
+ * 07:04 Arb1		Slice 1 of PCI slave pizza arbiter.
+ * 11:08 Arb2		Slice 2 of PCI slave pizza arbiter.
+ * 15:12 Arb3		Slice 3 of PCI slave pizza arbiter.
+ * 19:16 Arb4		Slice 4 of PCI slave pizza arbiter.
+ * 23:20 Arb5		Slice 5 of PCI slave pizza arbiter.
+ * 27:24 Arb6		Slice 6 of PCI slave pizza arbiter.
+ * 31:28 Arb7		Slice 7 of PCI slave pizza arbiter.
+ */
+#define	PCI_RRXBRCL_GET_SLICE(v, n)	PCI__EXT(v, (n) * 4, 4)
+#define	PCI_RRXBRCL_SET_SLICE(v, n, s)	((void)(PCI__CLR(v, (n)*4, 4),\
+						(v) |= PCI__INS((n)*4, s)))
+
+
+/*
+ * Table 265: PCI Read Response Crossbar Control (High)
+ * 03:00 Arb8		Slice 8 of PCI slave pizza arbiter.
+ * 07:04 Arb9		Slice 9 of PCI slave pizza arbiter.
+ * 11:08 Arb10		Slice 10 of PCI slave pizza arbiter.
+ * 15:12 Arb11		Slice 11 of PCI slave pizza arbiter.
+ * 19:16 Arb12		Slice 12 of PCI slave pizza arbiter.
+ * 23:20 Arb13		Slice 13 of PCI slave pizza arbiter.
+ * 27:24 Arb14		Slice 14 of PCI slave pizza arbiter.
+ * 31:28 Arb15		Slice 15 of PCI slave pizza arbiter.
+ */
+#define	PCI_RRXBRCH_GET_SLICE(v, n)	PCI__EXT(v, ((n) - 8) * 4, 4)
+#define	PCI_RRXBRCH_SET_SLICE(v, n, s)	((void)(PCI__CLR(v, ((n)*-8)4, 4),\
+						(v) |= PCI__INS(((n)-8)*4, s)))
+
+/*
+ * Table 266: PCI Sync Barrier Virtual Register
+ * 31:0 SyncReg Sync Barrier Virtual Register
+ * PCI read from this register results in PCI slave sync barrier
+ * action.  The returned data is un-deterministic.  Read Only.
+ */
+
+/*
+ * Table 267: PCI P2P Configuration
+ * 07:00 2ndBusL	Secondary PCI Interface Bus Range Lower Boundary
+ * 15:08 2ndBusH	Secondary PCI Interface Bus Range Upper Boundary
+ * 23:16 BusNum		The PCI bus number to which the PCI interface
+ *			is connected.
+ * 28:24 DevNum		The PCI interface's device number.
+ * 31:29 Reserved	Reserved.
+ */
+#define	PCI_P2PCFG_2ndBusL_GET(v)	PCI__EXT(v,  0, 8)
+#define	PCI_P2PCFG_2ndBusH_GET(v)	PCI__EXT(v,  8, 8)
+#define	PCI_P2PCFG_BusNum_GET(v)	PCI__EXT(v, 16, 8)
+#define	PCI_P2PCFG_DevNum_GET(v)	PCI__EXT(v, 24, 5)
+
+/*
+ * Table 268: PCI P2P Swap Control
+ * 02:00 M0Sw		P2P Mem0 BAR Swap Control
+ * 03:03 M0Req64	P2P Mem0 BAR Force REQ64
+ * 06:04 M1Sw		P2P Mem1 BAR Swap Control
+ * 07:07 M1Req64	P2P Mem1 BAR Force REQ64
+ * 10:08 DM0Sw		P2P DAC Mem0 BAR Swap Control
+ * 11:11 DM0Req64	P2P DAC Mem0 BAR Force REQ64
+ * 14:12 DM1Sw		P2P DAC Mem1 BAR Swap Control
+ * 15:15 DM1Req64	P2P DAC Mem1 BAR Force REQ64
+ * 18:16 IOSw		P2P I/O BAR Swap Control
+ * 19:19 Reserved
+ * 22:20 CfgSw		P2P Configuration Swap Control
+ * 31:19 Reserved
+ */
+#define	PCI_P2PSWAP_M0Sw_GET(v)		PCI__EXT(v, 0, 3)
+#define	PCI_P2PSWAP_M0Req64		PCI__BIT(3)
+#define	PCI_P2PSWAP_M1Sw_GET(v)		PCI__EXT(v, 4, 3)
+#define	PCI_P2PSWAP_M1Req64		PCI__BIT(7)
+#define	PCI_P2PSWAP_DM0Sw_GET(v)	PCI__EXT(v, 8, 3)
+#define	PCI_P2PSWAP_DM0Req64		PCI__BIT(11)
+#define	PCI_P2PSWAP_DM1Sw_GET(v)	PCI__EXT(v, 12, 3)
+#define	PCI_P2PSWAP_DM1Req64		PCI__BIT(15)
+#define	PCI_P2PSWAP_CfgSw_GET(v)	PCI__EXT(v, 20, 3)
+
+
+
+/*
+ * Table 269: PCI Access Control Base (Low)
+ * 11:00 Addr		Base Address Corresponds to address bits[31:20].
+ * 12:12 PrefetchEn	Read Prefetch Enable
+ *			0: Prefetch disabled (The PCI slave reads single words)
+ *			1: Prefetch enabled.
+ * 14:14 Reserved	 Must be 0
+ * 15:15 Reserved
+ * 16:16 RdPrefetch	PCI Read Aggressive Prefetch Enable; 0: Disable;
+ *			1: Enable (The PCI slave prefetches two
+ *			bursts in advance)
+ * 17:17 RdLinePrefetch	PCI Read Line Aggressive Prefetch Enable; 0: Disable;
+ *			1: Enable (PCI slave prefetch two bursts in advance)
+ * 18:18 RdMulPrefetch	PCI Read Multiple Aggressive Prefetch Enable
+ *			0: Disable; 1: Enable (PCI slave prefetch two bursts in
+ *			advance)
+ * 19:19 Reserved
+ * 21:20 MBurst		PCI Max Burst
+ *			Specifies the maximum burst size for a single transac-
+ *			tion between a PCI slave and the other interfaces
+ *				00 - 4 64-bit words
+ *				01 - 8 64-bit words
+ *				10 - 16 64-bit words
+ *				11 - Reserved
+ * 23:22 Reserved
+ * 25:24 PCISwap	Data Swap Control
+ *				00 - Byte Swap
+ *				01 - No swapping
+ *				10 - Both byte and word swap
+ *				11 - Word swap
+ * 26:26 Reserved	Must be 0
+ * 27:27 Reserved
+ * 28:28 AccProt	Access Protect (0: PCI access is allowed; 1; Region is
+			not accessible from PCI)
+ * 29:29 WrProt		Write Protect (0: PCI write is allowed; 1: Region is
+ *			not writeable from PCI)
+ * 31:30 Reserved
+ */
+#define	PCI_ACCCTLBASEL_Addr_GET(v)	PCI__EXT(v, 0, 12)
+#define	PCI_ACCCTLBASEL_PrefetchEn	PCI__BIT(12)
+#define PCI_ACCCTLBASEL_MBZ0_14		PCI__BIT(14)
+#define PCI_ACCCTLBASEL_RdPrefetch	PCI__BIT(16)
+#define PCI_ACCCTLBASEL_RdLinePrefetch	PCI__BIT(17)
+#define PCI_ACCCTLBASEL_RdMulPrefetch	PCI__BIT(18)
+#define PCI_ACCCTLBASEL_WBurst		PCI__EXT(v, 20, 2)
+#define PCI_ACCCTLBASEL_WBurst_8_QW	PCI__INS(20, PCI_WBURST_8_QW)
+#define PCI_ACCCTLBASEL_PCISwap		PCI__EXT(v, 24, 2)
+#define PCI_ACCCTLBASEL_PCISwap_NoSwap	PCI__INS(24, PCI_PCISWAP_NoSwap)
+#define PCI_ACCCTLBASEL_MBZ0_26		PCI__BIT(26)
+#define PCI_ACCCTLBASEL_AccProt		PCI__BIT(28)
+#define PCI_ACCCTLBASEL_WrProt		PCI__BIT(29)
+
+#define	PCI_WBURST_4_QW			0x00
+#define	PCI_WBURST_8_QW			0x01
+#define	PCI_WBURST_16_QW		0x02
+#define	PCI_WBURST_Reserved		0x04
+
+#define	PCI_PCISWAP_ByteSwap		0x00
+#define	PCI_PCISWAP_NoSwap		0x01
+#define	PCI_PCISWAP_ByteWordSwap	0x02
+#define	PCI_PCISWAP_WordSwap		0x04
+
+/*
+ * Table 293: PCI Snoop Control Base (Low)
+ * 11:00 Addr		Base Address	 Corresponds to address bits[31:20].
+ * 13:12 Snoop		Snoop Type
+ * 31:14 Reserved
+ */
+#define PCI_SNOOPCTL_ADDR(v)	PCI__EXT(v, 0, 12)
+#define PCI_SNOOPCTL_TYPE(v)	PCI__EXT(v, 12, 2)
+
+#define	PCI_SNOOP_None		0	/* no snoop */
+#define	PCI_SNOOP_WT		1	/* Snoop to WT region */
+#define	PCI_SNOOP_WB		2	/* Snoop to WB region */
+
+
+/*
+ * Table 305: PCI Configuration Address
+ *
+ * 07:02 RegNum		Register number.
+ * 10:08 FunctNum	Function number.
+ * 15:11 DevNum		Device number.
+ * 23:16 BusNum		Bus number.
+ * 31:31 ConfigEn	When set, an access to the Configuration Data
+ *			register is translated into a Configuration
+ *			or Special cycle on the PCI bus.
+ */
+#define	PCI_CFG_MAKE_TAG(bus, dev, fun, reg)	(PCI__BIT(31)|\
+						 PCI__INS(16, (bus))|\
+						 PCI__INS(11, (dev))|\
+						 PCI__INS( 8, (fun))|\
+						 PCI__INS( 0, (reg)))
+#define	PCI_CFG_GET_BUSNO(tag)			PCI__EXT(tag, 16, 8)
+#define	PCI_CFG_GET_DEVNO(tag)			PCI__EXT(tag, 11, 5)
+#define	PCI_CFG_GET_FUNCNO(tag)			PCI__EXT(tag,  8, 3)
+#define	PCI_CFG_GET_REGNO(tag)			PCI__EXT(tag,  0, 8)
+
+/*
+ * Table 306: PCI Configuration Data
+ *
+ * 31:00 ConfigData	The data is transferred to/from the PCI bus when
+ *			the CPU accesses this register and the ConfigEn
+ *			bit in the Configuration Address register is set
+ *
+ * A CPU access to this register causes the GT64260 to perform a Configuration
+ * or Special cycle on the PCI bus.
+ */
+
+
+/*
+ * Table 307: PCI Interrupt Acknowledge (This register is READ ONLY)
+ * 31:00 IntAck		A CPU read access to this register forces an
+ *			interrupt acknowledge cycle on the PCI bus.
+ */
+
+
+/*
+ * Table 308: PCI SERR* Mask
+ *
+ * NOTE: The GT64260 asserts SERR* only if SERR* is enabled via the PCI Status
+ *       and Command register.
+ * If the corresponding bit is set, then asserts SERR* upon ...
+ */
+#define PCI_SERRMSK_SAPerr	PCI__BIT(0)	/* PCI slave detection of bad
+						 * address parity. */
+#define PCI_SERRMSK_SWrPerr	PCI__BIT(1)	/* PCI slave detection of bad
+						 * write data parity. */
+#define PCI_SERRMSK_SRdPerr	PCI__BIT(2)	/* a PERR* response to read
+						 * data driven by the PCI
+						 * slave. */
+#define PCI_SERRMSK_MAPerr	PCI__BIT(4)	/* a PERR* response to an
+						 * address driven by the PCI
+						 * master. */
+#define PCI_SERRMSK_MWrPerr	PCI__BIT(5)	/* a PERR* response to write
+						 * data driven by the PCI
+						 * master. */
+#define PCI_SERRMSK_MRdPerr	PCI__BIT(6)	/* bad data parity detection
+						 * during a PCI master read
+						 * transaction. */
+#define PCI_SERRMSK_MMabort	PCI__BIT(8)	/* a PCI master generation of
+						 * master abort. */
+#define PCI_SERRMSK_MTabort	PCI__BIT(9)	/* a PCI master detection of
+						 * target abort. */
+#define PCI_SERRMSK_MRetry	PCI__BIT(11)	/* a PCI master reaching retry
+						 * counter limit. */
+#define PCI_SERRMSK_SMabort	PCI__BIT(16)	/* a PCI slave detection of
+						 * master abort. */
+#define PCI_SERRMSK_STabort	PCI__BIT(17)	/* a PCI slave termination of
+						 * a transaction with Target
+						 * Abort. */
+#define PCI_SERRMSK_SAccProt	PCI__BIT(18)	/* a PCI slave access protect
+						 * violation. */
+#define PCI_SERRMSK_SWrProt	PCI__BIT(19)	/* a PCI slave write protect
+						 * violation. */
+#define PCI_SERRMSK_SRdBuf	PCI__BIT(20)	/* the PCI slave's read buffer,
+						 * discard timer expires */
+#define PCI_SERRMSK_Arb		PCI__BIT(21)	/* the internal PCI arbiter
+						 * detection of a broken PCI
+						 * master. */
+
+#define PCI_SERRMSK_ALL_ERRS \
+	(PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \
+	|PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \
+	|PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \
+	|PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \
+	|PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb)
+
+
+
+/*
+ * Table 309: PCI Error Address (Low) -- Read Only.
+ * 31:00 ErrAddr	PCI address bits [31:0] are latched upon an error
+ *			condition.  Upon address latch, no new addresses can
+ *			be registered (due to additional error condition) until
+ *			the register is being read.
+ */
+
+
+
+/*
+ * Table 310: PCI Error Address (High)	Applicable only when running DAC cycles.
+ * 31:00 ErrAddr	PCI address bits [63:32] are latched upon
+ *			error condition.
+ *
+ * NOTE: Upon data sample, no new data is latched until the PCI Error Low
+ *       Address register is read. This means that PCI Error Low Address
+ *       register must bethe last register read by the interrupt handler.
+ */
+
+/*
+ * Table 311: PCI Error Data (Low)
+ * 31:00 ErrData	PCI data bits [31:00] are latched upon error condition.
+ */
+
+/*
+ * Table 312: PCI Error Data (High)	Applicable only when running
+ *					64-bit cycles.
+ * 31:00 ErrData	PCI data bits [63:32] are latched upon error condition.
+ */
+
+/*
+ * Table 313: PCI Error Command
+ * 03:00 ErrCmd		PCI command is latched upon error condition.
+ * 07:04 Reserved
+ * 15:08 ErrBE		PCI byte enable is latched upon error condition.
+ * 16:16 ErrPAR		PCI PAR is latched upon error condition.
+ * 17:17 ErrPAR64	PCI PAR64 is latched upon error condition.
+ *			Applicable only when running 64-bit cycles.
+ * 31:18 Reserved
+ * NOTE: Upon data sample, no new data is latched until the PCI Error Low
+ * Address register is read. This means that PCI Error Low Address register
+ * must be the last register read by the interrupt handler.
+ */
+#define PCI_ERRCMD_Cmd_GET(v)		PCI__EXT(v, 0, 4)
+#define PCI_ERRCMD_ByteEn_GET(v)	PCI__EXT(v, 8, 8)
+#define	PCI_ERRCMD_PAR			PCI__BIT(16)
+#define	PCI_ERRCMD_PAR64		PCI__BIT(17)
+
+/*
+ * Table 314: PCI Interrupt Cause
+ * 1. All bits are Clear Only. A cause bit set upon error event occurrence.
+ *    A write of 0 clears the bit. A write of 1 has no affect.
+ * 2. PCI Interrupt bits are organized in four groups:
+ *    bits[ 7: 0] for address and data parity errors,
+ *    bits[15: 8] for PCI master transaction failure (possible external
+ *		  target problem),
+ *    bits[23:16] for slave response failure (possible external master problem),
+ *    bits[26:24] for external PCI events that require CPU handle.
+ */
+#define PCI_IC_SAPerr		PCI__BIT(0)	/* The PCI slave detected
+						 * bad address parity. */
+#define PCI_IC_SWrPerr		PCI__BIT(1)	/* The PCI slave detected
+						 * bad write data parity. */
+#define PCI_IC_SRdPerr		PCI__BIT(2)	/* PERR* response to read
+						 * data driven by PCI slave. */
+#define PCI_IC_MAPerr		PCI__BIT(4)	/* PERR* response to address
+						 * driven by the PCI master. */
+#define PCI_IC_MWrPerr		PCI__BIT(5)	/* PERR* response to write data
+						 * driven by the PCI master. */
+#define PCI_IC_MRdPerr		PCI__BIT(6)	/* Bad data parity detected
+						 * during the PCI master read
+						 * transaction. */
+#define PCI_IC_MMabort		PCI__BIT(8)	/* The PCI master generated
+						 * master abort. */
+#define PCI_IC_MTabort		PCI__BIT(9)	/* The PCI master detected
+						 * target abort. */
+#define PCI_IC_MMasterEn	PCI__BIT(10)	/* An attempt to generate a PCI
+						 * transaction while master is
+						 * not enabled. */
+#define PCI_IC_MRetry		PCI__BIT(11)	/* The PCI master reached
+						 * retry counter limit. */
+#define PCI_IC_SMabort		PCI__BIT(16)	/* The PCI slave detects an il-
+						 * legal master termination. */
+#define PCI_IC_STabort		PCI__BIT(17)	/* The PCI slave terminates a
+						 * transaction with Target
+						 * Abort. */
+#define PCI_IC_SAccProt		PCI__BIT(18)	/* A PCI slave access protect
+						 * violation. */
+#define PCI_IC_SWrProt		PCI__BIT(19)	/* A PCI slave write protect
+						 * violation. */
+#define PCI_IC_SRdBuf		PCI__BIT(20)	/* A PCI slave read buffer
+						 * discard timer expired. */
+#define PCI_IC_Arb		PCI__BIT(21)	/* Internal PCI arbiter detec-
+						 * tion of a broken master. */
+#define PCI_IC_BIST		PCI__BIT(24)	/* PCI BIST Interrupt */
+#define PCI_IC_PMG		PCI__BIT(25)	/* PCI Power Management
+						 * Interrupt */
+#define PCI_IC_PRST		PCI__BIT(26)	/* PCI Reset Assert */
+
+/*
+31:27 Sel Specifies the error event currently being reported in the
+Error Address, Error Data, and Error Command registers.
+*/
+#define PCI_IC_SEL_GET(v)	PCI__EXT((v), 27, 5)
+#define PCI_IC_SEL_SAPerr	0x00
+#define PCI_IC_SEL_SWrPerr	0x01
+#define PCI_IC_SEL_SRdPerr	0x02
+#define PCI_IC_SEL_MAPerr	0x04
+#define PCI_IC_SEL_MWrPerr	0x05
+#define PCI_IC_SEL_MRdPerr	0x06
+#define PCI_IC_SEL_MMabort	0x08
+#define PCI_IC_SEL_MTabort	0x09
+#define PCI_IC_SEL_MMasterEn	0x0a
+#define PCI_IC_SEL_MRetry	0x0b
+#define PCI_IC_SEL_SMabort	0x10
+#define PCI_IC_SEL_STabort	0x11
+#define PCI_IC_SEL_SAccProt	0x12
+#define PCI_IC_SEL_SWrProt	0x13
+#define PCI_IC_SEL_SRdBuf	0x14
+#define PCI_IC_SEL_Arb		0x15
+#define PCI_IC_SEL_BIST		0x18
+#define PCI_IC_SEL_PMG		0x19
+#define PCI_IC_SEL_PRST		0x1a
+
+#define	PCI_IC_SEL_Strings { \
+	"SAPerr",  "SWrPerr", "SRdPerr",   "Rsvd#03", \
+	"MAPerr",  "MWrPerr", "MRdPerr",   "Rsvd#07", \
+	"MMabort", "MTabort", "MMasterEn", "MRetry", \
+	"Rsvd#0c", "Rsvd#0d", "Rsvd#0e",   "Rsvd#0f", \
+	"SMabort", "STabort", "SAccProt",  "SWrProt", \
+	"SRdBuf",  "Arb",     "Rsvd#16",   "Rsvd#17", \
+	"BIST",    "PMG",     "PRST",      "Rsvd#1b", \
+	"Rsvd#1c", "Rsvd#1d", "Rsvd#1e",   "Rsvd#1f" }
+
+/*
+ * Table 315: PCI Error Mask
+ * If the corresponding bit is 1, that interrupt is enabled
+ * Bits 3, 7, 12:15, 22:23, 27:31 are reserved.
+ */
+#define PCI_ERRMASK_SAPErr		PCI__BIT(0)
+#define PCI_ERRMASK_SWrPErr		PCI__BIT(1)
+#define PCI_ERRMASK_SRdPErr		PCI__BIT(2)
+#define PCI_ERRMASK_MAPErr		PCI__BIT(4)
+#define PCI_ERRMASK_MWRPErr		PCI__BIT(5)
+#define PCI_ERRMASK_MRDPErr		PCI__BIT(6)
+#define PCI_ERRMASK_MMAbort		PCI__BIT(8)
+#define PCI_ERRMASK_MTAbort		PCI__BIT(9)
+#define PCI_ERRMASK_MMasterEn		PCI__BIT(10)
+#define PCI_ERRMASK_MRetry		PCI__BIT(11)
+#define PCI_ERRMASK_SMAbort		PCI__BIT(16)
+#define PCI_ERRMASK_STAbort		PCI__BIT(17)
+#define PCI_ERRMASK_SAccProt		PCI__BIT(18)
+#define PCI_ERRMASK_SWrProt		PCI__BIT(19)
+#define PCI_ERRMASK_SRdBuf		PCI__BIT(20)
+#define PCI_ERRMASK_Arb			PCI__BIT(21)
+#define PCI_ERRMASK_BIST		PCI__BIT(24)
+#define PCI_ERRMASK_PMG			PCI__BIT(25)
+#define PCI_ERRMASK_PRST		PCI__BIT(26)
+
+#endif /* _DEV_GTPCIREG_H_ */
Index: bsps/powerpc/beatnik/include/bsp/gtreg.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/gtreg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/gtreg.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,854 @@
+/*	$NetBSD: gtreg.h,v 1.2 2005/02/27 00:27:21 perry Exp $	*/
+
+/*
+ * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
+ * All rights reserved.  *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Allegro Networks, Inc., and Wasabi Systems, Inc.
+ * 4. The name of Allegro Networks, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ * 5. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
+ * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DISCOVERY_DEV_GTREG_H_
+#define _DISCOVERY_DEV_GTREG_H_
+
+
+#define GT__BIT(bit)			(1U << (bit))
+#define GT__MASK(bit)			(GT__BIT(bit) - 1)
+#define	GT__EXT(data, bit, len)		(((data) >> (bit)) & GT__MASK(len))
+#define	GT__CLR(data, bit, len)		((data) &= ~(GT__MASK(len) << (bit)))
+#define	GT__INS(new, bit)		((new) << (bit))
+
+
+/*
+ * Table 30: CPU Address Decode Register Map
+ */
+#define GT_SCS0_Low_Decode		0x0008
+#define GT_SCS0_High_Decode		0x0010
+#define GT_SCS1_Low_Decode		0x0208
+#define GT_SCS1_High_Decode		0x0210
+#define GT_SCS2_Low_Decode		0x0018
+#define GT_SCS2_High_Decode		0x0020
+#define GT_SCS3_Low_Decode		0x0218
+#define GT_SCS3_High_Decode		0x0220
+#define GT_CS0_Low_Decode		0x0028
+#define GT_CS0_High_Decode		0x0030
+#define GT_CS1_Low_Decode		0x0228
+#define GT_CS1_High_Decode		0x0230
+#define GT_CS2_Low_Decode		0x0248
+#define GT_CS2_High_Decode		0x0250
+#define GT_CS3_Low_Decode		0x0038
+#define GT_CS3_High_Decode		0x0040
+#define GT_BootCS_Low_Decode		0x0238
+#define GT_BootCS_High_Decode		0x0240
+#define GT_PCI0_IO_Low_Decode		0x0048
+#define GT_PCI0_IO_High_Decode		0x0050
+#define GT_PCI0_Mem0_Low_Decode		0x0058
+#define GT_PCI0_Mem0_High_Decode	0x0060
+#define GT_PCI0_Mem1_Low_Decode		0x0080
+#define GT_PCI0_Mem1_High_Decode	0x0088
+#define GT_PCI0_Mem2_Low_Decode		0x0258
+#define GT_PCI0_Mem2_High_Decode	0x0260
+#define GT_PCI0_Mem3_Low_Decode		0x0280
+#define GT_PCI0_Mem3_High_Decode	0x0288
+#define GT_PCI1_IO_Low_Decode		0x0090
+#define GT_PCI1_IO_High_Decode		0x0098
+#define GT_PCI1_Mem0_Low_Decode		0x00a0
+#define GT_PCI1_Mem0_High_Decode	0x00a8
+#define GT_PCI1_Mem1_Low_Decode		0x00b0
+#define GT_PCI1_Mem1_High_Decode	0x00b8
+#define GT_PCI1_Mem2_Low_Decode		0x02a0
+#define GT_PCI1_Mem2_High_Decode	0x02a8
+#define GT_PCI1_Mem3_Low_Decode		0x02b0
+#define GT_PCI1_Mem3_High_Decode	0x02b8
+#define GT_Internal_Decode		0x0068
+#define GT_CPU0_Low_Decode		0x0290
+#define GT_CPU0_High_Decode		0x0298
+#define GT_CPU1_Low_Decode		0x02c0
+#define GT_CPU1_High_Decode		0x02c8
+/* ts, 2005/8: it seems that these are implicitely written
+ *             when setting the 'Low_Decode' regs...
+ */
+#define GT_PCI0_IO_Remap		0x00f0
+#define GT_PCI0_Mem0_Remap_Low		0x00f8
+#define GT_PCI0_Mem0_Remap_High		0x0320
+#define GT_PCI0_Mem1_Remap_Low		0x0100
+#define GT_PCI0_Mem1_Remap_High		0x0328
+#define GT_PCI0_Mem2_Remap_Low		0x02f8
+#define GT_PCI0_Mem2_Remap_High		0x0330
+#define GT_PCI0_Mem3_Remap_Low		0x0300
+#define GT_PCI0_Mem3_Remap_High		0x0338
+#define GT_PCI1_IO_Remap		0x0108
+#define GT_PCI1_Mem0_Remap_Low		0x0110
+#define GT_PCI1_Mem0_Remap_High		0x0340
+#define GT_PCI1_Mem1_Remap_Low		0x0118
+#define GT_PCI1_Mem1_Remap_High		0x0348
+#define GT_PCI1_Mem2_Remap_Low		0x0310
+#define GT_PCI1_Mem2_Remap_High		0x0350
+#define GT_PCI1_Mem3_Remap_Low		0x0318
+#define GT_PCI1_Mem3_Remap_High		0x0358
+
+
+/*
+ * Table 31: CPU Control Register Map
+ */
+#define GT_CPU_Cfg			0x0000
+#define GT_CPU_Mode			0x0120
+#define GT_CPU_Master_Ctl		0x0160
+#define GT_CPU_If_Xbar_Ctl_Low		0x0150
+#define GT_CPU_If_Xbar_Ctl_High		0x0158
+#define GT_CPU_If_Xbar_Timeout		0x0168
+#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_Low	0x0170
+#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_High	0x0178
+
+/*
+ * Table 32: CPU Sync Barrier Register Map
+ */
+#define	GT_260_PCI_Sync_Barrier(bus)	(0x00c0 | ((bus) << 3))
+#define GT_260_PCI0_Sync_Barrier		0x00c0
+#define GT_260_PCI1_Sync_Barrier		0x00c8
+
+/*
+ * Table 33: CPU Access Protection Register Map
+ */
+#define GT_Protect_Low_0		0x0180
+#define GT_Protect_High_0		0x0188
+#define GT_Protect_Low_1		0x0190
+#define GT_Protect_High_1		0x0198
+#define GT_Protect_Low_2		0x01a0
+#define GT_Protect_High_2		0x01a8
+#define GT_Protect_Low_3		0x01b0
+#define GT_Protect_High_3		0x01b8
+#define GT_260_Protect_Low_4		0x01c0
+#define GT_260_Protect_High_4		0x01c8
+#define GT_260_Protect_Low_5		0x01d0
+#define GT_260_Protect_High_5		0x01d8
+#define GT_260_Protect_Low_6		0x01e0
+#define GT_260_Protect_High_6		0x01e8
+#define GT_260_Protect_Low_7		0x01f0
+#define GT_260_Protect_High_7		0x01f8
+
+/*
+ * Table 34: Snoop Control Register Map
+ */
+#define GT_260_Snoop_Base_0			0x0380
+#define GT_260_Snoop_Top_0			0x0388
+#define GT_260_Snoop_Base_1			0x0390
+#define GT_260_Snoop_Top_1			0x0398
+#define GT_260_Snoop_Base_2			0x03a0
+#define GT_260_Snoop_Top_2			0x03a8
+#define GT_260_Snoop_Base_3			0x03b0
+#define GT_260_Snoop_Top_3			0x03b8
+
+/*
+ * Table 35: CPU Error Report Register Map
+ */
+#define GT_CPU_Error_Address_Low	0x0070
+#define GT_CPU_Error_Address_High	0x0078
+#define GT_CPU_Error_Data_Low		0x0128
+#define GT_CPU_Error_Data_High		0x0130
+#define GT_CPU_Error_Parity		0x0138
+#define GT_CPU_Error_Cause		0x0140
+#define GT_CPU_Error_Mask		0x0148
+
+#define	GT_DecodeAddr_SET(g, r, v)					\
+	do { 								\
+		gt_read((g), GT_Internal_Decode);			\
+		gt_write((g), (r), ((v) & 0xfff00000) >> 20);		\
+		while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20));	\
+	} while (0)
+
+#define	GT_LowAddr_GET(v)		 (GT__EXT((v), 0, 12) << 20)
+#define	GT_HighAddr_GET(v)		((GT__EXT((v), 0, 12) << 20) | 0xfffff)
+
+#define GT_MPP_Control0			0xf000
+#define GT_MPP_Control1			0xf004
+#define GT_MPP_Control2			0xf008
+#define GT_MPP_Control3			0xf00c
+
+#define	GT_GPP_IO_Control		0xf100
+#define	GT_GPP_Level_Control		0xf110
+#define GT_GPP_Value			0xf104
+#define	GT_GPP_Interrupt_Cause		0xf108
+#define GT_GPP_Interrupt_Mask		0xf10c
+/*
+ * Table 36: SCS[0]* Low Decode Address, Offset: 0x008
+ * Table 38: SCS[1]* Low Decode Address, Offset: 0x208
+ * Table 40: SCS[2]* Low Decode Address, Offset: 0x018
+ * Table 42: SCS[3]* Low Decode Address, Offset: 0x218
+ * Table 44: CS[0]*  Low Decode Address, Offset: 0x028
+ * Table 46: CS[1]*  Low Decode Address, Offset: 0x228
+ * Table 48: CS[2]*  Low Decode Address, Offset: 0x248
+ * Table 50: CS[3]*  Low Decode Address, Offset: 0x038
+ * Table 52: BootCS* Low Decode Address, Offset: 0x238
+ * Table 75: CPU 0   Low Decode Address, Offset: 0x290
+ * Table 77: CPU 1   Low Decode Address, Offset: 0x2c0
+ *
+ * 11:00 LowAddr		SCS[0] Base Address
+ * 31:12 Reserved		Must be 0.
+ */
+
+/*
+ * Table 37: SCS[0]* High Decode Address, Offset: 0x010
+ * Table 39: SCS[1]* High Decode Address, Offset: 0x210
+ * Table 41: SCS[2]* High Decode Address, Offset: 0x020
+ * Table 43: SCS[3]* High Decode Address, Offset: 0x220
+ * Table 45: CS[0]*  High Decode Address, Offset: 0x030
+ * Table 47: CS[1]*  High Decode Address, Offset: 0x230
+ * Table 49: CS[2]*  High Decode Address, Offset: 0x250
+ * Table 51: CS[3]*  High Decode Address, Offset: 0x040
+ * Table 53: BootCS* High Decode Address, Offset: 0x240
+ * Table 76: CPU 0   High Decode Address, Offset: 0x298
+ * Table 78: CPU 1   High Decode Address, Offset: 0x2c8
+ *
+ * 11:00 HighAddr		SCS[0] Top Address
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 54: PCI_0 I/O Low Decode Address,      Offset: 0x048
+ * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058
+ * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080
+ * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258
+ * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280
+ * Table 64: PCI_1 I/O Low Decode Address,      Offset: 0x090
+ * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0
+ * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0
+ * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0
+ * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0
+ *
+ * 11:00 LowAddr		PCI IO/Memory Space Base Address
+ * 23:12 Reserved
+ * 26:24 PCISwap		PCI Master Data Swap Control (0: Byte Swap;
+ *				1: No swapping; 2: Both byte and word swap;
+ *				3: Word swap; 4..7: Reserved)
+ * 27:27 PCIReq64		PCI master REQ64* policy (Relevant only when
+ *				configured to 64-bit PCI bus and not I/O)
+ *				0: Assert s REQ64* only when transaction
+ *				   is longer than 64-bits.
+ *				1: Always assert REQ64*.
+ * 31:28 Reserved
+ */
+#define	GT_PCISwap_GET(v)		GT__EXT((v), 24, 3)
+#define	GT_PCISwap_ByteSwap		0
+#define	GT_PCISwap_NoSwap		1
+#define	GT_PCISwap_ByteWordSwap		2
+#define	GT_PCISwap_WordSwap		3
+#define	GT_PCI_LowDecode_PCIReq64	GT__BIT(27)
+
+/*
+ * Table 55: PCI_0 I/O High Decode Address,      Offset: 0x050
+ * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060
+ * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088
+ * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260
+ * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288
+ * Table 65: PCI_1 I/O High Decode Address,      Offset: 0x098
+ * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8
+ * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8
+ * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8
+ * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8
+ *
+ * 11:00 HighAddr		PCI_0 I/O Space Top Address
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 74: Internal Space Decode, Offset: 0x068
+ * 15:00 IntDecode		GT64260 Internal Space Base Address
+ * 23:16 Reserved
+ * 26:24 PCISwap		Same as PCI_0 Memory 0 Low Decode Address.
+ *				NOTE: Reserved for Galileo Technology usage.
+ *				Relevant only for PCI master configuration
+ *				transactions on the PCI bus.
+ * 31:27 Reserved
+ */
+
+/*
+ * Table 79: PCI_0 I/O Address Remap,          Offset: 0x0f0
+ * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8
+ * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100
+ * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8
+ * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300
+ * Table 88: PCI_1 I/O Address Remap,          Offset: 0x108
+ * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110
+ * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118
+ * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310
+ * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318
+ *
+ * 11:00 Remap			PCI IO/Memory Space Address Remap (31:20)
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320
+ * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328
+ * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330
+ * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338
+ * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340
+ * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348
+ * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350
+ * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358
+ *
+ * 31:00 Remap			PCI Memory Address Remap (high 32 bits)
+ */
+
+/*
+ * Table 97: CPU Configuration, Offset: 0x000
+ * 07:00 NoMatchCnt		CPU Address Miss Counter
+ * 08:08 NoMatchCntEn		CPU Address Miss Counter Enable
+ *				NOTE: Relevant only if multi-GT is enabled.
+ *				(0: Disabled; 1: Enabled)
+ * 09:09 NoMatchCntExt		CPU address miss counter MSB
+ * 10:10 Reserved
+ * 11:11 AACKDelay		Address Acknowledge Delay
+ *				0: AACK* is asserted one cycle after TS*.
+ *				1: AACK* is asserted two cycles after TS*.
+ * 12:12 Endianess		Must be 0
+ *				NOTE: The GT64260 does not support the PowerPC
+ *				      Little Endian convention
+ * 13:13 Pipeline		Pipeline Enable
+ *				0: Disabled. The GT64260 will not respond with
+ *				   AACK* to a new CPU transaction, before the
+ *				   previous transaction data phase completes.
+ *				1: Enabled.
+ * 14:14 Reserved
+ * 15:15 TADelay		Transfer Acknowledge Delay
+ *				0: TA* is asserted one cycle after AACK*
+ *				1: TA* is asserted two cycles after AACK*
+ * 16:16 RdOOO			Read Out of Order Completion
+ *				0: Not Supported, Data is always returned in
+ *				   order (DTI[0-2] is always driven
+ *				1: Supported
+ * 17:17 StopRetry		Relevant only if PCI Retry is enabled
+ *				0: Keep Retry all PCI transactions targeted
+ *				   to the GT64260.
+ *				1: Stop Retry of PCI transactions.
+ * 18:18 MultiGTDec		Multi-GT Address Decode
+ *				0: Normal address decoding
+ *				1: Multi-GT address decoding
+ * 19:19 DPValid		CPU DP[0-7] Connection.  CPU write parity ...
+ *				0: is not checked. (Not connected)
+ *				1: is checked (Connected)
+ * 21:20 Reserved
+ * 22:22 PErrProp		Parity Error Propagation
+ *				0: GT64260 always drives good parity on
+ *				   DP[0-7] during CPU reads.
+ *				1: GT64260 drives bad parity on DP[0-7] in case
+ *				   the read response from the target interface
+ *				   comes with erroneous data indication
+ *				   (e.g. ECC error from SDRAM interface).
+ * 25:23 Reserved
+ * 26:26 APValid		CPU AP[0-3] Connection.  CPU address parity ...
+ *				0: is not checked. (Not connected)
+ *				1: is checked (Connected)
+ * 27:27 RemapWrDis		Address Remap Registers Write Control
+ *				0: Write to Low Address decode register.
+ *				   Results in writing of the corresponding
+ *				   Remap register.
+ *				1: Write to Low Address decode register.  No
+ *				   affect on the corresponding Remap register.
+ * 28:28 ConfSBDis		Configuration Read Sync Barrier Disable
+ *				0: enabled; 1: disabled
+ * 29:29 IOSBDis		I/O Read Sync Barrier Disable
+ *				0: enabled; 1: disabled
+ * 30:30 ClkSync		Clocks Synchronization
+ *				0: The CPU interface is running with SysClk,
+ *				   which is asynchronous to TClk.
+ *				1: The CPU interface is running with TClk.
+ * 31:31 Reserved
+ */
+#define	GT_CPUCfg_NoMatchCnt_GET(v)	GT__EXT((v), 0, 8)
+#define	GT_CPUCfg_NoMatchCntEn		GT__BIT( 9)
+#define	GT_CPUCfg_NoMatchCntExt		GT__BIT(10)
+#define	GT_CPUCfg_AACKDelay		GT__BIT(11)
+#define	GT_CPUCfg_Endianess		GT__BIT(12)
+#define	GT_CPUCfg_Pipeline		GT__BIT(13)
+#define	GT_CPUCfg_TADelay		GT__BIT(15)
+#define	GT_CPUCfg_RdOOO			GT__BIT(16)
+#define	GT_CPUCfg_StopRetry		GT__BIT(17)
+#define	GT_CPUCfg_MultiGTDec		GT__BIT(18)
+#define	GT_CPUCfg_DPValid		GT__BIT(19)
+#define	GT_CPUCfg_PErrProp		GT__BIT(22)
+#define	GT_CPUCfg_APValid		GT__BIT(26)
+#define	GT_CPUCfg_RemapWrDis		GT__BIT(27)
+#define	GT_CPUCfg_ConfSBDis		GT__BIT(28)
+#define	GT_CPUCfg_IOSBDis		GT__BIT(29)
+#define	GT_CPUCfg_ClkSync		GT__BIT(30)
+
+/*
+ * Table 98: CPU Mode, Offset: 0x120, Read only
+ * 01:00 MultiGTID		Multi-GT ID
+ *				Represents the ID to which the GT64260 responds
+ *				to during a multi-GT address decoding period.
+ * 02:02 MultiGT		(0: Single; 1: Multiple) GT configuration
+ * 03:03 RetryEn		(0: Don't; 1: Do) Retry PCI transactions
+ * 07:04 CPUType
+ *				0x0-0x3: Reserved
+ *				0x4:     64-bit PowerPC CPU, 60x bus
+ *				0x5:     64-bit PowerPC CPU, MPX bus
+ *				0x6-0xf: Reserved
+ * 31:08 Reserved
+ */
+#define	GT_CPUMode_MultiGTID_GET(v)	GT__EXT(v, 0, 2)
+#define GT_CPUMode_MultiGT		GT__BIT(2)
+#define GT_CPUMode_RetryEn		GT__BIT(3)
+#define	GT_CPUMode_CPUType_GET(v)	GT__EXT(v, 4, 4)
+
+/*
+ * Table 99: CPU Master Control, Offset: 0x160
+ * 07:00 Reserved
+ * 08:08 IntArb			CPU Bus Internal Arbiter Enable
+ *				NOTE: Only relevant to 60x bus mode. When
+ *				      running MPX bus, the GT64260 internal
+ *				      arbiter must be used.
+ *				0: Disabled.  External arbiter is required.
+ *				1: Enabled.  Use the GT64260 CPU bus arbiter.
+ * 09:09 IntBusCtl		CPU Interface Unit Internal Bus Control
+ *				NOTE: This bit must be set to 1. It is reserved
+ *				      for Galileo Technology usage.
+ *				0: Enable internal bus sharing between master
+ *				   and slave interfaces.
+ *				1: Disable internal bus sharing between master
+ *				   and slave interfaces.
+ * 10:10 MWrTrig		Master Write Transaction Trigger
+ *				0: With first valid write data
+ *				1: With last valid write data
+ * 11:11 MRdTrig		Master Read Response Trigger
+ *				0: With first valid read data
+ *				1: With last valid read data
+ * 12:12 CleanBlock		Clean Block Snoop Transaction Support
+ *				0: CPU does not support clean block (603e,750)
+ *				1: CPU supports clean block (604e,G4)
+ * 13:13 FlushBlock		Flush Block Snoop Transaction Support
+ *				0: CPU does not support flush block (603e,750)
+ *				1: CPU supports flush block (604e,G4)
+ * 31:14 Reserved
+ */
+#define GT_CPUMstrCtl_IntArb			GT__BIT(8)
+#define GT_CPUMstrCtl_IntBusCtl			GT__BIT(9)
+#define GT_CPUMstrCtl_MWrTrig			GT__BIT(10)
+#define GT_CPUMstrCtl_MRdTrig			GT__BIT(11)
+#define GT_CPUMstrCtl_CleanBlock		GT__BIT(12)
+#define GT_CPUMstrCtl_FlushBlock		GT__BIT(13)
+
+#define	GT_ArbSlice_SDRAM	0x0	/* SDRAM interface snoop request */
+#define GT_ArbSlice_DEVICE	0x1	/* Device request */
+#define GT_ArbSlice_NULL	0x2	/* NULL request */
+#define GT_ArbSlice_PCI0	0x3	/* PCI_0 access */
+#define GT_ArbSlice_PCI1	0x4	/* PCI_1 access */
+#define GT_ArbSlice_COMM	0x5	/* Comm unit access */
+#define GT_ArbSlice_IDMA0123	0x6	/* IDMA channels 0/1/2/3 access */
+#define GT_ArbSlice_IDMA4567	0x7	/* IDMA channels 4/5/6/7 access */
+					/* 0x8-0xf: Reserved */
+
+/* Pass in the slice number (from 0..16) as 'n'
+ */
+#define	GT_XbarCtl_GET_ArbSlice(v, n)		GT__EXT((v), (((n) & 7)*4, 4)
+
+/*
+ * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150
+ * 03:00 Arb0			Slice  0 of CPU Master pizza Arbiter
+ * 07:04 Arb1			Slice  1 of CPU Master pizza Arbiter
+ * 11:08 Arb2			Slice  2 of CPU Master pizza Arbiter
+ * 15:12 Arb3			Slice  3 of CPU Master pizza Arbiter
+ * 19:16 Arb4			Slice  4 of CPU Master pizza Arbiter
+ * 23:20 Arb5			Slice  5 of CPU Master pizza Arbiter
+ * 27:24 Arb6			Slice  6 of CPU Master pizza Arbiter
+ * 31:28 Arb7			Slice  7 of CPU Master pizza Arbiter
+ */
+
+/*
+ * Table 101: CPU Interface Crossbar Control High, Offset: 0x158
+ * 03:00 Arb8			Slice  8 of CPU Master pizza Arbiter
+ * 07:04 Arb9			Slice  9 of CPU Master pizza Arbiter
+ * 11:08 Arb10			Slice 10 of CPU Master pizza Arbiter
+ * 15:12 Arb11			Slice 11 of CPU Master pizza Arbiter
+ * 19:16 Arb12			Slice 12 of CPU Master pizza Arbiter
+ * 23:20 Arb13			Slice 13 of CPU Master pizza Arbiter
+ * 27:24 Arb14			Slice 14 of CPU Master pizza Arbiter
+ * 31:28 Arb15			Slice 15 of CPU Master pizza Arbiter
+ */
+
+/*
+ * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168
+ * NOTE: Reserved for Galileo Technology usage.
+ * 07:00 Timeout		Crossbar Arbiter Timeout Preset Value
+ * 15:08 Reserved
+ * 16:16 TimeoutEn		Crossbar Arbiter Timer Enable
+ *				(0: Enable; 1: Disable)
+ * 31:17 Reserved
+ */
+
+/*
+ * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170
+ * 03:00 Arb0			Slice  0 of CPU Slave pizza Arbiter
+ * 07:04 Arb1			Slice  1 of CPU Slave pizza Arbiter
+ * 11:08 Arb2			Slice  2 of CPU Slave pizza Arbiter
+ * 15:12 Arb3			Slice  3 of CPU Slave pizza Arbiter
+ * 19:16 Arb4			Slice  4 of CPU Slave pizza Arbiter
+ * 23:20 Arb5			Slice  5 of CPU Slave pizza Arbiter
+ * 27:24 Arb6			Slice  6 of CPU Slave pizza Arbiter
+ * 31:28 Arb7			Slice  7 of CPU Slave pizza Arbiter
+ */
+/*
+ * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178
+ * 03:00 Arb8			Slice  8 of CPU Slave pizza Arbiter
+ * 07:04 Arb9			Slice  9 of CPU Slave pizza Arbiter
+ * 11:08 Arb10			Slice 10 of CPU Slave pizza Arbiter
+ * 15:12 Arb11			Slice 11 of CPU Slave pizza Arbiter
+ * 19:16 Arb12			Slice 12 of CPU Slave pizza Arbiter
+ * 23:20 Arb13			Slice 13 of CPU Slave pizza Arbiter
+ * 27:24 Arb14			Slice 14 of CPU Slave pizza Arbiter
+ * 31:28 Arb15			Slice 15 of CPU Slave pizza Arbiter
+ */
+
+/*
+ * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0
+ * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8
+ *   NOTE: The read data is random and should be ignored.
+ * 31:00 SyncBarrier		A CPU read from this register creates a
+ *				synchronization barrier cycle.
+ */
+
+/*
+ * Table 107: CPU Protect Address 0 Low, Offset: 0x180
+ * Table 109: CPU Protect Address 1 Low, Offset: 0x190
+ * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0
+ * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0
+ * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0
+ * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0
+ * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0
+ * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0
+ *
+ * 11:00 LowAddr		CPU Protect Region Base Address
+ *				Corresponds to address bits[31:20].
+ * 15:12 Reserved.		Must be 0
+ * 16:16 AccProtect		CPU Access Protect
+ *				Access is (0: allowed; 1: forbidden)
+ * 17:17 WrProtect		CPU Write Protect
+ *				Writes are (0: allowed; 1: forbidden)
+ * 18:18 CacheProtect		CPU caching protect. 	Caching (block read)
+ *				is (0: allowed; 1: forbidden)
+ * 31:19 Reserved
+ */
+#define GT_CPU_AccProtect			GT__BIT(16)
+#define GT_CPU_WrProtect			GT__BIT(17)
+#define GT_CPU_CacheProtect			GT__BIT(18)
+
+/*
+ * Table 108: CPU Protect Address 0 High, Offset: 0x188
+ * Table 110: CPU Protect Address 1 High, Offset: 0x198
+ * Table 112: CPU Protect Address 2 High, Offset: 0x1a8
+ * Table 114: CPU Protect Address 3 High, Offset: 0x1b8
+ * Table 116: CPU Protect Address 4 High, Offset: 0x1c8
+ * Table 118: CPU Protect Address 5 High, Offset: 0x1d8
+ * Table 120: CPU Protect Address 6 High, Offset: 0x1e8
+ * Table 122: CPU Protect Address 7 High, Offset: 0x1f8
+ *
+ * 11:00 HighAddr		CPU Protect Region Top Address
+ *				Corresponds to address bits[31:20]
+ * 31:12 Reserved
+ */
+
+/*
+ * Table 123: Snoop Base Address 0, Offset: 0x380
+ * Table 125: Snoop Base Address 1, Offset: 0x390
+ * Table 127: Snoop Base Address 2, Offset: 0x3a0
+ * Table 129: Snoop Base Address 3, Offset: 0x3b0
+ *
+ * 11:00 LowAddr		Snoop Region Base Address [31:20]
+ * 15:12 Reserved		Must be 0.
+ * 17:16 Snoop			Snoop Type
+ *				0x0: No Snoop
+ *				0x1: Snoop to WT region
+ *				0x2: Snoop to WB region
+ *				0x3: Reserved
+ * 31:18 Reserved
+ */
+#define GT_Snoop_GET(v)				GT__EXT((v), 16, 2)
+#define GT_Snoop_INS(v)				GT__INS((v), 16)
+#define	GT_Snoop_None				0
+#define	GT_Snoop_WT				1
+#define	GT_Snoop_WB				2
+
+
+/*
+ * Table 124: Snoop Top Address 0, Offset: 0x388
+ * Table 126: Snoop Top Address 1, Offset: 0x398
+ * Table 128: Snoop Top Address 2, Offset: 0x3a8
+ * Table 130: Snoop Top Address 3, Offset: 0x3b8
+ * 11:00 HighAddr		Snoop Region Top Address [31:20]
+ * 31:12 Reserved
+ */
+
+
+/*
+ * Table 131: CPU Error Address Low, Offset: 0x070, Read Only.
+ *   In case of multiple errors, only the first one is latched.  New error
+ *   report latching is enabled only after the CPU Error Address Low register
+ *   is being read.
+ * 31:00 ErrAddr		Latched address bits [31:0] of a CPU
+ *				transaction in case of:
+ *				o illegal address (failed address decoding)
+ *				o access protection violation
+ *				o bad data parity
+ *				o bad address parity
+ *				Upon address latch, no new address are
+ *				registered (due to additional error condition),
+ *				until the register is being read.
+ */
+
+/*
+ * Table 132: CPU Error Address High, Offset: 0x078, Read Only.
+ *   Once data is latched, no new data can be registered (due to additional
+ *   error condition), until CPU Error Low Address is being read (which
+ *   implies, it should be the last being read by the interrupt handler).
+ * 03:00 Reserved
+ * 07:04 ErrPar			Latched address parity bits in case
+ *				of bad CPU address parity detection.
+ * 31:08 Reserved
+ */
+#define	GT_CPUErrorAddrHigh_ErrPar_GET(v)	GT__EXT((v), 4, 4)
+
+/*
+ * Table 133: CPU Error Data Low, Offset: 0x128, Read only.
+ * 31:00 PErrData		Latched data bits [31:0] in case of bad data
+ *				parity sampled on write transactions or on
+ *				master read transactions.
+ */
+
+/*
+ * Table 134: CPU Error Data High, Offset: 0x130, Read only.
+ * 31:00 PErrData		Latched data bits [63:32] in case of bad data
+ *				parity sampled on write transactions or on
+ *				master read transactions.
+ */
+
+/*
+ * Table 135: CPU Error Parity, Offset: 0x138, Read only.
+ * 07:00 PErrPar		Latched data parity bus in case of bad data
+ *				parity sampled on write transactions or on
+ *				master read transactions.
+ * 31:10 Reserved
+ */
+#define	GT_CPUErrorParity_PErrPar_GET(v)	GT__EXT((v), 0, 8)
+
+/*
+ * Table 136: CPU Error Cause, Offset: 0x140
+ *   Bits[7:0] are clear only. A cause bit is set upon an error condition
+ *   occurrence. Write a 0 value to clear the bit.  Writing a 1 value has
+ *   no affect.
+ * 00:00 AddrOut		CPU Address Out of Range
+ * 01:01 AddrPErr		Bad Address Parity Detected
+ * 02:02 TTErr			Transfer Type Violation.
+ *				The CPU attempts to burst (read or write) to an
+ *				internal register.
+ * 03:03 AccErr			Access to a Protected Region
+ * 04:04 WrErr			Write to a Write Protected Region
+ * 05:05 CacheErr		Read from a Caching protected region
+ * 06:06 WrDataPErr		Bad Write Data Parity Detected
+ * 07:07 RdDataPErr		Bad Read Data Parity Detected
+ * 26:08 Reserved
+ * 31:27 Sel			Specifies the error event currently being
+ *				reported in Error Address, Error Data, and
+ *				Error Parity registers.
+ *				0x0: AddrOut
+ *				0x1: AddrPErr
+ *				0x2: TTErr
+ *				0x3: AccErr
+ *				0x4: WrErr
+ *				0x5: CacheErr
+ *				0x6: WrDataPErr
+ *				0x7: RdDataPErr
+ *				0x8-0x1f: Reserved
+ */
+#define GT_CPUError_AddrOut		GT__BIT(GT_CPUError_Sel_AddrOut)
+#define GT_CPUError_AddrPErr		GT__BIT(GT_CPUError_Sel_AddrPErr)
+#define GT_CPUError_TTErr		GT__BIT(GT_CPUError_Sel_TTErr)
+#define GT_CPUError_AccErr		GT__BIT(GT_CPUError_Sel_AccErr)
+#define GT_CPUError_WrErr		GT__BIT(GT_CPUError_Sel_WrPErr)
+#define GT_CPUError_CacheErr		GT__BIT(GT_CPUError_Sel_CachePErr)
+#define GT_CPUError_WrDataPErr		GT__BIT(GT_CPUError_Sel_WrDataPErr)
+#define GT_CPUError_RdDataPErr		GT__BIT(GT_CPUError_Sel_RdDataPErr)
+
+#define GT_CPUError_Sel_AddrOut		0
+#define GT_CPUError_Sel_AddrPErr	1
+#define GT_CPUError_Sel_TTErr		2
+#define GT_CPUError_Sel_AccErr		3
+#define GT_CPUError_Sel_WrErr		4
+#define GT_CPUError_Sel_CacheErr	5
+#define GT_CPUError_Sel_WrDataPErr	6
+#define GT_CPUError_Sel_RdDataPErr	7
+
+#define	GT_CPUError_Sel_GET(v)		GT__EXT((v), 27, 5)
+
+/*
+ * Table 137: CPU Error Mask, Offset: 0x148
+ * 00:00 AddrOut		If set to 1, enables AddrOut interrupt.
+ * 01:01 AddrPErr		If set to 1, enables AddrPErr interrupt.
+ * 02:02 TTErr			If set to 1, enables TTErr interrupt.
+ * 03:03 AccErr			If set to 1, enables AccErr interrupt.
+ * 04:04 WrErr			If set to 1, enables WrErr interrupt.
+ * 05:05 CacheErr		If set to 1, enables CacheErr interrupt.
+ * 06:06 WrDataPErr		If set to 1, enables WrDataPErr interrupt.
+ * 07:07 RdDataPErr		If set to 1, enables RdDataPErr interrupt.
+ * 31:08 Reserved
+ */
+
+/*
+ * Comm Unit Interrupt registers
+ */
+
+/* Comm Unit Arbiter Control */
+#define GT_CommUnitArb_Ctrl     0xf300
+/* GPP IRQs level vs. edge sensitivity */
+#define GT_CommUnitArb_Ctrl_GPP_Ints_Level_Sensitive	(1<<10)
+
+#define GT_CommUnitIntr_Cause	0xf310
+#define GT_CommUnitIntr_Mask	0xf314
+#define GT_CommUnitIntr_ErrAddr	0xf318
+
+#define GT_CommUnitIntr_E0	0x00000007
+#define GT_CommUnitIntr_E1	0x00000070
+#define GT_CommUnitIntr_E2	0x00000700
+#define GT_CommUnitIntr_S0	0x00070000
+#define GT_CommUnitIntr_S1	0x00700000
+#define GT_CommUnitIntr_Sel	0x70000000
+
+/*
+ * SDRAM Error Report (ECC) Registers
+ */
+#define GT_260_ECC_Data_Lo		0x484	/* latched Error Data (low) */
+#define GT_260_ECC_Data_Hi		0x480	/* latched Error Data (high) */
+#define GT_260_ECC_Addr		0x490	/* latched Error Address */
+#define GT_260_ECC_Rec		0x488	/* latched ECC code from SDRAM */
+#define GT_260_ECC_Calc		0x48c	/* latched ECC code from SDRAM */
+#define GT_260_ECC_Ctl		0x494	/* ECC Control */
+#define GT_260_ECC_Count		0x498	/* ECC 1-bit error count */
+
+/* Timer/Counter Registers (t. straumann)
+ */
+#define GT_TIMER_0			0x0850		/* preset / running value  */
+#define GT_TIMER_1			0x0854
+#define GT_TIMER_2			0x0858
+#define GT_TIMER_3			0x085c
+
+#define GT_TIMER_0_3_Ctl		0x0864
+
+#define GT_TIMER_0_Ctl_Enb		0x00000001	/* enable timer 			*/
+#define GT_TIMER_0_Ctl_Rld		0x00000002	/* reload after expiration	*/
+#define GT_TIMER_1_Ctl_Enb		0x00000100	/* enable timer 			*/
+#define GT_TIMER_1_Ctl_Rld		0x00000200	/* reload after expiration	*/
+#define GT_TIMER_2_Ctl_Enb		0x00010000	/* enable timer 			*/
+#define GT_TIMER_2_Ctl_Rld		0x00020000	/* reload after expiration	*/
+#define GT_TIMER_3_Ctl_Enb		0x01000000	/* enable timer 			*/
+#define GT_TIMER_3_Ctl_Rld		0x02000000	/* reload after expiration	*/
+
+#define GT_TIMER_0_3_Intr_Cse	0x0868
+#define GT_TIMER_0_Intr			0x00000001
+#define GT_TIMER_1_Intr			0x00000002
+#define GT_TIMER_2_Intr			0x00000004
+#define GT_TIMER_3_Intr			0x00000008
+#define GT_TIMER_Intr_Smry		0x80000000	/* Interrupt Summary        */
+
+#define GT_TIMER_0_3_Intr_Msk	0x086c
+
+/*
+ * Watchdog Registers
+ */
+#define GT_WDOG_Config		0xb410
+#define GT_WDOG_Value		0xb414
+#define GT_WDOG_Value_NMI	GT__MASK(24)
+#define GT_WDOG_Config_Preset	GT__MASK(24)
+#define GT_WDOG_Config_Ctl1a	GT__BIT(24)
+#define GT_WDOG_Config_Ctl1b	GT__BIT(25)
+#define GT_WDOG_Config_Ctl2a	GT__BIT(26)
+#define GT_WDOG_Config_Ctl2b	GT__BIT(27)
+#define GT_WDOG_Config_Enb	GT__BIT(31)
+
+#define GT_WDOG_NMI_DFLT	(GT__MASK(24) & GT_WDOG_Value_NMI)
+#define GT_WDOG_Preset_DFLT	(GT__MASK(22) & GT_WDOG_Config_Preset)
+
+/*
+ * Device Bus Interrupts
+ */
+#define GT_DEVBUS_ICAUSE	0x4d0	/* Device Interrupt Cause */
+#define GT_DEVBUS_IMASK		0x4d4	/* Device Interrupt Mask */
+#define GT_DEVBUS_ERR_ADDR	0x4d8	/* Device Error Address */
+
+/*
+ * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK
+ */
+#define GT_DEVBUS_DBurstErr	GT__BIT(0)
+#define GT_DEVBUS_DRdyErr	GT__BIT(1)
+#define GT_DEVBUS_Sel		GT__BIT(27)
+#define GT_DEVBUS_RES	~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel)
+
+/* MV64360 */
+/* Enable individual CPU windows by *clearing* respective bits
+ * in MV_64360_BASE_ADDR_DISBL
+ *
+ * Bit ordering is:
+ *
+ *    SDRAM_CS_0..3			(1<<0..3)
+ *      DEV_CS_0..3			(1<<4..7)
+ *     BOOT_CS_0..3			(1<<8)
+ *      PCI_0_IO			(1<<9)
+ *   PCI_0_MEM_0..3			(1<<10..13)
+ *      PCI_1_IO			(1<<14)
+ *   PCI_1_MEM_0..3			(1<<15..18)
+ * INTERNAL_SRAM			(1<<19)
+ *  MV64x60_REGS			(1<<20)
+ */
+#define MV_64360_BASE_ADDR_DISBL (0x278)
+
+/* Internal SRAM */
+#define MV_64360_SRAM_BASE	(0x268)
+#define MV_64360_SRAM_CTRL	(0x380)
+/* Control register bits */
+#define MV_64360_SRAM_CacheWb	GT__BIT(1)
+/* default setup used by linux, motload (uses 90 instead of b0), ...
+ * Comments say:
+ *   - parity enabled,
+ *   - parity error propagation
+ *   - arbitration not parked for CPU only
+ *   - other bits are reserved
+ */
+#define MV_64360_SRAM_Ctl_Setup (0x001600b0)
+
+#define MV_64360_SRAM_TEST_MODE			(0x3f4)
+#define MV_64340_SRAM_ERR_CAUSE			(0x388)
+#define MV_64340_SRAM_ERR_ADDR			(0x390)
+#define MV_64340_SRAM_ERR_ADDR_HI		(0X3f8)
+#define MV_64340_SRAM_ERR_DATA_LO		(0x398)
+#define MV_64340_SRAM_ERR_DATA_HI		(0x3a0)
+#define MV_64340_SRAM_ERR_DATA_PARITY	(0x3a8)
+
+#endif /* !_DISCOVERY_DEV_GTREG_H */
Index: bsps/powerpc/beatnik/include/bsp/if_em_pub.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/if_em_pub.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/if_em_pub.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,22 @@
+#ifndef RTEMS_BSDNET_IF_EM_PUBLIC_SYMBOLS_H
+#define RTEMS_BSDNET_IF_EM_PUBLIC_SYMBOLS_H
+
+#include <rtems.h>
+#include <rtems/rtems_bsdnet.h>
+#include <bsp/early_enet_link_status.h>
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+extern int                               rtems_em_attach(struct rtems_bsdnet_ifconfig *, int);
+extern int                               rtems_em_pci_setup(int);
+extern rtems_bsdnet_early_link_check_ops rtems_em_early_link_check_ops;
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
+
+
Index: bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,30 @@
+#ifndef RTEMS_BSDNET_IF_GFE_PUBLIC_SYMBOLS_H
+#define RTEMS_BSDNET_IF_GFE_PUBLIC_SYMBOLS_H
+
+#include <rtems.h>
+#include <rtems/rtems_bsdnet.h>
+#include <bsp/early_enet_link_status.h>
+#include <net/ethernet.h>
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+extern int
+rtems_gfe_attach(struct rtems_bsdnet_ifconfig *, int);
+
+
+/* enet_addr must be 6 bytes long */
+int
+rtems_gfe_setup(int unit, char *enet_addr, uint32_t base_addr);
+
+extern rtems_bsdnet_early_link_check_ops
+rtems_gfe_early_link_check_ops;
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
+
+
Index: bsps/powerpc/beatnik/include/bsp/if_mve_pub.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/if_mve_pub.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/if_mve_pub.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,422 @@
+#ifndef RTEMS_BSDNET_IF_MVE_PUBLIC_SYMBOLS_H
+#define RTEMS_BSDNET_IF_MVE_PUBLIC_SYMBOLS_H
+
+/* 
+ * Authorship
+ * ----------
+ * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
+ *     created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
+ * 	   Stanford Linear Accelerator Center, Stanford University.
+ * 
+ * Acknowledgement of sponsorship
+ * ------------------------------
+ * The 'beatnik' BSP was produced by
+ *     the Stanford Linear Accelerator Center, Stanford University,
+ * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
+ * 
+ * Government disclaimer of liability
+ * ----------------------------------
+ * Neither the United States nor the United States Department of Energy,
+ * nor any of their employees, makes any warranty, express or implied, or
+ * assumes any legal liability or responsibility for the accuracy,
+ * completeness, or usefulness of any data, apparatus, product, or process
+ * disclosed, or represents that its use would not infringe privately owned
+ * rights.
+ * 
+ * Stanford disclaimer of liability
+ * --------------------------------
+ * Stanford University makes no representations or warranties, express or
+ * implied, nor assumes any liability for the use of this software.
+ * 
+ * Stanford disclaimer of copyright
+ * --------------------------------
+ * Stanford University, owner of the copyright, hereby disclaims its
+ * copyright and all other rights in this software.  Hence, anyone may
+ * freely use it for any purpose without restriction.  
+ * 
+ * Maintenance of notices
+ * ----------------------
+ * In the interest of clarity regarding the origin and status of this
+ * SLAC software, this and all the preceding Stanford University notices
+ * are to remain affixed to any copy or derivative of this software made
+ * or distributed by the recipient and are to be affixed to any copy of
+ * software made or distributed by the recipient that contains a copy or
+ * derivative of this software.
+ * 
+ * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
+ */ 
+#include <rtems.h>
+#include <rtems/rtems_bsdnet.h>
+#include <bsp/early_enet_link_status.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+extern int                               rtems_mve_attach(struct rtems_bsdnet_ifconfig *, int);
+extern rtems_bsdnet_early_link_check_ops rtems_mve_early_link_check_ops;
+
+/* Low-level Driver API.
+ * This provides driver access to applications that want to use e.g., the second
+ * ethernet interface w/o running the BSD TCP/IP stack.
+ */
+
+/* Opaque handle */
+struct mveth_private;
+
+/* Direct assignment of MVE flags to user API relies on irqs and x-irqs not overlapping */
+#define BSP_MVE_IRQ_RX		(1<<2)
+#define BSP_MVE_IRQ_TX		(1<<0)
+#define BSP_MVE_IRQ_LINK	(1<<16)
+
+/* Setup an interface.
+ * Allocates resources for descriptor rings and sets up the driver software structure.
+ *
+ * Arguments:
+ *	unit:
+ *		interface # (1..2). The interface must not be attached to BSD.
+ *
+ *  driver_tid:
+ *		ISR posts RTEMS event # ('unit' - 1) to task with ID 'driver_tid' and disables interrupts
+ *		from this interface.
+ *
+ *	void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred):
+ *		Pointer to user-supplied callback to release a buffer that had been sent
+ *		by BSP_mve_send_buf() earlier. The callback is passed 'cleanup_txbuf_arg'
+ *		and a flag indicating whether the send had been successful.
+ *		The driver no longer accesses 'user_buf' after invoking this callback.
+ *		CONTEXT: This callback is executed either by BSP_mve_swipe_tx() or 
+ *		BSP_mve_send_buf(), BSP_mve_init_hw(), BSP_mve_stop_hw() (the latter 
+ *		ones calling BSP_mve_swipe_tx()).
+ *	void *cleanup_txbuf_arg:
+ *		Closure argument that is passed on to 'cleanup_txbuf()' callback;
+ *
+ *	void *(*alloc_rxbuf)(int *p_size, unsigned long *p_data_addr),
+ *		Pointer to user-supplied callback to allocate a buffer for subsequent
+ *		insertion into the RX ring by the driver.
+ *		RETURNS: opaque handle to the buffer (which may be a more complex object
+ *				 such as an 'mbuf'). The handle is not used by the driver directly
+ *				 but passed back to the 'consume_rxbuf()' callback.
+ *				 Size of the available data area and pointer to buffer's data area
+ *				 in '*psize' and '*p_data_area', respectively.
+ *				 If no buffer is available, this routine should return NULL in which
+ *				 case the driver drops the last packet and re-uses the last buffer
+ *				 instead of handing it out to 'consume_rxbuf()'.
+ *		CONTEXT: Called when initializing the RX ring (BSP_mve_init_hw()) or when
+ *				 swiping it (BSP_mve_swipe_rx()).
+ *		
+ *
+ *	void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len);
+ *		Pointer to user-supplied callback to pass a received buffer back to
+ *		the user. The driver no longer accesses the buffer after invoking this
+ *		callback (with 'len'>0, see below). 'user_buf' is the buffer handle
+ *		previously generated by 'alloc_rxbuf()'.
+ *		The callback is passed 'cleanup_rxbuf_arg' and a 'len'
+ *		argument giving the number of bytes that were received.
+ *		'len' may be <=0 in which case the 'user_buf' argument is NULL.
+ *		'len' == 0 means that the last 'alloc_rxbuf()' had failed,
+ *		'len' < 0 indicates a receiver error. In both cases, the last packet
+ *		was dropped/missed and the last buffer will be re-used by the driver.
+ *		NOTE: the data are 'prefixed' with two bytes, i.e., the ethernet packet header
+ *		      is stored at offset 2 in the buffer's data area. Also, the FCS (4 bytes)
+ *		      is appended. 'len' accounts for both.
+ *		CONTEXT: Called from BSP_mve_swipe_rx().
+ *	void *cleanup_rxbuf_arg:
+ *		Closure argument that is passed on to 'consume_rxbuf()' callback;
+ *
+ *  rx_ring_size, tx_ring_size:
+ *		How many big to make the RX and TX descriptor rings. Note that the sizes
+ *		may be 0 in which case a reasonable default will be used.
+ *		If either ring size is < 0 then the RX or TX will be disabled.
+ *		Note that it is illegal in this case to use BSP_mve_swipe_rx() or
+ *		BSP_mve_swipe_tx(), respectively.
+ *
+ *  irq_mask:
+ *		Interrupts to enable. OR of flags from above.
+ *
+ */
+struct mveth_private *
+BSP_mve_setup(
+	int		 unit,
+	rtems_id driver_tid,
+	void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), 
+	void *cleanup_txbuf_arg,
+	void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr),
+	void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len),
+	void *consume_rxbuf_arg,
+	int		rx_ring_size,
+	int		tx_ring_size,
+	int		irq_mask
+);
+
+/*
+ * Alternate 'setup' routine allowing the user to install an ISR rather
+ * than a task ID.
+ * All parameters (other than 'isr' / 'isr_arg') and the return value
+ * are identical to the BSP_mve_setup() entry point.
+ */
+struct mveth_private *
+BSP_mve_setup_1(
+	int		 unit,
+	void     (*isr)(void *isr_arg),
+	void     *isr_arg,
+	void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), 
+	void *cleanup_txbuf_arg,
+	void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr),
+	void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len),
+	void *consume_rxbuf_arg,
+	int		rx_ring_size,
+	int		tx_ring_size,
+	int		irq_mask
+);
+
+
+/*
+ * Initialize interface hardware
+ *
+ * 'mp'			handle obtained by from BSP_mve_setup(). 
+ * 'promisc'	whether to set promiscuous flag.
+ * 'enaddr'		pointer to six bytes with MAC address. Read
+ *				from the device if NULL.
+ *
+ * Note:        Multicast filters are cleared by this routine.
+ *              However, in promiscuous mode the mcast filters
+ *              are programmed to accept all multicast frames.
+ */
+void
+BSP_mve_init_hw(struct mveth_private *mp, int promisc, unsigned char *enaddr);
+
+/*
+ * Clear multicast hash filter. No multicast frames are accepted
+ * after executing this routine (unless the hardware was initialized
+ * in 'promiscuous' mode).
+ */
+void
+BSP_mve_mcast_filter_clear(struct mveth_private *mp);
+
+/*
+ * Program multicast filter to accept all multicast frames
+ */
+void
+BSP_mve_mcast_filter_accept_all(struct mveth_private *mp);
+
+/*
+ * Add a MAC address to the multicast filter.
+ * Existing entries are not changed but note that
+ * the filter is imperfect, i.e., multiple MAC addresses
+ * may alias to a single filter entry. Hence software
+ * filtering must still be performed.
+ *
+ * If a higher-level driver implements IP multicasting
+ * then multiple IP addresses may alias to the same MAC
+ * address. This driver maintains a 'reference-count'
+ * which is incremented every time the same MAC-address
+ * is passed to this routine; the address is only removed
+ * from the filter if BSP_mve_mcast_filter_accept_del()
+ * is called the same number of times (or by BSP_mve_mcast_filter_clear).
+ */
+void
+BSP_mve_mcast_filter_accept_add(struct mveth_private *mp, unsigned char *enaddr);
+
+/*
+ * Remove a MAC address from the multicast filter.
+ * This routine decrements the reference count of the given
+ * MAC-address and removes it from the filter once the
+ * count reaches zero.
+ */
+void
+BSP_mve_mcast_filter_accept_del(struct mveth_private *mp, unsigned char *enaddr);
+
+/*
+ * Shutdown hardware and clean out the rings
+ */
+void
+BSP_mve_stop_hw(struct mveth_private *mp);
+
+/* calls BSP_mve_stop_hw(), releases all resources and marks the interface
+ * as unused.
+ * RETURNS 0 on success, nonzero on failure.
+ * NOTE:   the handle MUST NOT be used after successful execution of this
+ *         routine.
+ */
+int
+BSP_mve_detach(struct mveth_private *mp);
+
+/*
+ * Enqueue a mbuf chain or a raw data buffer for transmission;
+ * RETURN: #bytes sent or -1 if there are not enough free descriptors
+ *
+ * If 'len' is <=0 then 'm_head' is assumed to point to a mbuf chain.
+ * OTOH, a raw data packet (or a different type of buffer)
+ * may be send (non-BSD driver) by pointing data_p to the start of
+ * the data and passing 'len' > 0.
+ * 'm_head' is passed back to the 'cleanup_txbuf()' callback.
+ *
+ * Comments: software cache-flushing incurs a penalty if the
+ *           packet cannot be queued since it is flushed anyways.
+ *           The algorithm is slightly more efficient in the normal
+ *			 case, though.
+ *
+ * RETURNS: # bytes enqueued to device for transmission or -1 if no
+ *          space in the TX ring was available.
+ */
+int
+BSP_mve_send_buf(struct mveth_private *mp, void *m_head, void *data_p, int len);
+
+/* Descriptor scavenger; cleanup the TX ring, passing all buffers
+ * that have been sent to the cleanup_tx() callback.
+ * This routine is called from BSP_mve_send_buf(), BSP_mve_init_hw(),
+ * BSP_mve_stop_hw().
+ *
+ * RETURNS: number of buffers processed.
+ */
+int
+BSP_mve_swipe_tx(struct mveth_private *mp);
+
+/* Retrieve all received buffers from the RX ring, replacing them
+ * by fresh ones (obtained from the alloc_rxbuf() callback). The
+ * received buffers are passed to consume_rxbuf().
+ *
+ * RETURNS: number of buffers processed.
+ */
+int
+BSP_mve_swipe_rx(struct mveth_private *mp);
+
+/* read ethernet address from hw to buffer */
+void
+BSP_mve_read_eaddr(struct mveth_private *mp, unsigned char *eaddr);
+
+/* read/write media word.
+ *   'cmd': can be SIOCGIFMEDIA, SIOCSIFMEDIA, 0 or 1. The latter
+ *          are aliased to the former for convenience.
+ *  'parg': pointer to media word.
+ *
+ * RETURNS: 0 on success, nonzero on error
+ *
+ * NOTE:    This routine is thread-safe.
+ */
+int
+BSP_mve_media_ioctl(struct mveth_private *mp, int cmd, int *parg);
+
+/* Interrupt related routines */
+
+/* Note: the BSP_mve_enable/disable/ack_irqs() entry points
+ *       are deprecated.
+ *       The newer API where the user passes a mask allows
+ *       for more selective control.
+ */
+
+/* Enable all supported interrupts at device */
+void
+BSP_mve_enable_irqs(struct mveth_private *mp);
+
+/* Disable all supported interrupts at device */
+void
+BSP_mve_disable_irqs(struct mveth_private *mp);
+
+/* Acknowledge (and clear) all supported interrupts.
+ * RETURNS: interrupts that were raised.
+ */
+uint32_t
+BSP_mve_ack_irqs(struct mveth_private *mp);
+
+/* Enable interrupts included in 'mask' (leaving
+ * already enabled interrupts on). If the mask
+ * includes bits that were not passed to the 'setup'
+ * routine then the behavior is undefined.
+ */
+void
+BSP_mve_enable_irq_mask(struct mveth_private *mp, uint32_t irq_mask);
+
+/* Disable interrupts included in 'mask' (leaving
+ * other ones that are currently enabled on). If the
+ * mask includes bits that were not passed to the 'setup'
+ * routine then the behavior is undefined.
+ *
+ * RETURNS: Bitmask of interrupts that were enabled upon entry
+ *          into this routine. This can be used to restore the
+ *          previous state.
+ */
+uint32_t
+BSP_mve_disable_irq_mask(struct mveth_private *mp, uint32_t irq_mask);
+
+/* Acknowledge and clear selected interrupts.
+ * 
+ * RETURNS: All pending interrupts.
+ *
+ * NOTE:    Only pending interrupts contained in 'mask'
+ *          are cleared. Others are left pending.
+ *
+ *          This routine can be used to check for pending
+ *          interrupts (pass mask ==  0) or to clear all
+ *          interrupts (pass mask == -1).
+ */
+uint32_t
+BSP_mve_ack_irq_mask(struct mveth_private *mp, uint32_t mask);
+
+/* If the PHY link status changes then some
+ * internal settings in the ethernet controller's
+ * serial port need to be updated to match the
+ * PHY settings. Use this routine to perform the
+ * necessary steps after a link change has been
+ * detected.
+ *
+ * RETURNS: 0 on success, -1 if the PHY state
+ *          could not be determined.
+ *
+ *          The current state of the media as read
+ *          by BSP_mve_media_ioctl() is returned in
+ *          *pmedia.
+ *
+ * NOTE:    This routine calls BSP_mve_media_ioctl().
+ */
+int
+BSP_mve_ack_link_chg(struct mveth_private *mp, int *pmedia);
+
+/* Retrieve the driver daemon TID that was passed to
+ * BSP_mve_setup().
+ */
+
+rtems_id
+BSP_mve_get_tid(struct mveth_private *mp);
+
+/* Dump statistics to file (stdout if NULL)
+ *
+ * NOTE: this routine is not thread safe
+ */
+void
+BSP_mve_dump_stats(struct mveth_private *mp, FILE *f);
+
+/* 
+ *
+ * Example driver task loop (note: no synchronization of
+ * buffer access shown!).
+ * RTEMS_EVENTx = 0,1 or 2 depending on IF unit.
+ *
+ *    / * setup (obtain handle) and initialize hw here * /
+ *
+ *    do {
+ *      / * ISR disables IRQs and posts event * /
+ *		rtems_event_receive( RTEMS_EVENTx, RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &evs );
+ *		irqs = BSP_mve_ack_irqs(handle);
+ *      if ( irqs & BSP_MVE_IRQ_TX ) {
+ *			BSP_mve_swipe_tx(handle); / * cleanup_txbuf() callback executed * /
+ *		}
+ *      if ( irqs & BSP_MVE_IRQ_RX ) {
+ *			BSP_mve_swipe_rx(handle); / * alloc_rxbuf() and consume_rxbuf() executed * /
+ *		}
+ *		if ( irqs & BSP_MVE_IRQ_LINK ) {
+ *          / * update serial port settings from current link status * /
+ *          BSP_mve_ack_link_chg(handle, 0);
+ *		}
+ *		BSP_mve_enable_irqs(handle);
+ *    } while (1);
+ *
+ */
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif
Index: bsps/powerpc/beatnik/include/bsp/irq.h
===================================================================
--- bsps/powerpc/beatnik/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,133 @@
+/* irq.h
+ *
+ *  This include file describe the data structure and the functions implemented
+ *  by rtems to write interrupt handlers.
+ *
+ *  CopyRight (C) 1999 valette@crf.canon.fr
+ *
+ *  This code is heavilly inspired by the public specification of STREAM V2
+ *  that can be found at :
+ *
+ *      <http://www.chorus.com/Documentation/index.html> by following
+ *  the STREAM API Specification Document link.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ * Modified by T. Straumann for the beatnik BSP, 2005-2007
+ * Some information may be based on mvme5500/irq/irq.h by K. Feng.
+ */
+
+#ifndef LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H
+#define LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H
+
+#define BSP_SHARED_HANDLER_SUPPORT      1
+#include <rtems/irq.h>
+#include <bsp/vectors.h>
+
+/* This BSP also passes a pointer to the interrupt frame to the handler.
+ * The PPC ABI guarantees that this will not mess up handlers written
+ * without knowledge of this feature.
+ */
+
+typedef void (*BSP_rtems_irq_hdl)(rtems_irq_hdl_param,BSP_Exception_frame*);
+
+
+/* legal priorities are 0 <= priority <= MAX_PRIO; 0 effectively disables the interrupt */
+#define BSP_IRQ_MAX_PRIO		4
+#define BSP_IRQ_MIN_PRIO		1
+
+/* Note that priorites are only honoured for 'PCI' interrupt numbers.
+ * The discovery pic has no support for hardware priorites; hence they
+ * are handled in software
+ */
+#define BSP_IRQ_DEFAULT_PRIORITY 2
+
+
+#define	BSP_PCI_IRQ_LOWEST_OFFSET	0	/* IMPLEMENTATION RELIES ON discovery pic INTERRUPTS HAVING NUMBERS 0..95 */
+#define	BSP_IRQ_DEV			1	/* device interface interrupt */
+#define	BSP_IRQ_DMA			2	/* DMA addres error interrupt (260) */
+#define	BSP_IRQ_CPU			3	/* CPU interface interrupt */
+#define	BSP_IRQ_IDMA0_1			4	/* IDMA ch. 0..1 complete interrupt (260) */
+#define	BSP_IRQ_IDMA2_3			5	/* IDMA ch. 2..3 complete interrupt (260) */
+#define	BSP_IRQ_IDMA4_5			6	/* IDMA ch. 4..5 complete interrupt (260) */
+#define	BSP_IRQ_IDMA6_7			7	/* IDMA ch. 6..7 complete interrupt (260) */
+#define	BSP_IRQ_TIME0_1			8	/* Timer 0..1 interrupt; Timer 0 on 64360 */
+#define	BSP_IRQ_TIME2_3			9	/* Timer 2..3 interrupt; Timer 1 on 64360 */
+#define	BSP_IRQ_TIME4_5			10	/* Timer 4..5 interrupt; Timer 2 on 64360 */
+#define	BSP_IRQ_TIME6_7			11	/* Timer 6..7 interrupt; Timer 3 on 64360 */
+#define	BSP_IRQ_PCI0_0			12	/* PCI 0 interrupt 0 summary (PCI 0 interrupt summary on 64360) */
+#define	BSP_IRQ_PCI0_1			13	/* PCI 0 interrupt 1 summary (SRAM PAR ERROR on 64360)          */
+#define	BSP_IRQ_PCI0_2			14	/* PCI 0 interrupt 2 summary */
+#define	BSP_IRQ_PCI0_3			15	/* PCI 0 interrupt 3 summary */
+#define	BSP_IRQ_PCI1_0			16	/* PCI 1 interrupt 0 summary (PCI 1 interrupt summary on 64360) */
+#define	BSP_IRQ_ECC			    17	/* ECC error interrupt */
+#define	BSP_IRQ_PCI1_1			18	/* PCI 1 interrupt 1 summary */
+#define	BSP_IRQ_PCI1_2			19	/* PCI 1 interrupt 2 summary */
+#define	BSP_IRQ_PCI1_3			20	/* PCI 1 interrupt 3 summary */
+#define	BSP_IRQ_PCI0OUT_LO		21	/* PCI 0 outbound interrupt summary */
+#define	BSP_IRQ_PCI0OUT_HI		22	/* PCI 0 outbound interrupt summary */
+#define	BSP_IRQ_PCI1OUT_LO		23	/* PCI 1 outbound interrupt summary */
+#define	BSP_IRQ_PCI1OUT_HI		24	/* PCI 1 outbound interrupt summary */
+#define	BSP_IRQ_PCI0IN_LO		26	/* PCI 0 inbound interrupt summary */
+#define	BSP_IRQ_PCI0IN_HI		27	/* PCI 0 inbound interrupt summary */
+#define	BSP_IRQ_PCI1IN_LO		28	/* PCI 1 inbound interrupt summary */
+#define	BSP_IRQ_PCI1IN_HI		29	/* PCI 1 inbound interrupt summary */
+#define	BSP_IRQ_ETH0			(32+0)	/* Ethernet controller 0 interrupt */
+#define	BSP_IRQ_ETH1			(32+1)	/* Ethernet controller 1 interrupt */
+#define	BSP_IRQ_ETH2			(32+2)	/* Ethernet controller 2 interrupt */
+#define	BSP_IRQ_SDMA			(32+4)	/* SDMA interrupt */
+#define	BSP_IRQ_I2C			(32+5)	/* I2C interrupt */
+#define	BSP_IRQ_BRG			(32+7)	/* Baud Rate Generator interrupt */
+#define	BSP_IRQ_MPSC0			(32+8)	/* MPSC 0 interrupt */
+#define	BSP_IRQ_MPSC1			(32+10)	/* MPSC 1 interrupt */
+#define	BSP_IRQ_COMM			(32+11)	/* Comm unit interrupt */
+#define	BSP_IRQ_GPP7_0			(32+24)	/* GPP[7..0] interrupt summary */
+#define	BSP_IRQ_GPP15_8			(32+25)	/* GPP[15..8] interrupt summary */
+#define	BSP_IRQ_GPP23_16   		(32+26)	/* GPP[23..16] interrupt summary */
+#define	BSP_IRQ_GPP31_24  		(32+27)	/* GPP[31..24] interrupt summary */
+#define	BSP_IRQ_GPP_0			64
+
+#define	BSP_PCI_IRQ_NUMBER		(64+32)
+#define	BSP_PCI_IRQ_MAX_OFFSET		(BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+#define	BSP_PROCESSOR_IRQ_NUMBER 	1
+#define	BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET+1)
+#define	BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+
+/* summary */
+
+#define	BSP_IRQ_NUMBER			(BSP_PCI_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER)
+#define	BSP_LOWEST_OFFSET		0
+#define	BSP_MAX_OFFSET			(BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1)
+#define	BSP_DECREMENTER			BSP_PROCESSOR_IRQ_LOWEST_OFFSET
+
+#define BSP_UART_COM1_IRQ		BSP_IRQ_GPP_0
+#define BSP_UART_COM2_IRQ		BSP_IRQ_GPP_0
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include <bsp/irq_supp.h>
+
+int  BSP_irq_is_enabled_at_pic(rtems_irq_number irq);
+
+/* set priority of an interrupt; must not be called from ISR level */
+int  BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri);
+
+/* Not for public use */
+void BSP_rtems_irq_mng_init(unsigned cpuId);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
+#endif
Index: bsps/powerpc/beatnik/include/tm27.h
===================================================================
--- bsps/powerpc/beatnik/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/powerpc/beatnik/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1 @@
+#include <rtems/tm27-default.h>
