Index: bsps/mips/csb350/headers.am
===================================================================
--- bsps/mips/csb350/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/csb350/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,10 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/mips/csb350/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/mips/csb350/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/mips/csb350/include/bsp/irq.h
Index: bsps/mips/csb350/include/bsp.h
===================================================================
--- bsps/mips/csb350/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/csb350/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,47 @@
+/**
+ *  @file
+ *  
+ *  This include file contains some definitions specific to the
+ *  Cogent CSB350 Board.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_CSB350_BSP_H
+#define LIBBSP_MIPS_CSB350_BSP_H
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/au1x00.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+/*
+ * Network driver configuration
+ */
+extern struct rtems_bsdnet_ifconfig *config;
+
+int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config,
+                             int attaching);
+#define RTEMS_BSP_NETWORK_DRIVER_NAME	"eth0"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_au1x00_emac_attach
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: bsps/mips/csb350/include/bsp/irq.h
===================================================================
--- bsps/mips/csb350/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/csb350/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_AU1X00_IRQ_H
+#define LIBBSP_MIPS_AU1X00_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ */
+/* MIPS_INTERRUPT_BASE should be 32 (0x20) */
+#define BSP_INTERRUPT_VECTOR_MIN      0
+#define AU1X00_IRQ_SW0                (MIPS_INTERRUPT_BASE + 0)
+#define AU1X00_IRQ_SW1                (MIPS_INTERRUPT_BASE + 1)
+#define AU1X00_IRQ_IC0_REQ0           (MIPS_INTERRUPT_BASE + 2)
+#define AU1X00_IRQ_IC0_REQ1           (MIPS_INTERRUPT_BASE + 3)
+#define AU1X00_IRQ_IC1_REQ0           (MIPS_INTERRUPT_BASE + 4)
+#define AU1X00_IRQ_IC1_REQ1           (MIPS_INTERRUPT_BASE + 5)
+#define AU1X00_IRQ_PERF               (MIPS_INTERRUPT_BASE + 6)
+#define AU1X00_IRQ_CNT                (MIPS_INTERRUPT_BASE + 7)
+
+#define AU1X00_IRQ_IC0_BASE           (MIPS_INTERRUPT_BASE + 8)
+#define AU1X00_IRQ_UART0              (MIPS_INTERRUPT_BASE + 8)
+#define AU1X00_IRQ_INTA               (MIPS_INTERRUPT_BASE + 9)
+#define AU1X00_IRQ_INTB               (MIPS_INTERRUPT_BASE + 10)
+#define AU1X00_IRQ_UART3              (MIPS_INTERRUPT_BASE + 11)
+#define AU1X00_IRQ_INTC               (MIPS_INTERRUPT_BASE + 12)
+#define AU1X00_IRQ_INTD               (MIPS_INTERRUPT_BASE + 13)
+#define AU1X00_IRQ_DMA0               (MIPS_INTERRUPT_BASE + 14)
+#define AU1X00_IRQ_DMA1               (MIPS_INTERRUPT_BASE + 15)
+#define AU1X00_IRQ_DMA2               (MIPS_INTERRUPT_BASE + 16)
+#define AU1X00_IRQ_DMA3               (MIPS_INTERRUPT_BASE + 17)
+#define AU1X00_IRQ_DMA4               (MIPS_INTERRUPT_BASE + 18)
+#define AU1X00_IRQ_DMA5               (MIPS_INTERRUPT_BASE + 19)
+#define AU1X00_IRQ_DMA6               (MIPS_INTERRUPT_BASE + 20)
+#define AU1X00_IRQ_DMA7               (MIPS_INTERRUPT_BASE + 21)
+#define AU1X00_IRQ_TOY_TICK           (MIPS_INTERRUPT_BASE + 22)
+#define AU1X00_IRQ_TOY_MATCH0         (MIPS_INTERRUPT_BASE + 23)
+#define AU1X00_IRQ_TOY_MATCH1         (MIPS_INTERRUPT_BASE + 24)
+#define AU1X00_IRQ_TOY_MATCH2         (MIPS_INTERRUPT_BASE + 25)
+#define AU1X00_IRQ_RTC_TICK           (MIPS_INTERRUPT_BASE + 26)
+#define AU1X00_IRQ_RTC_MATCH0         (MIPS_INTERRUPT_BASE + 27)
+#define AU1X00_IRQ_RTC_MATCH1         (MIPS_INTERRUPT_BASE + 28)
+#define AU1X00_IRQ_RTC_MATCH2         (MIPS_INTERRUPT_BASE + 29)
+#define AU1X00_IRQ_PCI_ERR            (MIPS_INTERRUPT_BASE + 30)
+#define AU1X00_IRQ_RSV0               (MIPS_INTERRUPT_BASE + 31)
+#define AU1X00_IRQ_USB_DEV            (MIPS_INTERRUPT_BASE + 32)
+#define AU1X00_IRQ_USB_SUSPEND        (MIPS_INTERRUPT_BASE + 33)
+#define AU1X00_IRQ_USB_HOST           (MIPS_INTERRUPT_BASE + 34)
+#define AU1X00_IRQ_AC97_ACSYNC        (MIPS_INTERRUPT_BASE + 35)
+#define AU1X00_IRQ_MAC0               (MIPS_INTERRUPT_BASE + 36)
+#define AU1X00_IRQ_MAC1               (MIPS_INTERRUPT_BASE + 37)
+#define AU1X00_IRQ_RSV1               (MIPS_INTERRUPT_BASE + 38)
+#define AU1X00_IRQ_AC97_CMD           (MIPS_INTERRUPT_BASE + 39)
+
+#define AU1X00_IRQ_IC1_BASE           (MIPS_INTERRUPT_BASE + 40)
+#define AU1X00_IRQ_GPIO0              (MIPS_INTERRUPT_BASE + 40)
+#define AU1X00_IRQ_GPIO1              (MIPS_INTERRUPT_BASE + 41)
+#define AU1X00_IRQ_GPIO2              (MIPS_INTERRUPT_BASE + 42)
+#define AU1X00_IRQ_GPIO3              (MIPS_INTERRUPT_BASE + 43)
+#define AU1X00_IRQ_GPIO4              (MIPS_INTERRUPT_BASE + 44)
+#define AU1X00_IRQ_GPIO5              (MIPS_INTERRUPT_BASE + 45)
+#define AU1X00_IRQ_GPIO6              (MIPS_INTERRUPT_BASE + 46)
+#define AU1X00_IRQ_GPIO7              (MIPS_INTERRUPT_BASE + 47)
+#define AU1X00_IRQ_GPIO8              (MIPS_INTERRUPT_BASE + 48)
+#define AU1X00_IRQ_GPIO9              (MIPS_INTERRUPT_BASE + 49)
+#define AU1X00_IRQ_GPIO10             (MIPS_INTERRUPT_BASE + 50)
+#define AU1X00_IRQ_GPIO11             (MIPS_INTERRUPT_BASE + 51)
+#define AU1X00_IRQ_GPIO12             (MIPS_INTERRUPT_BASE + 52)
+#define AU1X00_IRQ_GPIO13             (MIPS_INTERRUPT_BASE + 53)
+#define AU1X00_IRQ_GPIO14             (MIPS_INTERRUPT_BASE + 54)
+#define AU1X00_IRQ_GPIO15             (MIPS_INTERRUPT_BASE + 55)
+#define AU1X00_IRQ_GPIO200            (MIPS_INTERRUPT_BASE + 56)
+#define AU1X00_IRQ_GPIO201            (MIPS_INTERRUPT_BASE + 57)
+#define AU1X00_IRQ_GPIO202            (MIPS_INTERRUPT_BASE + 58)
+#define AU1X00_IRQ_GPIO203            (MIPS_INTERRUPT_BASE + 59)
+#define AU1X00_IRQ_GPIO20             (MIPS_INTERRUPT_BASE + 60)
+#define AU1X00_IRQ_GPIO204            (MIPS_INTERRUPT_BASE + 61)
+#define AU1X00_IRQ_GPIO205            (MIPS_INTERRUPT_BASE + 62)
+#define AU1X00_IRQ_GPIO23             (MIPS_INTERRUPT_BASE + 63)
+#define AU1X00_IRQ_GPIO24             (MIPS_INTERRUPT_BASE + 64)
+#define AU1X00_IRQ_GPIO25             (MIPS_INTERRUPT_BASE + 65)
+#define AU1X00_IRQ_GPIO26             (MIPS_INTERRUPT_BASE + 66)
+#define AU1X00_IRQ_GPIO27             (MIPS_INTERRUPT_BASE + 67)
+#define AU1X00_IRQ_GPIO28             (MIPS_INTERRUPT_BASE + 68)
+#define AU1X00_IRQ_GPIO206            (MIPS_INTERRUPT_BASE + 69)
+#define AU1X00_IRQ_GPIO207            (MIPS_INTERRUPT_BASE + 70)
+#define AU1X00_IRQ_GPIO208_215        (MIPS_INTERRUPT_BASE + 71)
+
+#define AU1X00_MAXIMUM_VECTORS        (MIPS_INTERRUPT_BASE + 72)
+
+#define BSP_INTERRUPT_VECTOR_MAX      AU1X00_MAXIMUM_VECTORS 
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_AU1X00_IRQ_H */
Index: bsps/mips/csb350/include/tm27.h
===================================================================
--- bsps/mips/csb350/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/csb350/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,48 @@
+/**
+ *  @file
+ */
+
+/*
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <bsp/irq.h>
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ */
+
+int assert_sw_irw(uint32_t irqnum);
+int negate_sw_irw(uint32_t irqnum);
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) \
+   rtems_interrupt_handler_install( \
+      AU1X00_IRQ_SW0, "benchmark", 0, (rtems_interrupt_handler)handler, NULL );
+
+#define Cause_tm27_intr() \
+  do { \
+     assert_sw_irq(0); \
+  } while(0)
+
+#define Clear_tm27_intr() \
+  do { \
+     negate_sw_irq(0); \
+  } while(0)
+
+#define Lower_tm27_intr() \
+  do { \
+     continue;\
+  } while(0)
+
+#endif
Index: bsps/mips/headers.am
===================================================================
--- bsps/mips/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,15 @@
+## This file was generated by "./boostrap -H".
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../bsps/mips/include/bsp/i8259.h
+include_bsp_HEADERS += ../../../../../bsps/mips/include/bsp/regs.h
+
+include_libcpudir = $(includedir)/libcpu
+include_libcpu_HEADERS =
+include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/au1x00.h
+include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/isr_entries.h
+include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/rm5231.h
+include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/tx3904.h
+include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/tx4925.h
+include_libcpu_HEADERS += ../../../../../bsps/mips/include/libcpu/tx4938.h
Index: bsps/mips/hurricane/headers.am
===================================================================
--- bsps/mips/hurricane/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/hurricane/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,11 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/mips/hurricane/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/mips/hurricane/include/tm27.h
+include_HEADERS += ../../../../../../bsps/mips/hurricane/include/usc.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/mips/hurricane/include/bsp/irq.h
Index: bsps/mips/hurricane/include/bsp.h
===================================================================
--- bsps/mips/hurricane/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/hurricane/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,79 @@
+/**
+ *  @file
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_HURRICANE_BSP_H
+#define LIBBSP_MIPS_HURRICANE_BSP_H
+
+#ifndef ASM
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/rm5231.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void WriteDisplay( char * string );
+
+extern uint32_t mips_get_timer( void );
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+#define CPU_CLOCK_RATE_MHZ     (200)
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ *
+ *  NOTE: This macro generates a warning like "integer constant out
+ *        of range" which is safe to ignore.  In 64 bit mode, unsigned32
+ *        types are actually 64 bits long so that comparisons between
+ *        unsigned32 types and pointers are valid.  The warning is caused
+ *        by code in the delay macro that is necessary for 64 bit mode.
+ */
+
+#define rtems_bsp_delay( microseconds ) \
+  { \
+     uint32_t _end_clock = \
+          mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \
+     _end_clock %= 0x100000000;  /* make sure result is 32 bits */ \
+     \
+     /* handle timer overflow, if necessary */ \
+     while ( _end_clock < mips_get_timer() );  \
+     \
+     while ( _end_clock > mips_get_timer() ); \
+  }
+
+/* Constants */
+
+#define RAM_START 0
+#define RAM_END   0x100000
+
+/*
+ * Prototypes for methods called from .S for dependency tracking
+ */
+void init_tlb(void);
+void resettlb(int i);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif	/* __HURRICANE_BSP_h */
Index: bsps/mips/hurricane/include/bsp/irq.h
===================================================================
--- bsps/mips/hurricane/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/hurricane/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,40 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_XXX_IRQ_H
+#define LIBBSP_MIPS_XXX_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN    0
+#define RM5231_MAXIMUM_VECTORS      (MIPS_INTERRUPT_BASE+8)
+#define BSP_INTERRUPT_VECTOR_MAX    RM5231_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */
Index: bsps/mips/hurricane/include/tm27.h
===================================================================
--- bsps/mips/hurricane/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/hurricane/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1 @@
+#include <rtems/tm27-default.h>
Index: bsps/mips/hurricane/include/usc.h
===================================================================
--- bsps/mips/hurricane/include/usc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/hurricane/include/usc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,32 @@
+/* USC constants */
+
+#ifndef _USC_H__
+#define _USC_H__
+
+
+#define USC_REG_BASE	(0x1D000000 | 0xA0000000)
+
+/* Internal register addresses */
+#define SYSTEM (USC_REG_BASE + 0x73)
+
+#define INT_CFG0 (USC_REG_BASE + 0xE0)
+#define INT_CFG1 (USC_REG_BASE + 0xE4)
+#define INT_CFG2 (USC_REG_BASE + 0xE8)
+#define INT_STAT (USC_REG_BASE + 0xEC)
+
+#define WD_HBI (USC_REG_BASE + 0xF4)
+
+#define INT_CFG3 (USC_REG_BASE + 0x158)
+
+/* INT_CFGx register masks */
+#define HBI_MASK	0x00200000	/* Heartbeat timer interrupt mask */
+#define WDI_MASK	0x00400000	/* Watchdog timer interrupt mask */
+#define MODE_TOTEM_POLE	0x20000000	/* Totem Pole Output Mode */
+
+/* WD_HBI register bits */
+#define WD_EN 0x00800000	/* Watchdog enable */
+#define HBI_4000_PS	0x00200000	/* Heartbeat timer prescaler = 4000 */
+#define WD_INIT 0x10	/* Watchdog reset pattern (written to byte 2 in WD_HBI register) */
+
+
+#endif /* _USC_H__ */
Index: bsps/mips/include/bsp/i8259.h
===================================================================
--- bsps/mips/include/bsp/i8259.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/bsp/i8259.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,269 @@
+/**
+ * @file
+ * @ingroup mips_i8259_irq
+ * @brief Data structure and functions used to control i8259 chip.
+ */
+
+/* irq.h
+ *
+ *  This include file describe the data structure and the functions implemented
+ *  by RTEMS to control the i8259 chip.
+ *
+ *  Copyright (C) 1999 valette@crf.canon.fr
+ *
+ *  This code is heavilly inspired by the public specification of STREAM V2
+ *  that can be found at :
+ *
+ *      <http://www.chorus.com/Documentation/index.html> by following
+ *  the STREAM API Specification Document link.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef I8259_H
+#define I8259_H
+
+/**
+ * @defgroup mips_i8259_irq i8259 Chip Support
+ * @ingroup mips_shared
+ * @brief i8259 Chip Support
+ * @{
+ */
+
+/**
+ * @name 8259 edge/level control definitions at VIA
+ * @{
+ */
+
+#if 1 
+#define ISA8259_M_ELCR 		0x4d0
+#define ISA8259_S_ELCR 		0x4d1
+#endif
+
+#define ELCRS_INT15_LVL         0x80
+#define ELCRS_INT14_LVL         0x40
+#define ELCRS_INT13_LVL         0x20
+#define ELCRS_INT12_LVL         0x10
+#define ELCRS_INT11_LVL         0x08
+#define ELCRS_INT10_LVL         0x04
+#define ELCRS_INT9_LVL          0x02
+#define ELCRS_INT8_LVL          0x01
+#define ELCRM_INT7_LVL          0x80
+#define ELCRM_INT6_LVL          0x40
+#define ELCRM_INT5_LVL          0x20
+#define ELCRM_INT4_LVL          0x10
+#define ELCRM_INT3_LVL          0x8
+#define ELCRM_INT2_LVL          0x4
+#define ELCRM_INT1_LVL          0x2
+#define ELCRM_INT0_LVL          0x1
+
+/** @} */
+
+/**
+ * @name PIC's command and mask registers
+ * @{
+ */
+
+#define PIC_MASTER_COMMAND_IO_PORT		0x20	///< @brief Master PIC command register */
+#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	///< @brief Slave PIC command register */
+#define PIC_MASTER_IMR_IO_PORT			0x21	///< @brief Master PIC Interrupt Mask Register */
+#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	///< @brief Slave PIC Interrupt Mask Register */
+
+/** @} */
+
+/**
+ * @name Command for specific EOI (End Of Interrupt): Interrupt acknowledge
+ * @{
+ */
+
+#define PIC_EOSI	0x60	///< @brief End of Specific Interrupt (EOSI) */
+#define	SLAVE_PIC_EOSI  0x62	///< @brief End of Specific Interrupt (EOSI) for cascade */
+#define PIC_EOI		0x20	///< @brief Generic End of Interrupt (EOI) */
+
+/** @} */
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * rtems_irq_number Definitions
+ */
+#if 0
+
+/**
+ * @name ISA IRQ handler related definitions
+ * @{
+ */
+
+#define BSP_ISA_IRQ_NUMBER		(16)
+#define BSP_ISA_IRQ_LOWEST_OFFSET	(0)
+#define BSP_ISA_IRQ_MAX_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
+
+/** @} */
+
+#ifndef qemu
+#define BSP_PCI_IRQ_NUMBER		(16)
+#else
+#define BSP_PCI_IRQ_NUMBER		(0)
+#endif
+#define BSP_PCI_IRQ_LOWEST_OFFSET	(BSP_ISA_IRQ_NUMBER)
+#define BSP_PCI_IRQ_MAX_OFFSET		(BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+/*
+ * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
+ * handler might be connected
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER	(1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+/* Misc vectors for OPENPIC irqs (IPI, timers)
+ */
+#ifndef qemu
+#define BSP_MISC_IRQ_NUMBER		(8)
+#else
+#define BSP_MISC_IRQ_NUMBER		(0)
+#endif
+
+#define BSP_MISC_IRQ_LOWEST_OFFSET	(BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
+#define BSP_MISC_IRQ_MAX_OFFSET		(BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
+
+/**
+ * @name Summary
+ * @{
+ */
+
+#define BSP_IRQ_NUMBER			(BSP_MISC_IRQ_MAX_OFFSET + 1)
+#define BSP_LOWEST_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET)
+#define BSP_MAX_OFFSET			(BSP_MISC_IRQ_MAX_OFFSET)
+
+/** @} */
+
+/**
+ * @name Some ISA IRQ symbolic name definition
+ * @{
+ */
+
+#define BSP_ISA_PERIODIC_TIMER      	(0)
+#define BSP_ISA_KEYBOARD          	(1)
+#define BSP_ISA_UART_COM2_IRQ		(3)
+#define BSP_ISA_UART_COM1_IRQ		(4)
+#define BSP_ISA_RT_TIMER1	      	(8)
+#define BSP_ISA_RT_TIMER3		(10)
+
+/** @} */
+
+/**
+ * @name Some PCI IRQ symbolic name definition
+ * @{
+ */
+
+#define BSP_PCI_IRQ0			(BSP_PCI_IRQ_LOWEST_OFFSET)
+#if     BSP_PCI_IRQ_NUMBER > 0
+#define BSP_PCI_ISA_BRIDGE_IRQ		(BSP_PCI_IRQ0)
+#endif
+
+/** @} */
+
+#if defined(mvme2100)
+#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
+#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
+#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
+#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
+#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
+#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
+#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
+#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
+#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
+#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
+#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
+#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
+#else
+#define BSP_UART_COM1_IRQ		BSP_ISA_UART_COM1_IRQ
+#define BSP_UART_COM2_IRQ		BSP_ISA_UART_COM2_IRQ
+#endif
+
+/**
+ * @brief Some Processor execption handled as RTEMS IRQ symbolic name definition
+ */
+#define BSP_DECREMENTER			(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+#endif
+
+/**
+ * @name Type definition for RTEMS managed interrupts
+ * @{
+ */
+
+typedef unsigned short rtems_i8259_masks;
+extern  volatile rtems_i8259_masks i8259s_cache;
+
+/** @} */
+
+/*-------------------------------------------------------------------------+
+| Function Prototypes.
++--------------------------------------------------------------------------*/
+/*
+ * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
+ */
+
+/**
+ * @name Function Prototypes
+ * @{
+ */
+
+void BSP_i8259s_init(void);
+
+/**
+ * @brief function to disable a particular irq at 8259 level.
+ *
+ * After calling this function, even if the device asserts the interrupt
+ * line it will not be propagated further to the processor.
+ *
+ * @retval 1 the interrupt was enabled originally
+ * @retval 0 the interrupt was disabled originally
+ * @retval <0 error
+ */
+int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
+
+/**
+ * @brief function to enable a particular irq at 8259 level.
+ *
+ * After calling this function, if the device asserts the interrupt line
+ * it will be propagated further to the processor.
+ */
+int BSP_irq_enable_at_i8259s		(const rtems_irq_number irqLine);
+
+/**
+ * @brief function to acknowledge a particular irq at 8259 level.
+ *
+ * After calling this function, if a device asserts an enabled interrupt
+ * line it will be propagated further to the processor. Mainly useful for
+ * people writing raw handlers as this is automagically done for RTEMS managed
+ * handlers.
+ */
+int BSP_irq_ack_at_i8259s           	(const rtems_irq_number irqLine);
+
+/**
+ * @brief function to check if a particular irq is enabled at 8259 level.
+ */
+int BSP_irq_enabled_at_i8259s        	(const rtems_irq_number irqLine);
+
+int BSP_i8259s_int_process(void);
+
+extern void BSP_rtems_irq_mng_init(unsigned cpuId);
+extern void BSP_i8259s_init(void);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+#endif
Index: bsps/mips/include/bsp/regs.h
===================================================================
--- bsps/mips/include/bsp/regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/bsp/regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,187 @@
+/**
+ * @file
+ * @ingroup mips_regs
+ * @brief Standard MIPS register names.
+ */
+
+/*
+ * regs.S -- standard MIPS register names.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/**
+ * @defgroup mips_regs MIPS Registers
+ * @ingroup mips_shared
+ * @brief MIPS Registers
+ * @{
+ */
+
+/**
+ * @name Standard MIPS register names:
+ * @{
+ */
+
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	///< @brief kernel private register 0 */
+#define k1	$27	///< @brief kernel private register 1 */
+#define gp	$28	///< @brief global data pointer */
+#define sp 	$29	///< @brief stack-pointer */
+#define fp	$30	///< @brief frame-pointer */
+#define ra	$31	///< @brief return address */
+#define pc	$pc	///< @brief pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/** @} */
+
+/**
+ * @name Useful memory constants:
+ * @{
+ */
+
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+/** @} */
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/**
+ * @name Standard Co-Processor 0 register numbers:
+ * @{
+ */
+
+#define C0_COUNT	$9		///< @brief Count Register */
+#define C0_SR		$12		///< @brief Status Register */
+#define C0_CAUSE	$13		///< @brief last exception description */
+#define C0_EPC		$14		///< @brief Exception error address */
+#define C0_CONFIG	$16		///< @brief CPU configuration */
+
+/** @} */
+
+/**
+ * @name Standard Status Register bitmasks:
+ * @{
+ */
+
+#define SR_CU1		0x20000000	///< @brief Mark CP1 as usable */
+#define SR_FR		0x04000000	///< @brief Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	///< @brief Controls location of exception vectors */
+#define SR_PE		0x00100000	///< @brief Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	///< @brief Kernel extended addressing enabled */
+#define SR_SX		0x00000040	///< @brief Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	///< @brief User extended addressing enabled */
+
+/** @} */
+
+/**
+ * @name Standard (R4000) cache operations.
+ * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition:
+ * @{
+ */
+
+#define CACHE_I		(0)	///< @brief primary instruction */
+#define CACHE_D		(1)	///< @brief primary data */
+#define CACHE_SI	(2)	///< @brief secondary instruction */
+#define CACHE_SD	(3)	///< @brief secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	///< @brief CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	///< @brief CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	///< @brief CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	///< @brief CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	///< @brief CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/** @} */
+
+/**
+ * @name Individual cache operations:
+ * @{
+ */
+
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/** @} */
+
+/** @} */
+
+/*> EOF regs.S <*/
Index: bsps/mips/include/libcpu/au1x00.h
===================================================================
--- bsps/mips/include/libcpu/au1x00.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/libcpu/au1x00.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,445 @@
+/**
+ *  @file
+ *  
+ *  AMD AU1X00 specific information
+ */
+
+/*
+ *  Copyright (c) 2005 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __AU1X00_H__
+#define __AU1X00_H__
+
+#define bit(x)         (1 << (x))
+
+/* Au1x00 CP0 registers
+ */
+#define CP0_Index		$0
+#define CP0_Random		$1
+#define CP0_EntryLo0	$2
+#define CP0_EntryLo1	$3
+#define CP0_Context		$4
+#define CP0_PageMask	$5
+#define CP0_Wired		$6
+#define CP0_BadVAddr	$8
+#define CP0_Count		$9
+#define CP0_EntryHi		$10
+#define CP0_Compare		$11
+#define CP0_Status		$12
+#define CP0_Cause		$13
+#define CP0_EPC			$14
+#define CP0_PRId		$15
+#define CP0_Config		$16
+#define CP0_Config0		$16
+#define CP0_Config1		$16,1
+#define CP0_LLAddr		$17
+#define CP0_WatchLo		$18
+#define CP0_IWatchLo	$18,1
+#define CP0_WatchHi		$19
+#define CP0_IWatchHi	$19,1
+#define CP0_Scratch		$22
+#define CP0_Debug		$23
+#define CP0_DEPC		$24
+#define CP0_PerfCnt		$25
+#define CP0_PerfCtrl	$25,1
+#define CP0_DTag		$28
+#define CP0_DData		$28,1
+#define CP0_ITag		$29
+#define CP0_IData		$29,1
+#define CP0_ErrorEPC	$30
+#define CP0_DESave		$31
+
+/* Addresses common to all AU1x00 CPUs */
+#define AU1X00_MEM_ADDR		0xB4000000
+#define AU1X00_AC97_ADDR	0xB0000000
+#define AU1X00_USBH_ADDR	0xB0100000
+#define AU1X00_USBD_ADDR	0xB0200000
+#define AU1X00_MACDMA0_ADDR	0xB4004000
+#define AU1X00_MACDMA1_ADDR	0xB4004200
+#define AU1X00_UART0_ADDR	0xB1100000
+#define AU1X00_UART3_ADDR	0xB1400000
+#define AU1X00_SYS_ADDR	        0xB1900000
+#define AU1X00_GPIO2_ADDR	0xB1700000
+#define AU1X00_IC0_ADDR	        0xB0400000
+#define AU1X00_IC1_ADDR	        0xB1800000
+
+/* Au1100 base addresses (in KSEG1 region) */
+#define AU1100_MAC0_ADDR	0xB0500000
+#define AU1100_MACEN_ADDR	0xB0520000
+
+/* Au1500 base addresses (in KSEG1 region) */
+#define AU1500_MAC0_ADDR	0xB1500000
+#define AU1500_MAC1_ADDR	0xB1510000
+#define AU1500_MACEN_ADDR	0xB1520000
+#define AU1500_PCI_ADDR	        0xB4005000
+
+/* Au1x00 gpio2 register offsets
+ */
+#define gpio2_dir		0x0000
+#define gpio2_output	0x0008
+#define gpio2_pinstate	0x000c
+#define gpio2_inten		0x0010
+#define gpio2_enable	0x0014
+
+/* Au1x00 memory controller register offsets
+ */
+#define mem_sdmode0		0x0000
+#define mem_sdmode1		0x0004
+#define mem_sdmode2		0x0008
+#define mem_sdaddr0		0x000C
+#define mem_sdaddr1		0x0010
+#define mem_sdaddr2		0x0014
+#define mem_sdrefcfg	0x0018
+#define mem_sdprecmd	0x001C
+#define mem_sdautoref	0x0020
+#define mem_sdwrmd0		0x0024
+#define mem_sdwrmd1		0x0028
+#define mem_sdwrmd2		0x002C
+#define mem_sdsleep		0x0030
+#define mem_sdsmcke		0x0034
+
+#define mem_stcfg0		0x1000
+#define mem_sttime0		0x1004
+#define mem_staddr0		0x1008
+#define mem_stcfg1		0x1010
+#define mem_sttime1		0x1014
+#define mem_staddr1		0x1018
+#define mem_stcfg2		0x1020
+#define mem_sttime2		0x1024
+#define mem_staddr2		0x1028
+#define mem_stcfg3		0x1030
+#define mem_sttime3		0x1034
+#define mem_staddr3		0x1038
+
+/*
+ * Au1x00 peripheral register offsets
+ */
+#define ac97_enable		0x0010
+#define usbh_enable		0x0007FFFC
+#define usbd_enable		0x0058
+#define irda_enable		0x0040
+#define macen_mac0		0x0000
+#define macen_mac1		0x0004
+#define i2s_enable		0x0008
+#define uart_enable		0x0100
+#define ssi_enable		0x0100
+
+#define sys_scratch0	0x0018
+#define sys_scratch1	0x001c
+#define sys_cntctrl		0x0014
+#define sys_freqctrl0	0x0020
+#define sys_freqctrl1	0x0024
+#define sys_clksrc		0x0028
+#define sys_pinfunc		0x002C
+#define sys_powerctrl	0x003C
+#define sys_endian		0x0038
+#define sys_wakesrc		0x005C
+#define sys_cpupll		0x0060
+#define sys_auxpll		0x0064
+#define sys_pininputen	0x0110
+
+#define pci_cmem			0x0000
+#define pci_config			0x0004
+#define pci_b2bmask_cch		0x0008
+#define pci_b2bbase0_venid	0x000C
+#define pci_b2bbase1_id		0x0010
+#define pci_mwmask_dev		0x0014
+#define pci_mwbase_rev_ccl	0x0018
+#define pci_err_addr		0x001C
+#define pci_spec_intack		0x0020
+#define pci_id				0x0100
+#define pci_statcmd			0x0104
+#define pci_classrev		0x0108
+#define pci_hdrtype			0x010C
+#define pci_mbar			0x0110
+
+/*
+ * CSB250-specific values
+ */
+
+#define SYS_CPUPLL		33
+#define SYS_POWERCTRL	1
+#define SYS_AUXPLL		8
+#define SYS_CNTCTRL		256
+
+/* RCE0: */
+#define MEM_STCFG0	0x00000203
+#define MEM_STTIME0	0x22080b20
+#define MEM_STADDR0	0x11f03fc0
+
+/* RCE1: */
+#define MEM_STCFG1	0x00000203
+#define MEM_STTIME1	0x22080b20
+#define MEM_STADDR1	0x11e03fc0
+
+/* RCE2: */
+#define MEM_STCFG2	0x00000244
+#define MEM_STTIME2	0x22080a20
+#define MEM_STADDR2	0x11803f00
+
+/* RCE3: */
+#define MEM_STCFG3	0x00000201
+#define MEM_STTIME3	0x22080b20
+#define MEM_STADDR3	0x11003f00
+
+/*
+ * SDCS0 -
+ * SDCS1 -
+ * SDCS2 -
+ */
+#define MEM_SDMODE0		0x00552229
+#define MEM_SDMODE1		0x00552229
+#define MEM_SDMODE2		0x00552229
+
+#define MEM_SDADDR0		0x001003F8
+#define MEM_SDADDR1		0x001023F8
+#define MEM_SDADDR2		0x001043F8
+
+#define MEM_SDREFCFG_D	0x74000c30	/* disable */
+#define MEM_SDREFCFG_E	0x76000c30	/* enable */
+#define MEM_SDWRMD0		0x00000023
+#define MEM_SDWRMD1		0x00000023
+#define MEM_SDWRMD2		0x00000023
+
+#define MEM_1MS			((396000000/1000000) * 1000)
+
+#define AU1X00_IC_CFG0RD(x)       (*(volatile uint32_t*)(x + 0x40))
+#define AU1X00_IC_CFG0SET(x)      (*(volatile uint32_t*)(x + 0x40))
+#define AU1X00_IC_CFG0CLR(x)      (*(volatile uint32_t*)(x + 0x44))
+#define AU1X00_IC_CFG1RD(x)       (*(volatile uint32_t*)(x + 0x48))
+#define AU1X00_IC_CFG1SET(x)      (*(volatile uint32_t*)(x + 0x48))
+#define AU1X00_IC_CFG1CLR(x)      (*(volatile uint32_t*)(x + 0x4c))
+#define AU1X00_IC_CFG2RD(x)       (*(volatile uint32_t*)(x + 0x50))
+#define AU1X00_IC_CFG2SET(x)      (*(volatile uint32_t*)(x + 0x50))
+#define AU1X00_IC_CFG2CLR(x)      (*(volatile uint32_t*)(x + 0x54))
+#define AU1X00_IC_REQ0INT(x)      (*(volatile uint32_t*)(x + 0x54))
+#define AU1X00_IC_SRCRD(x)        (*(volatile uint32_t*)(x + 0x58))
+#define AU1X00_IC_SRCSET(x)       (*(volatile uint32_t*)(x + 0x58))
+#define AU1X00_IC_SRCCLR(x)       (*(volatile uint32_t*)(x + 0x5c))
+#define AU1X00_IC_REQ1INT(x)      (*(volatile uint32_t*)(x + 0x5c))
+#define AU1X00_IC_ASSIGNRD(x)     (*(volatile uint32_t*)(x + 0x60))
+#define AU1X00_IC_ASSIGNSET(x)    (*(volatile uint32_t*)(x + 0x60))
+#define AU1X00_IC_ASSIGNCLR(x)    (*(volatile uint32_t*)(x + 0x64))
+#define AU1X00_IC_WAKERD(x)       (*(volatile uint32_t*)(x + 0x68))
+#define AU1X00_IC_WAKESET(x)      (*(volatile uint32_t*)(x + 0x68))
+#define AU1X00_IC_WAKECLR(x)      (*(volatile uint32_t*)(x + 0x6c))
+#define AU1X00_IC_MASKRD(x)       (*(volatile uint32_t*)(x + 0x70))
+#define AU1X00_IC_MASKSET(x)      (*(volatile uint32_t*)(x + 0x70))
+#define AU1X00_IC_MASKCLR(x)      (*(volatile uint32_t*)(x + 0x74))
+#define AU1X00_IC_RISINGRD(x)     (*(volatile uint32_t*)(x + 0x78))
+#define AU1X00_IC_RISINGCLR(x)    (*(volatile uint32_t*)(x + 0x78))
+#define AU1X00_IC_FALLINGRD(x)    (*(volatile uint32_t*)(x + 0x7c))
+#define AU1X00_IC_FALLINGCLR(x)   (*(volatile uint32_t*)(x + 0x7c))
+#define AU1X00_IC_TESTBIT(x)      (*(volatile uint32_t*)(x + 0x80))
+#define AU1X00_IC_IRQ_MAC0        (bit(28))
+#define AU1X00_IC_IRQ_MAC1        (bit(29))
+#define AU1X00_IC_IRQ_TOY_MATCH0  (bit(15))
+#define AU1X00_IC_IRQ_TOY_MATCH1  (bit(16))
+#define AU1X00_IC_IRQ_TOY_MATCH2  (bit(17))
+
+
+
+#define AU1X00_SYS_TOYTRIM(x)    (*(volatile uint32_t*)(x + 0x00))
+#define AU1X00_SYS_TOYWRITE(x)   (*(volatile uint32_t*)(x + 0x04))
+#define AU1X00_SYS_TOYMATCH0(x)  (*(volatile uint32_t*)(x + 0x08))
+#define AU1X00_SYS_TOYMATCH1(x)  (*(volatile uint32_t*)(x + 0x0c))
+#define AU1X00_SYS_TOYMATCH2(x)  (*(volatile uint32_t*)(x + 0x10))
+#define AU1X00_SYS_CNTCTRL(x)    (*(volatile uint32_t*)(x + 0x14))
+#define AU1X00_SYS_SCRATCH0(x)   (*(volatile uint32_t*)(x + 0x18))
+#define AU1X00_SYS_SCRATCH1(x)   (*(volatile uint32_t*)(x + 0x1c))
+#define AU1X00_SYS_WAKEMSK(x)   (*(volatile uint32_t*)(x + 0x34))
+#define AU1X00_SYS_ENDIAN(x)     (*(volatile uint32_t*)(x + 0x38))
+#define AU1X00_SYS_POWERCTRL(x)  (*(volatile uint32_t*)(x + 0x3c))
+#define AU1X00_SYS_TOYREAD(x)    (*(volatile uint32_t*)(x + 0x40))
+#define AU1X00_SYS_RTCTRIM(x)    (*(volatile uint32_t*)(x + 0x44))
+#define AU1X00_SYS_RTCWRITE(x)   (*(volatile uint32_t*)(x + 0x48))
+#define AU1X00_SYS_RTCMATCH0(x)  (*(volatile uint32_t*)(x + 0x4c))
+#define AU1X00_SYS_RTCMATCH1(x)  (*(volatile uint32_t*)(x + 0x50))
+#define AU1X00_SYS_RTCMATCH2(x)  (*(volatile uint32_t*)(x + 0x54))
+#define AU1X00_SYS_RTCREAD(x)    (*(volatile uint32_t*)(x + 0x58))
+#define AU1X00_SYS_WAKESRC(x)    (*(volatile uint32_t*)(x + 0x5c))
+#define AU1X00_SYS_SLPPWR(x)     (*(volatile uint32_t*)(x + 0x78))
+#define AU1X00_SYS_SLEEP(x)      (*(volatile uint32_t*)(x + 0x7c))
+
+#define AU1X00_SYS_CNTCTRL_ERS   (bit(23))
+#define AU1X00_SYS_CNTCTRL_RTS   (bit(20))
+#define AU1X00_SYS_CNTCTRL_RM2   (bit(19))
+#define AU1X00_SYS_CNTCTRL_RM1   (bit(18))
+#define AU1X00_SYS_CNTCTRL_RM0   (bit(17))
+#define AU1X00_SYS_CNTCTRL_RS    (bit(16))
+#define AU1X00_SYS_CNTCTRL_BP    (bit(14))
+#define AU1X00_SYS_CNTCTRL_REN   (bit(13))
+#define AU1X00_SYS_CNTCTRL_BRT   (bit(12))
+#define AU1X00_SYS_CNTCTRL_TEN   (bit(11))
+#define AU1X00_SYS_CNTCTRL_BTT   (bit(10))
+#define AU1X00_SYS_CNTCTRL_E0    (bit(8))
+#define AU1X00_SYS_CNTCTRL_ETS   (bit(7))
+#define AU1X00_SYS_CNTCTRL_32S   (bit(5))
+#define AU1X00_SYS_CNTCTRL_TTS   (bit(4))
+#define AU1X00_SYS_CNTCTRL_TM2   (bit(3))
+#define AU1X00_SYS_CNTCTRL_TM1   (bit(2))
+#define AU1X00_SYS_CNTCTRL_TM0   (bit(1))
+#define AU1X00_SYS_CNTCTRL_TS    (bit(0))
+#define AU1X00_SYS_WAKEMSK_M20   (bit(8))
+
+#define AU1X00_MAC_CONTROL(x)         (*(volatile uint32_t*)(x + 0x00))
+#define AU1X00_MAC_ADDRHIGH(x)        (*(volatile uint32_t*)(x + 0x04))
+#define AU1X00_MAC_ADDRLOW(x)         (*(volatile uint32_t*)(x + 0x08))
+#define AU1X00_MAC_HASHHIGH(x)        (*(volatile uint32_t*)(x + 0x0c))
+#define AU1X00_MAC_HASHLOW(x)         (*(volatile uint32_t*)(x + 0x10))
+#define AU1X00_MAC_MIICTRL(x)         (*(volatile uint32_t*)(x + 0x14))
+#define AU1X00_MAC_MIIDATA(x)         (*(volatile uint32_t*)(x + 0x18))
+#define AU1X00_MAC_FLOWCTRL(x)        (*(volatile uint32_t*)(x + 0x1c))
+#define AU1X00_MAC_VLAN1(x)           (*(volatile uint32_t*)(x + 0x20))
+#define AU1X00_MAC_VLAN2(x)           (*(volatile uint32_t*)(x + 0x24))
+#define AU1X00_MAC_EN0                (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x0))
+#define AU1X00_MAC_EN1                (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x4))
+#define AU1X00_MAC_DMA_TX0_ADDR(x)    (*(volatile uint32_t*)(x + 0x000))
+#define AU1X00_MAC_DMA_TX1_ADDR(x)    (*(volatile uint32_t*)(x + 0x010))
+#define AU1X00_MAC_DMA_TX2_ADDR(x)    (*(volatile uint32_t*)(x + 0x020))
+#define AU1X00_MAC_DMA_TX3_ADDR(x)    (*(volatile uint32_t*)(x + 0x030))
+#define AU1X00_MAC_DMA_RX0_ADDR(x)    (*(volatile uint32_t*)(x + 0x100))
+#define AU1X00_MAC_DMA_RX1_ADDR(x)    (*(volatile uint32_t*)(x + 0x110))
+#define AU1X00_MAC_DMA_RX2_ADDR(x)    (*(volatile uint32_t*)(x + 0x120))
+#define AU1X00_MAC_DMA_RX3_ADDR(x)    (*(volatile uint32_t*)(x + 0x130))
+
+typedef struct {
+    volatile uint32_t stat;
+    volatile uint32_t addr;
+    uint32_t _rsv0;
+    uint32_t _rsv1;
+} au1x00_macdma_rx_t;
+
+
+typedef struct {
+    volatile uint32_t stat;
+    volatile uint32_t addr;
+    volatile uint32_t len;
+    uint32_t _rsv0;
+} au1x00_macdma_tx_t;
+
+#define AU1X00_MAC_CTRL_RA                (bit(31))
+#define AU1X00_MAC_CTRL_EM                (bit(30))
+#define AU1X00_MAC_CTRL_DO                (bit(23))
+#define AU1X00_MAC_CTRL_LM(x)             ((x) << 21)
+#define AU1X00_MAC_CTRL_LM_NORMAL         ((0) << 21)
+#define AU1X00_MAC_CTRL_LM_INTERNAL       ((1) << 21)
+#define AU1X00_MAC_CTRL_LM_EXTERNAL       ((2) << 21)
+#define AU1X00_MAC_CTRL_F                 (bit(20))
+#define AU1X00_MAC_CTRL_PM                (bit(19))
+#define AU1X00_MAC_CTRL_PR                (bit(18))
+#define AU1X00_MAC_CTRL_IF                (bit(17))
+#define AU1X00_MAC_CTRL_PB                (bit(16))
+#define AU1X00_MAC_CTRL_HO                (bit(15))
+#define AU1X00_MAC_CTRL_HP                (bit(13))
+#define AU1X00_MAC_CTRL_LC                (bit(12))
+#define AU1X00_MAC_CTRL_DB                (bit(11))
+#define AU1X00_MAC_CTRL_DR                (bit(10))
+#define AU1X00_MAC_CTRL_AP                (bit(8))
+#define AU1X00_MAC_CTRL_BL(x)             ((x) << 6)
+#define AU1X00_MAC_CTRL_DC                (bit(5))
+#define AU1X00_MAC_CTRL_TE                (bit(3))
+#define AU1X00_MAC_CTRL_RE                (bit(2))
+
+#define AU1X00_MAC_EN_JP                  (bit(6))
+#define AU1X00_MAC_EN_E2                  (bit(5))
+#define AU1X00_MAC_EN_E1                  (bit(4))
+#define AU1X00_MAC_EN_C                   (bit(3))
+#define AU1X00_MAC_EN_TS                  (bit(2))
+#define AU1X00_MAC_EN_E0                  (bit(1))
+#define AU1X00_MAC_EN_CE                  (bit(0))
+
+#define AU1X00_MAC_ADDRHIGH_MASK          (0xffff)_
+#define AU1X00_MAC_MIICTRL_PHYADDR(x)     ((x & 0x1f) << 11)
+#define AU1X00_MAC_MIICTRL_MIIREG(x)      ((x & 0x1f) << 6)
+#define AU1X00_MAC_MIICTRL_MW             (bit(1))
+#define AU1X00_MAC_MIICTRL_MB             (bit(0))
+#define AU1X00_MAC_MIIDATA_MASK           (0xffff)
+#define AU1X00_MAC_FLOWCTRL_PT(x)         (((x) & 0xffff) << 16)
+#define AU1X00_MAC_FLOWCTRL_PC            (bit(2))
+#define AU1X00_MAC_FLOWCTRL_FE            (bit(1))
+#define AU1X00_MAC_FLOWCTRL_FB            (bit(0))
+
+#define AU1X00_MAC_DMA_RXSTAT_MI          (bit(31))
+#define AU1X00_MAC_DMA_RXSTAT_PF          (bit(30))
+#define AU1X00_MAC_DMA_RXSTAT_FF          (bit(29))
+#define AU1X00_MAC_DMA_RXSTAT_BF          (bit(28))
+#define AU1X00_MAC_DMA_RXSTAT_MF          (bit(27))
+#define AU1X00_MAC_DMA_RXSTAT_UC          (bit(26))
+#define AU1X00_MAC_DMA_RXSTAT_CF          (bit(25))
+#define AU1X00_MAC_DMA_RXSTAT_LE          (bit(24))
+#define AU1X00_MAC_DMA_RXSTAT_V2          (bit(23))
+#define AU1X00_MAC_DMA_RXSTAT_V1          (bit(22))
+#define AU1X00_MAC_DMA_RXSTAT_CR          (bit(21))
+#define AU1X00_MAC_DMA_RXSTAT_DB          (bit(20))
+#define AU1X00_MAC_DMA_RXSTAT_ME          (bit(19))
+#define AU1X00_MAC_DMA_RXSTAT_FT          (bit(18))
+#define AU1X00_MAC_DMA_RXSTAT_CS          (bit(17))
+#define AU1X00_MAC_DMA_RXSTAT_FL          (bit(16))
+#define AU1X00_MAC_DMA_RXSTAT_RF          (bit(15))
+#define AU1X00_MAC_DMA_RXSTAT_WT          (bit(14))
+#define AU1X00_MAC_DMA_RXSTAT_LEN(x)      ((x) & 0x3fff)
+#define AU1X00_MAC_DMA_RXADDR_ADDR(x)     ((x) & ~0x1f)
+#define AU1X00_MAC_DMA_RXADDR_CB_MASK     (0x3 << 0x2)
+#define AU1X00_MAC_DMA_RXADDR_DN          (bit(1))
+#define AU1X00_MAC_DMA_RXADDR_EN          (bit(0))
+
+
+#define AU1X00_MAC_DMA_TXSTAT_PR          (bit(31))
+#define AU1X00_MAC_DMA_TXSTAT_CC_MASK     (0xf << 10)
+#define AU1X00_MAC_DMA_TXSTAT_LO          (bit(9))
+#define AU1X00_MAC_DMA_TXSTAT_DF          (bit(8))
+#define AU1X00_MAC_DMA_TXSTAT_UR          (bit(7))
+#define AU1X00_MAC_DMA_TXSTAT_EC          (bit(6))
+#define AU1X00_MAC_DMA_TXSTAT_LC          (bit(5))
+#define AU1X00_MAC_DMA_TXSTAT_ED          (bit(4))
+#define AU1X00_MAC_DMA_TXSTAT_LS          (bit(3))
+#define AU1X00_MAC_DMA_TXSTAT_NC          (bit(2))
+#define AU1X00_MAC_DMA_TXSTAT_JT          (bit(1))
+#define AU1X00_MAC_DMA_TXSTAT_FA          (bit(0))
+#define AU1X00_MAC_DMA_TXADDR_ADDR(x)     ((x) & ~0x1f)
+#define AU1X00_MAC_DMA_TXADDR_CB_MASK     (0x3 << 0x2)
+#define AU1X00_MAC_DMA_TXADDR_DN          (bit(1))
+#define AU1X00_MAC_DMA_TXADDR_EN          (bit(0))
+
+
+
+typedef struct {
+    volatile uint32_t rxdata;
+    volatile uint32_t txdata;
+    volatile uint32_t inten;
+    volatile uint32_t intcause;
+    volatile uint32_t fifoctrl;
+    volatile uint32_t linectrl;
+    volatile uint32_t mdmctrl;
+    volatile uint32_t linestat;
+    volatile uint32_t mdmstat;
+    volatile uint32_t clkdiv;
+    volatile uint32_t _resv[54];
+    volatile uint32_t enable;
+} au1x00_uart_t;
+
+extern au1x00_uart_t *uart0;
+extern au1x00_uart_t *uart3;
+
+void static inline au_sync(void)
+{
+	__asm__ volatile ("sync");
+}
+
+
+extern void mips_default_isr( int vector );
+
+/* Generate a software interrupt */
+extern int assert_sw_irq(uint32_t irqnum);
+
+/* Clear a software interrupt */
+extern int negate_sw_irq(uint32_t irqnum);
+
+#endif
Index: bsps/mips/include/libcpu/isr_entries.h
===================================================================
--- bsps/mips/include/libcpu/isr_entries.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/libcpu/isr_entries.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,39 @@
+/**
+ *  @file
+ *  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _ISR_ENTRIES_H
+#define _ISR_ENTRIES_H 1
+
+#include <rtems/score/cpuimpl.h>
+
+extern void mips_install_isr_entries( void );
+extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+
+#if __mips == 1
+extern void exc_utlb_code(void);
+extern void exc_dbg_code(void);
+extern void exc_norm_code(void);
+#elif __mips == 32
+extern void exc_tlb_code(void);
+extern void exc_xtlb_code(void);
+extern void exc_cache_code(void);
+extern void exc_norm_code(void);
+#elif __mips == 3
+extern void exc_tlb_code(void);
+extern void exc_xtlb_code(void);
+extern void exc_cache_code(void);
+extern void exc_norm_code(void);
+#endif
+
+#endif
Index: bsps/mips/include/libcpu/rm5231.h
===================================================================
--- bsps/mips/include/libcpu/rm5231.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/libcpu/rm5231.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,19 @@
+/**
+ *  @file
+ *  
+ *  MIPS RM5231 specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __RM5231_h
+#define __RM5231_h
+
+#endif
Index: bsps/mips/include/libcpu/tx3904.h
===================================================================
--- bsps/mips/include/libcpu/tx3904.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/libcpu/tx3904.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,45 @@
+/**
+ *  @file
+ *  
+ *  MIPS Tx3904 specific information
+ *
+ *  NOTE: This is far from complete.  --joel (13 Dec 2000)
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __TX3904_h
+#define __TX3904_h
+
+/*
+ *  Timer Base Addresses and Offsets
+ */
+
+#define TX3904_TIMER0_BASE 0xFFFFF000
+#define TX3904_TIMER1_BASE 0xFFFFF100
+#define TX3904_TIMER2_BASE 0xFFFFF200
+
+#define TX3904_TIMER_TCR  0x00
+#define TX3904_TIMER_TISR 0x04
+#define TX3904_TIMER_CPRA 0x08
+#define TX3904_TIMER_CPRB 0x0C
+#define TX3904_TIMER_ITMR 0x10
+#define TX3904_TIMER_CCDR 0x20
+#define TX3904_TIMER_PGMR 0x30
+#define TX3904_TIMER_WTMR 0x40
+#define TX3904_TIMER_TRR  0xF0
+
+#define TX3904_TIMER_READ( _base, _register ) \
+  *((volatile uint32_t*)((_base) + (_register)))
+
+#define TX3904_TIMER_WRITE( _base, _register, _value ) \
+  *((volatile uint32_t*)((_base) + (_register))) = (_value)
+
+#endif
Index: bsps/mips/include/libcpu/tx4925.h
===================================================================
--- bsps/mips/include/libcpu/tx4925.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/libcpu/tx4925.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,107 @@
+/**
+ *  @file
+ *  
+ *  MIPS Tx4925 specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __TX4925_h
+#define __TX4925_h
+
+#define TX4925_REG_BASE	0xFF1F0000
+
+
+/*
+ *  Configuration Registers
+ */
+#define TX4925_CFG_CCFG 0xE000		/* Chip Configuration Register */
+#define TX4925_CFG_REVID 0xE004		/* Chip Revision ID Register */
+#define TX4925_CFG_PCFG 0xE008		/* Pin Configuration Register */
+#define TX4925_CFG_TOEA 0xE00C		/* TimeOut Error Access Address Register */
+#define TX4925_CFG_PDNCTR 0xE010	/* Power Down Control Register */
+#define TX4925_CFG_GARBP 0xE018		/* GBUS Arbiter Priority Register */
+#define TX4925_CFG_TOCNT 0xE020		/* Timeout Count Register */
+#define TX4925_CFG_DRQCTR 0xE024		/* DMA Request Control Register */
+#define TX4925_CFG_CLKCTR 0xE028		/* Clock Control Register */
+#define TX4925_CFG_GARBC 0xE02C		/* GBUS Arbiter Control Register */
+#define TX4925_CFG_RAMP 0xE030		/* Register Address Mapping Register */
+
+/* Pin Configuration register bits */
+#define SELCHI	0x00100000
+#define SELTMR0 0x00000200
+
+
+/*
+ *  Timer Registers
+ */
+
+#define TX4925_TIMER0_BASE 0xF000
+#define TX4925_TIMER1_BASE 0xF100
+#define TX4925_TIMER2_BASE 0xF200
+
+#define TX4925_TIMER_TCR  0x00			/* Timer Control Register */
+#define TX4925_TIMER_TISR 0x04			/* Timer Interrupt Status Register */
+#define TX4925_TIMER_CPRA 0x08			/* Compare Register A */
+#define TX4925_TIMER_CPRB 0x0C			/* Compare Register B */
+#define TX4925_TIMER_ITMR 0x10			/* Interval Timer Mode Register */
+#define TX4925_TIMER_CCDR 0x20			/* Divide Cycle Register */
+#define TX4925_TIMER_PGMR 0x30			/* Pulse Generator Mode Register */
+#define TX4925_TIMER_WTMR 0x40			/* Reserved Register */
+#define TX4925_TIMER_TRR  0xF0			/* Timer Read Register */
+
+/* ITMR register bits */
+#define TIMER_CLEAR_ENABLE_MASK		0x1
+#define TIMER_INT_ENABLE_MASK	0x8000
+
+/* PGMR register bits */
+#define FFI			0x1
+#define TPIAE		0x4000
+#define TPIBE		0x8000
+
+/* TISR register bits */
+#define TIIS	0x1
+#define TPIAS	0x2
+#define TPIBS	0x4
+#define TWIS	0x8
+
+
+/*
+ *	Interrupt Controller Registers
+ */
+#define TX4925_IRQCTL_DEN 0xF600		/* Interrupt Detection Enable Register */
+#define TX4925_IRQCTL_DM0 0xF604		/* Interrupt Detection Mode Register 0 */
+#define TX4925_IRQCTL_DM1 0xF608		/* Interrupt Detection Mode Register 1 */
+#define TX4925_IRQCTL_LVL0 0xF610		/* Interrupt Level Register 0 */
+#define TX4925_IRQCTL_LVL1 0xF614		/* Interrupt Level Register 1 */
+#define TX4925_IRQCTL_LVL2 0xF618		/* Interrupt Level Register 2 */
+#define TX4925_IRQCTL_LVL3 0xF61C		/* Interrupt Level Register 3 */
+#define TX4925_IRQCTL_LVL4 0xF620		/* Interrupt Level Register 4 */
+#define TX4925_IRQCTL_LVL5 0xF624		/* Interrupt Level Register 5 */
+#define TX4925_IRQCTL_LVL6 0xF628		/* Interrupt Level Register 6 */
+#define TX4925_IRQCTL_LVL7 0xF62C		/* Interrupt Level Register 7 */
+#define TX4925_IRQCTL_MSK 0xF640		/* Interrupt Mask Register */
+#define TX4925_IRQCTL_EDC 0xF660		/* Interrupt Edge Detection Clear Register */
+#define TX4925_IRQCTL_PND 0xF680		/* Interrupt Pending Register */
+#define TX4925_IRQCTL_CS 0xF6A0			/* Interrupt Current Status Register */
+#define TX4925_IRQCTL_FLAG0 0xF510		/* Interrupt Request Flag Register 0 */
+#define TX4925_IRQCTL_FLAG1 0xF514		/* Interrupt Request Flag Register 1 */
+#define TX4925_IRQCTL_POL 0xF518		/* Interrupt Request Polarity Control Register */
+#define TX4925_IRQCTL_RCNT 0xF51C		/* Interrupt Request Control Register */
+#define TX4925_IRQCTL_MASKINT 0xF520	/* Interrupt Request Internal Interrupt Mask Register */
+#define TX4925_IRQCTL_MASKEXT 0xF524	/* Interrupt Request External Interrupt Mask Register */
+
+#define TX4925_REG_READ( _base, _register ) \
+  *((volatile uint32_t *)((_base) + (_register)))
+
+#define TX4925_REG_WRITE( _base, _register, _value ) \
+  *((volatile uint32_t *)((_base) + (_register))) = (_value)
+
+#endif
Index: bsps/mips/include/libcpu/tx4938.h
===================================================================
--- bsps/mips/include/libcpu/tx4938.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/include/libcpu/tx4938.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,191 @@
+/**
+ *  @file
+ *  
+ *  MIPS Tx4938 specific information
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __TX4938_h
+#define __TX4938_h
+
+#define TX4938_REG_BASE	0xFF1F0000
+
+/* PCI1 Registers */
+#define TX4938_PCI1_PCIID       0x7000
+#define TX4938_PCI1_PCISTATUS   0x7004
+#define TX4938_PCI1_PCICFG1     0x700c
+#define TX4938_PCI1_P2GM1PLBASE 0x7018
+#define TX4938_PCI1_P2GCFG      0x7090
+#define TX4938_PCI1_PBAREQPORT  0x7100
+#define TX4938_PCI1_PBACFG      0x7104
+#define TX4938_PCI1_G2PM0GBASE  0x7120
+#define TX4938_PCI1_G2PIOGBASE  0x7138
+#define TX4938_PCI1_G2PM0MASK   0x7140
+#define TX4938_PCI1_G2PIOMASK   0x714c
+#define TX4938_PCI1_G2PM0PBASE  0x7150
+#define TX4938_PCI1_G2PIOPBASE  0x7168
+#define TX4938_PCI1_PCICCFG     0x7170
+#define TX4938_PCI1_PCICSTATUS  0x7174
+#define TX4938_PCI1_P2GM1GBASE  0x7188
+#define TX4938_PCI1_G2PCFGADRS  0x71a0
+#define TX4938_PCI1_G2PCFGDATA  0x71a4
+
+/*
+ *  Configuration Registers
+ */
+#define TX4938_CFG_CCFG 0xE000		/* Chip Configuration Register */
+#define TX4938_CFG_REVID 0xE008		/* Chip Revision ID Register */
+#define TX4938_CFG_PCFG 0xE010		/* Pin Configuration Register */
+#define TX4938_CFG_TOEA 0xE018		/* TimeOut Error Access Address Register */
+#define TX4938_CFG_CLKCTR 0xE020		/* Clock Control Register */
+#define TX4938_CFG_GARBC 0xE030		/* GBUS Arbiter Control Register */
+#define TX4938_CFG_RAMP 0xE048		/* Register Address Mapping Register */
+
+/* Pin Configuration register bits */
+#define SELCHI	0x00100000
+#define SELTMR0 0x00000200
+
+
+/*
+ *  Timer Registers
+ */
+
+#define TX4938_TIMER0_BASE 0xF000
+#define TX4938_TIMER1_BASE 0xF100
+#define TX4938_TIMER2_BASE 0xF200
+
+#define TX4938_TIMER_TCR  0x00			/* Timer Control Register */
+#define TX4938_TIMER_TISR 0x04			/* Timer Interrupt Status Register */
+#define TX4938_TIMER_CPRA 0x08			/* Compare Register A */
+#define TX4938_TIMER_CPRB 0x0C			/* Compare Register B */
+#define TX4938_TIMER_ITMR 0x10			/* Interval Timer Mode Register */
+#define TX4938_TIMER_CCDR 0x20			/* Divide Cycle Register */
+#define TX4938_TIMER_PGMR 0x30			/* Pulse Generator Mode Register */
+#define TX4938_TIMER_WTMR 0x40			/* Reserved Register */
+#define TX4938_TIMER_TRR  0xF0			/* Timer Read Register */
+
+/* ITMR register bits */
+#define TIMER_CLEAR_ENABLE_MASK		0x1
+#define TIMER_INT_ENABLE_MASK	0x8000
+
+/* PGMR register bits */
+#define FFI			0x1
+#define TPIAE		0x4000
+#define TPIBE		0x8000
+
+/* TISR register bits */
+#define TIIS	0x1
+#define TPIAS	0x2
+#define TPIBS	0x4
+#define TWIS	0x8
+
+
+/*
+ *	Interrupt Controller Registers
+ */
+#define TX4938_IRQCTL_DEN 0xF600		/* Interrupt Detection Enable Register */
+#define TX4938_IRQCTL_DM0 0xF604		/* Interrupt Detection Mode Register 0 */
+#define TX4938_IRQCTL_DM1 0xF608		/* Interrupt Detection Mode Register 1 */
+#define TX4938_IRQCTL_LVL0 0xF610		/* Interrupt Level Register 0 */
+#define TX4938_IRQCTL_LVL1 0xF614		/* Interrupt Level Register 1 */
+#define TX4938_IRQCTL_LVL2 0xF618		/* Interrupt Level Register 2 */
+#define TX4938_IRQCTL_LVL3 0xF61C		/* Interrupt Level Register 3 */
+#define TX4938_IRQCTL_LVL4 0xF620		/* Interrupt Level Register 4 */
+#define TX4938_IRQCTL_LVL5 0xF624		/* Interrupt Level Register 5 */
+#define TX4938_IRQCTL_LVL6 0xF628		/* Interrupt Level Register 6 */
+#define TX4938_IRQCTL_LVL7 0xF62C		/* Interrupt Level Register 7 */
+#define TX4938_IRQCTL_MSK 0xF640		/* Interrupt Mask Register */
+#define TX4938_IRQCTL_EDC 0xF660		/* Interrupt Edge Detection Clear Register */
+#define TX4938_IRQCTL_PND 0xF680		/* Interrupt Pending Register */
+#define TX4938_IRQCTL_CS 0xF6A0			/* Interrupt Current Status Register */
+#define TX4938_IRQCTL_FLAG0 0xF510		/* Interrupt Request Flag Register 0 */
+#define TX4938_IRQCTL_FLAG1 0xF514		/* Interrupt Request Flag Register 1 */
+#define TX4938_IRQCTL_POL 0xF518		/* Interrupt Request Polarity Control Register */
+#define TX4938_IRQCTL_RCNT 0xF51C		/* Interrupt Request Control Register */
+#define TX4938_IRQCTL_MASKINT 0xF520	/* Interrupt Request Internal Interrupt Mask Register */
+#define TX4938_IRQCTL_MASKEXT 0xF524	/* Interrupt Request External Interrupt Mask Register */
+
+#define TX4938_REG_READ( _base, _register ) \
+  *((volatile uint32_t *)((_base) + (_register)))
+
+#define TX4938_REG_WRITE( _base, _register, _value ) \
+  *((volatile uint32_t *)((_base) + (_register))) = (_value)
+
+/************************************************************************
+ *      TX49 Register field encodings
+*************************************************************************/
+/******** reg: CCFG ********/
+/* field: PCIDIVMODE */
+#define TX4938_CCFG_SYSSP_SHF  6
+#define TX4938_CCFG_SYSSP_MSK  (MSK(2) << TX4938_CCFG_SYSSP_SHF)
+
+/* field: PCI1DMD */
+#define TX4938_CCFG_PCI1DMD_SHF  8
+#define TX4938_CCFG_PCI1DMD_MSK  (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
+
+/* field: PCIDIVMODE */
+#define TX4938_CCFG_PCIDIVMODE_SHF  10
+#define TX4938_CCFG_PCIDIVMODE_MSK  (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
+
+/* field: PCI1-66 */
+#define TX4938_CCFG_PCI166_SHF  21
+#define TX4938_CCFG_PCI166_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
+
+/* field: PCIMODE */
+#define TX4938_CCFG_PCIMODE_SHF  22
+#define TX4938_CCFG_PCIMODE_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
+
+/* field: BRDTY */
+#define TX4938_CCFG_BRDTY_SHF  36
+#define TX4938_CCFG_RRDTY_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
+
+/* field: BRDRV */
+#define TX4938_CCFG_BRDRV_SHF  32
+#define TX4938_CCFG_BRDRV_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
+
+/******** reg: CLKCTR ********/
+/* field: PCIC1RST */
+#define TX4938_CLKCTR_PCIC1RST_SHF  11
+#define TX4938_CLKCTR_PCIC1RST_MSK  (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
+
+/******** reg: PCISTATUS ********/
+/* field: MEMSP */
+#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
+#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
+
+/* field: BM */
+#define TX4938_PCI_PCISTATUS_BM_SHF    2
+#define TX4938_PCI_PCISTATUS_BM_MSK    (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
+
+/******** reg: PBACFG ********/
+/* field: RPBA */
+#define TX4938_PCI_PBACFG_RPBA_SHF     2
+#define TX4938_PCI_PBACFG_RPBA_MSK    (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
+
+/* field: PBAEN */
+#define TX4938_PCI_PBACFG_PBAEN_SHF    1
+#define TX4938_PCI_PBACFG_PBAEN_MSK   (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
+
+/******** reg: PCICFG ********/
+/* field: G2PM0EN */
+#define TX4938_PCI_PCICFG_G2PM0EN_SHF  6
+#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
+
+/* field: G2PIOEN */
+#define TX4938_PCI_PCICFG_G2PIOEN_SHF  5
+#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
+
+/* field: TCAR */
+#define TX4938_PCI_PCICFG_TCAR_SHF  4
+#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
+
+
+#endif
Index: bsps/mips/jmr3904/headers.am
===================================================================
--- bsps/mips/jmr3904/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/jmr3904/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,10 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/mips/jmr3904/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/mips/jmr3904/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/mips/jmr3904/include/bsp/irq.h
Index: bsps/mips/jmr3904/include/bsp.h
===================================================================
--- bsps/mips/jmr3904/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/jmr3904/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,37 @@
+/**
+ *  @file
+ *  
+ *  This include file contains some definitions specific to the
+ *  JMR3904 simulator in gdb.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_JMR3904_BSP_H
+#define LIBBSP_MIPS_JMR3904_BSP_H
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/tx3904.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: bsps/mips/jmr3904/include/bsp/irq.h
===================================================================
--- bsps/mips/jmr3904/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/jmr3904/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief jmr3904 interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_JMR3904_IRQ_H
+#define LIBBSP_MIPS_JMR3904_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ *  NOTE: Numbers 0-15 directly map to levels on the IRC.
+ *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
+ */
+
+  #define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
+  #define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
+  #define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
+  #define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
+  #define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
+  #define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
+  #define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
+  #define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
+  #define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
+  #define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
+  #define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
+  #define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
+  #define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
+  #define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
+  #define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
+  #define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
+  #define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
+  #define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
+  #define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
+  #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
+
+#define BSP_INTERRUPT_VECTOR_MAX TX3904_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */
Index: bsps/mips/jmr3904/include/tm27.h
===================================================================
--- bsps/mips/jmr3904/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/jmr3904/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,52 @@
+/**
+ *  @file
+ */
+
+/*
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ */
+
+#include <bsp/irq.h>
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+   rtems_interrupt_handler_install( \
+      TX3904_IRQ_TMR0, "benchmark", 0, \
+      (rtems_interrupt_handler)handler, NULL );
+
+#define Cause_tm27_intr() \
+  do { \
+    uint32_t   _clicks = 20; \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
+    *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
+  } while(0)
+
+#define Clear_tm27_intr() \
+  do { \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR,   0x00 ); \
+  } while(0)
+
+#define Lower_tm27_intr() \
+  mips_enable_in_interrupt_mask( 0xff01 );
+
+#endif
Index: bsps/mips/malta/headers.am
===================================================================
--- bsps/mips/malta/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/malta/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,11 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/mips/malta/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/mips/malta/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/mips/malta/include/bsp/irq.h
+include_bsp_HEADERS += ../../../../../../bsps/mips/malta/include/bsp/pci.h
Index: bsps/mips/malta/include/bsp.h
===================================================================
--- bsps/mips/malta/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/malta/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,113 @@
+/**
+ *  @file
+ *
+ *  This include file contains some definitions specific to the
+ *  MIPS Malta Board.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_MALTA_BSP_H
+#define LIBBSP_MIPS_MALTA_BSP_H
+
+#ifndef ASM
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+#define REVISION_REGISTER_ADDRESS  0x1fc00010
+#define PRORV_MASK       0x0000000f   /* 4 bit Product Revision */
+#define PROID_MASK       0x000000f0   /* 4 bit Product ID */
+#define CORRV_MASK       0x00000300   /* 2 bit Core Board Revision */
+#define CORID_MASK       0x0000fc00   /* 6 bit Core Board ID */
+#define FPGRV_MASK       0x00ff0000   /* 8 bit CBUS FPGA Revision */
+#define BSP_8259_BASE_ADDRESS    (0x18000000UL | 0xa0000000UL)
+#define BSP_PCI_BASE_ADDRESS     (0x1be00000UL | 0xa0000000UL)
+#define BSP_NIC_IO_BASE          (0x10000000UL | 0xa0000000UL)
+#define PCI0_IO_BASE             (0x18000000UL | 0xa0000000UL)
+#define BSP_NIC_MEM_BASE         (0x00000000UL | 0xa0000000UL)
+
+/* functions */
+#define WRITE_PROTECTED_UINT8( _addr, _value ) \
+        do { \
+          volatile uint8_t *_ptr = _addr | 0x80000000; \
+          *_ptr = _value; \
+        }
+#define WRITE_PROTECTED_UINT16( _addr, _value ) \
+        do { \
+          volatile uint16_t *_ptr = _addr | 0x80000000; \
+          *_ptr = _value; \
+        }
+#define WRITE_PROTECTED_UINT32( _addr, _value ) \
+        do { \
+          volatile uint32_t *_ptr = _addr | 0x80000000; \
+          *_ptr = _value; \
+        }
+#define READ_PROTECTED_UINT8( _addr, _value ) \
+        do { \
+          volatile uint8_t *_ptr = _addr | 0x80000000; \
+         _value = *_ptr; \
+        }
+#define READ_PROTECTED_UINT16( _addr, _value ) \
+        do { \
+          volatile uint16_t *_ptr = _addr | 0x80000000; \
+         _value = *_ptr; \
+        }
+#define READ_PROTECTED_UINT32( _addr, _value ) \
+        do { \
+          volatile uint32_t *_ptr = _addr | 0x80000000; \
+         _value = *_ptr; \
+        }
+
+#define READ_UINT8( _register_, _value_ ) \
+        ((_value_) = *((volatile unsigned char *)(_register_)))
+
+#define WRITE_UINT8( _register_, _value_ ) \
+        (*((volatile unsigned char *)(_register_)) = (_value_))
+
+#define READ_UINT16( _register_, _value_ ) \
+     ((_value_) = *((volatile unsigned short *)(_register_)))
+
+#define WRITE_UINT16( _register_, _value_ ) \
+     (*((volatile unsigned short *)(_register_)) = (_value_))
+
+void simple_out_32(uint32_t base, uint32_t addr, uint32_t val);
+void simple_out_le32(uint32_t base, uint32_t addr, uint32_t val);
+uint8_t simple_in_8( uint32_t base, uint32_t addr );
+void simple_out_8( uint32_t base, uint32_t addr, uint8_t val );
+int16_t simple_in_le16( uint32_t base, uint32_t addr );
+int16_t simple_in_16( uint32_t base, uint32_t addr );
+uint32_t simple_in_le32( uint32_t base, uint32_t addr );
+uint32_t simple_in_32( uint32_t base, uint32_t addr );
+void simple_out_le16( uint32_t base, uint32_t addr, uint16_t val );
+void simple_out_16( uint32_t base, uint32_t addr, uint16_t val );
+
+/*
+ * Prototypes for methods called from .S for dependency tracking
+ */
+void init_tlb(void);
+void resettlb(int i);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif
Index: bsps/mips/malta/include/bsp/irq.h
===================================================================
--- bsps/mips/malta/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/malta/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Malta Interrupt Definitions
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_MALTA_IRQ_H
+#define LIBBSP_MIPS_MALTA_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ *  NOTE: Numbers 0-15 directly map to levels on the IRC.
+ *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
+ */
+#define MALTA_CPU_INT_START           MIPS_INTERRUPT_BASE+0
+#define MALTA_CPU_INT_SW0             MALTA_CPU_INT_START+0
+#define MALTA_CPU_INT_SW2             MALTA_CPU_INT_START+1
+#define MALTA_CPU_INT0                MALTA_CPU_INT_START+2
+#define MALTA_CPU_INT1                MALTA_CPU_INT_START+3
+#define MALTA_CPU_INT2                MALTA_CPU_INT_START+4
+#define MALTA_CPU_INT3                MALTA_CPU_INT_START+5
+#define MALTA_CPU_INT4                MALTA_CPU_INT_START+6
+#define MALTA_CPU_INT5                MALTA_CPU_INT_START+7
+#define MALTA_CPU_INT_LAST            MALTA_CPU_INT5
+
+#define MALTA_SB_IRQ_START            MALTA_CPU_INT_LAST+1
+#define MALTA_SB_IRQ_0                MALTA_SB_IRQ_START+0
+#define MALTA_SB_IRQ_1                MALTA_SB_IRQ_START+1
+#define MALTA_SB_IRQ_2                MALTA_SB_IRQ_START+2
+#define MALTA_SB_IRQ_3                MALTA_SB_IRQ_START+3
+#define MALTA_SB_IRQ_4                MALTA_SB_IRQ_START+4
+#define MALTA_SB_IRQ_5                MALTA_SB_IRQ_START+5
+#define MALTA_SB_IRQ_6                MALTA_SB_IRQ_START+6
+#define MALTA_SB_IRQ_7                MALTA_SB_IRQ_START+7
+#define MALTA_SB_IRQ_8                MALTA_SB_IRQ_START+8
+#define MALTA_SB_IRQ_9                MALTA_SB_IRQ_START+9
+#define MALTA_SB_IRQ_10               MALTA_SB_IRQ_START+10
+#define MALTA_SB_IRQ_11               MALTA_SB_IRQ_START+11
+#define MALTA_SB_IRQ_12               MALTA_SB_IRQ_START+12
+#define MALTA_SB_IRQ_13               MALTA_SB_IRQ_START+13
+#define MALTA_SB_IRQ_14               MALTA_SB_IRQ_START+14
+#define MALTA_SB_IRQ_15               MALTA_SB_IRQ_START+15
+#define MALTA_SB_IRQ_LAST             MALTA_SB_IRQ_15
+
+#define MALTA_PCI_ADP_START           MALTA_SB_IRQ_LAST+1
+#define MALTA_PCI_ADP20               MALTA_PCI_ADP_START+0
+#define MALTA_PCI_ADP21               MALTA_PCI_ADP_START+1
+#define MALTA_PCI_ADP22               MALTA_PCI_ADP_START+2
+#define MALTA_PCI_ADP27               MALTA_PCI_ADP_START+3
+#define MALTA_PCI_ADP28               MALTA_PCI_ADP_START+4
+#define MALTA_PCI_ADP29               MALTA_PCI_ADP_START+5
+#define MALTA_PCI_ADP30               MALTA_PCI_ADP_START+6
+#define MALTA_PCI_ADP31               MALTA_PCI_ADP_START+7
+#define MALTA_PCI_ADP_LAST            MALTA_PCI_ADP31
+#
+
+#define BSP_INTERRUPT_VECTOR_MAX   MALTA_PCI_ADP_LAST
+
+/*
+ * Redefine interrupts with more descriptive names.
+ * The Generic ones above match the hardware name,
+ * where these match the device name.
+ */
+#define MALTA_INT_SOUTHBRIDGE_INTR             MALTA_CPU_INT0
+#define MALTA_INT_SOUTHBRIDGE_SMI              MALTA_CPU_INT1
+#define MALTA_INT_TTY2                         MALTA_CPU_INT2
+#define MALTA_INT_COREHI                       MALTA_CPU_INT3
+#define MALTA_INT_CORELO                       MALTA_CPU_INT4
+#define MALTA_INT_TICKER                       MALTA_CPU_INT5
+
+#define MALTA_IRQ_TIMER_SOUTH_BRIDGE           MALTA_SB_IRQ_0
+#define MALTA_IRQ_KEYBOARD_SUPERIO             MALTA_SB_IRQ_1
+#define MALTA_IRQ_RESERVED1_SOUTH_BRIDGE       MALTA_SB_IRQ_2
+#define MALTA_IRQ_TTY1                         MALTA_SB_IRQ_3
+#define MALTA_IRQ_TTY0                         MALTA_SB_IRQ_4
+#define MALTA_IRQ_NOT_USED                     MALTA_SB_IRQ_5
+#define MALTA_IRQ_FLOPPY_SUPERIO               MALTA_SB_IRQ_6
+#define MALTA_IRQ_PARALLEL_PORT_SUPERIO        MALTA_SB_IRQ_7
+#define MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE  MALTA_SB_IRQ_8
+#define MALTA_IRQ_I2C_SOUTH_BRIDGE             MALTA_SB_IRQ_9
+/* PCI A, PCI B (including Ethernet) PCI slot 1..4, Ethernet */
+#define MALTA_IRQ_PCI_A_B                      MALTA_SB_IRQ_10
+/* PCI slot 1..4 (audio, USB)  */
+#define MALTA_IRQ_PCI_C_D                      MALTA_SB_IRQ_11
+#define MALTA_IRQ_MOUSE_SUPERIO                MALTA_SB_IRQ_12
+#define MALTA_IRQ_RESERVED2_SOUTH_BRIDGE       MALTA_SB_IRQ_13
+#define MALTA_IRQ_PRIMARY_IDE                  MALTA_SB_IRQ_14
+#define MALTA_IRQ_SECONDARY_IDE                MALTA_SB_IRQ_15
+#define MALTA_IRQ_SOUTH_BRIDGE    MALTA_PCI_ADP20
+#define MALTA_IRQ_ETHERNET        MALTA_IRQ_PCI_A_B
+#define MALTA_IRQ_AUDIO           MALTA_PCI_ADP22
+#define MALTA_IRQ_CORE_CARD       MALTA_PCI_ADP27
+#define MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28
+#define MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29
+#define MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30
+#define MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31
+
+#ifndef ASM
+
+#endif /* ASM */
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_MALTA_IRQ_H */
Index: bsps/mips/malta/include/bsp/pci.h
===================================================================
--- bsps/mips/malta/include/bsp/pci.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/malta/include/bsp/pci.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,139 @@
+/**
+ *  @file
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ *
+ *	PCI defines and function prototypes
+ *	Copyright 1994, Drew Eckhardt
+ *	Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+ *
+ *	For more information, please consult the following manuals (look at
+ *	http://www.pcisig.com/ for how to get them):
+ *
+ *	PCI BIOS Specification
+ *	PCI Local Bus Specification
+ *	PCI to PCI Bridge Specification
+ *	PCI System Design Guide
+ */
+
+#ifndef BSP_PCI_H
+#define BSP_PCI_H
+
+#include <rtems/pci.h>
+#include <bsp.h>
+#include <stdio.h>
+
+struct _pin_routes
+{
+      int pin, int_name[4];
+};
+struct _int_map
+{
+      int bus, slot, opts;
+      struct _pin_routes pin_route[5];
+};
+struct pcibridge
+{
+  int bus;
+  int slot;
+};
+
+/* If there's a conflict between a name in the routing table and
+ * what's already set on the device, reprogram the device setting
+ * to reflect int_name[0] for the routing table entry
+ */
+#define PCI_FIXUP_OPT_OVERRIDE_NAME	(1<<0)
+
+void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) );
+
+/* FIXME: This probably belongs into rtems/pci.h */
+extern unsigned char pci_bus_count();
+
+int indirect_pci_read_config_byte(
+  unsigned char bus,
+  unsigned char slot,
+  unsigned char function,
+  unsigned char offset,
+  uint8_t       *val
+);
+
+int indirect_pci_read_config_word(
+  unsigned char bus,
+  unsigned char slot,
+  unsigned char function,
+  unsigned char offset,
+  uint16_t      *val
+);
+
+int indirect_pci_read_config_dword(
+  unsigned char bus,
+  unsigned char slot,
+  unsigned char function,
+  unsigned char offset,
+  uint32_t *val
+);
+
+int indirect_pci_write_config_byte(
+  unsigned char bus,
+  unsigned char slot,
+  unsigned char function,
+  unsigned char offset,
+  uint8_t       val
+);
+
+int indirect_pci_write_config_word(
+  unsigned char bus,
+  unsigned char slot,
+  unsigned char function,
+  unsigned char offset,
+  uint16_t      val
+);
+
+int indirect_pci_write_config_dword(
+  unsigned char bus,
+  unsigned char slot,
+  unsigned char function,
+  unsigned char offset,
+  uint32_t      val
+);
+
+/* Can these be moved to the rtems pci.h? */
+int FindPCIbridge( int mybus, struct pcibridge *pb );
+
+const pci_config_access_functions pci_indirect_functions;
+
+void     pci_out_le32( uint32_t base, uint32_t addr, uint32_t val);
+void     pci_out_32( uint32_t base, uint32_t addr, uint32_t val);
+uint8_t  pci_in_8    ( uint32_t base, uint32_t addr );
+int16_t  pci_in_le16 ( uint32_t base, uint32_t addr );
+uint32_t pci_in_le32 ( uint32_t base, uint32_t addr );
+int16_t  pci_in_16 ( uint32_t base, uint32_t addr );
+uint32_t pci_in_32 ( uint32_t base, uint32_t addr );
+void     pci_out_8   ( uint32_t base, uint32_t addr, uint8_t val );
+void     pci_out_le16( uint32_t base, uint32_t addr, uint16_t val );
+void     pci_out_16( uint32_t base, uint32_t addr, uint16_t val );
+void     pci_out_32  ( uint32_t base, uint32_t addr, uint32_t val);
+
+#define out_32(_addr, _val)   pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val)
+#define out_le32(_addr, _val) pci_out_le32(BSP_PCI_BASE_ADDRESS, _addr, _val)
+#define out_32(_addr, _val)   pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val)
+#define in_8(_addr)           pci_in_8( BSP_PCI_BASE_ADDRESS, _addr )
+#define in_le16(_addr)        pci_in_le16( BSP_PCI_BASE_ADDRESS, _addr )
+#define in_le32(_addr)        pci_in_le32( BSP_PCI_BASE_ADDRESS, _addr )
+#define in_16(_addr)          pci_in_16( BSP_PCI_BASE_ADDRESS, _addr )
+#define in_32(_addr)          pci_in_32( BSP_PCI_BASE_ADDRESS, _addr )
+#define out_8(_addr,_val)     pci_out_8( BSP_PCI_BASE_ADDRESS, _addr, _val )
+#define out_le16(_addr,_val)  pci_out_le16( BSP_PCI_BASE_ADDRESS, _addr, _val )
+#define out_16(_addr,_val)    pci_out_16( BSP_PCI_BASE_ADDRESS, _addr, _val )
+
+#endif /* BSP_PCI_H */
Index: bsps/mips/malta/include/tm27.h
===================================================================
--- bsps/mips/malta/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/malta/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1 @@
+#include <rtems/tm27-default.h>
Index: bsps/mips/rbtx4925/headers.am
===================================================================
--- bsps/mips/rbtx4925/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4925/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,10 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/mips/rbtx4925/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/mips/rbtx4925/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/mips/rbtx4925/include/bsp/irq.h
Index: bsps/mips/rbtx4925/include/bsp.h
===================================================================
--- bsps/mips/rbtx4925/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4925/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,46 @@
+/**
+ *  @file
+ *  
+ *  This include file contains some definitions specific to the RBTX4925.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_RBTX4925_BSP_H
+#define LIBBSP_MIPS_RBTX4925_BSP_H
+
+#ifndef ASM
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/tx4925.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+/*
+ * Prototypes for methods called from .S for dependency tracking
+ */
+void init_tlb(void);
+void resettlb(int i);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif
Index: bsps/mips/rbtx4925/include/bsp/irq.h
===================================================================
--- bsps/mips/rbtx4925/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4925/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_TX4925_IRQ_H
+#define LIBBSP_MIPS_TX4925_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ */
+#define BSP_INTERRUPT_VECTOR_MIN   0
+#define TX4925_IRQ_RSV1        MIPS_INTERRUPT_BASE+0
+#define TX4925_IRQ_WTE         MIPS_INTERRUPT_BASE+1
+#define TX4925_IRQ_INT0        MIPS_INTERRUPT_BASE+2
+#define TX4925_IRQ_INT1        MIPS_INTERRUPT_BASE+3
+#define TX4925_IRQ_INT2        MIPS_INTERRUPT_BASE+4
+#define TX4925_IRQ_INT3        MIPS_INTERRUPT_BASE+5
+#define TX4925_IRQ_INT4        MIPS_INTERRUPT_BASE+6
+#define TX4925_IRQ_INT5        MIPS_INTERRUPT_BASE+7
+#define TX4925_IRQ_INT6        MIPS_INTERRUPT_BASE+8
+#define TX4925_IRQ_INT7        MIPS_INTERRUPT_BASE+9
+#define TX4925_IRQ_RSV2        MIPS_INTERRUPT_BASE+10
+#define TX4925_IRQ_NAND        MIPS_INTERRUPT_BASE+11
+#define TX4925_IRQ_SIO0        MIPS_INTERRUPT_BASE+12
+#define TX4925_IRQ_SIO1        MIPS_INTERRUPT_BASE+13
+#define TX4925_IRQ_DMAC0       MIPS_INTERRUPT_BASE+14
+#define TX4925_IRQ_DMAC1       MIPS_INTERRUPT_BASE+15
+#define TX4925_IRQ_DMAC2       MIPS_INTERRUPT_BASE+16
+#define TX4925_IRQ_DMAC3       MIPS_INTERRUPT_BASE+17
+#define TX4925_IRQ_IRC         MIPS_INTERRUPT_BASE+18
+#define TX4925_IRQ_PDMAC       MIPS_INTERRUPT_BASE+19
+#define TX4925_IRQ_PCIC        MIPS_INTERRUPT_BASE+20
+#define TX4925_IRQ_TMR0        MIPS_INTERRUPT_BASE+21
+#define TX4925_IRQ_TMR1        MIPS_INTERRUPT_BASE+22
+#define TX4925_IRQ_TMR2        MIPS_INTERRUPT_BASE+23
+#define TX4925_IRQ_SPI         MIPS_INTERRUPT_BASE+24
+#define TX4925_IRQ_RTC         MIPS_INTERRUPT_BASE+25
+#define TX4925_IRQ_ACLC        MIPS_INTERRUPT_BASE+26
+#define TX4925_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
+#define TX4925_IRQ_CHI         MIPS_INTERRUPT_BASE+28
+#define TX4925_IRQ_PCIERR      MIPS_INTERRUPT_BASE+29
+#define TX4925_IRQ_PCIPME      MIPS_INTERRUPT_BASE+30
+#define TX4925_IRQ_RSV3        MIPS_INTERRUPT_BASE+31
+
+#define TX4925_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
+#define TX4925_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
+#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
+
+#define BSP_INTERRUPT_VECTOR_MAX TX4925_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_ TX4925_IRQ_H */
Index: bsps/mips/rbtx4925/include/tm27.h
===================================================================
--- bsps/mips/rbtx4925/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4925/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1 @@
+#include <rtems/tm27-default.h>
Index: bsps/mips/rbtx4938/headers.am
===================================================================
--- bsps/mips/rbtx4938/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4938/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,10 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/mips/rbtx4938/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/mips/rbtx4938/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/mips/rbtx4938/include/bsp/irq.h
Index: bsps/mips/rbtx4938/include/bsp.h
===================================================================
--- bsps/mips/rbtx4938/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4938/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,46 @@
+/**
+ *  @file
+ *  
+ *  This include file contains some definitions specific to the RBTX4938.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_RBTX4938_BSP_H
+#define LIBBSP_MIPS_RBTX4938_BSP_H
+
+#ifndef ASM
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/tx4938.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+/*
+ * Prototypes for methods called from .S for dependency tracking
+ */
+void init_tlb(void);
+void resettlb(int i);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif
Index: bsps/mips/rbtx4938/include/bsp/irq.h
===================================================================
--- bsps/mips/rbtx4938/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4938/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_TX4938_IRQ_H
+#define LIBBSP_MIPS_TX4938_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ */
+#define BSP_INTERRUPT_VECTOR_MIN   0
+#define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0
+#define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1
+#define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2
+#define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3
+#define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4
+#define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5
+#define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6
+#define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7
+#define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8
+#define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9
+#define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10
+#define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11
+#define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12
+#define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13
+#define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14
+#define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15
+#define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16
+#define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17
+#define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18
+#define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19
+#define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20
+#define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21
+#define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22
+#define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23
+#define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24
+#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25
+#define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26
+#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
+#define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28
+#define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29
+#define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30
+#define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31
+
+#define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
+#define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
+#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
+
+#define BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */
Index: bsps/mips/rbtx4938/include/tm27.h
===================================================================
--- bsps/mips/rbtx4938/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/mips/rbtx4938/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1 @@
+#include <rtems/tm27-default.h>
