Index: bsps/m68k/mcf5206elite/headers.am
===================================================================
--- bsps/m68k/mcf5206elite/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,10 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/ds1307.h
+include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/i2c.h
+include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/i2cdrv.h
+include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/nvram.h
+include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/tm27.h
Index: bsps/m68k/mcf5206elite/include/bsp.h
===================================================================
--- bsps/m68k/mcf5206elite/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,181 @@
+/*
+ * Board Support Package for MCF5206eLITE evaluation board
+ * BSP definitions
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_M68K_MCF5206ELITE_BSP_H
+#define LIBBSP_M68K_MCF5206ELITE_BSP_H
+
+#include "mcf5206/mcf5206e.h"
+
+/*** Board resources allocation ***/
+
+/*
+ * To achieve some compatibility with dBUG monitor, we use the same
+ * memory resources allocation as it is used in dBUG.
+ *
+ * If this definitions will be changed, change the linker script also.
+ */
+
+/* Memory mapping */
+/* CS0: Boot Flash */
+#define BSP_MEM_ADDR_FLASH    (0xFFE00000)
+#define BSP_MEM_SIZE_FLASH    (1*1024*1024)
+#define BSP_MEM_MASK_FLASH    (MCF5206E_CSMR_MASK_1M)
+
+/* CS2: External SRAM */
+#define BSP_MEM_ADDR_ESRAM    (0x30000000)
+#define BSP_MEM_SIZE_ESRAM    (1*1024*1024)
+#define BSP_MEM_MASK_ESRAM    (MCF5206E_CSMR_MASK_1M)
+
+/* CS3: General-Purpose I/O register */
+#define BSP_MEM_ADDR_GPIO     (0x40000000)
+#define BSP_MEM_SIZE_GPIO     (64*1024)
+#define BSP_MEM_MASK_GPIO     (MCF5206E_CSMR_MASK_64K)
+
+/* DRAM0: Dynamic RAM */
+#define BSP_MEM_ADDR_DRAM     (0x00000000)
+#define BSP_MEM_SIZE_DRAM     (16*1024*1024)
+#define BSP_MEM_MASK_DRAM     (MCF5206E_DCMR_MASK_16M)
+
+/* On-chip SRAM */
+#define BSP_MEM_ADDR_SRAM     (0x20000000)
+#define BSP_MEM_SIZE_SRAM     (8*1024)
+
+/* On-chip peripherial registers */
+#define BSP_MEM_ADDR_IMM      (0x10000000)
+#define BSP_MEM_SIZE_IMM      (1*1024)
+#define MBAR BSP_MEM_ADDR_IMM
+
+/* Interrupt vector assignment */
+#define BSP_INTVEC_AVEC1    (25)
+#define BSP_INTLVL_AVEC1    (1)
+#define BSP_INTPRIO_AVEC1   (3)
+
+#define BSP_INTVEC_AVEC2    (26)
+#define BSP_INTLVL_AVEC2    (2)
+#define BSP_INTPRIO_AVEC2   (3)
+
+#define BSP_INTVEC_AVEC3    (27)
+#define BSP_INTLVL_AVEC3    (3)
+#define BSP_INTPRIO_AVEC3   (3)
+
+#define BSP_INTVEC_AVEC4    (28)
+#define BSP_INTLVL_AVEC4    (4)
+#define BSP_INTPRIO_AVEC4   (3)
+
+#define BSP_INTVEC_AVEC5    (29)
+#define BSP_INTLVL_AVEC5    (5)
+#define BSP_INTPRIO_AVEC5   (3)
+
+#define BSP_INTVEC_AVEC6    (30)
+#define BSP_INTLVL_AVEC6    (6)
+#define BSP_INTPRIO_AVEC6   (3)
+
+#define BSP_INTVEC_AVEC7    (31)
+#define BSP_INTLVL_AVEC7    (7)
+#define BSP_INTPRIO_AVEC7   (3)
+
+#define BSP_INTVEC_TIMER1   (BSP_INTVEC_AVEC5)
+#define BSP_INTLVL_TIMER1   (BSP_INTLVL_AVEC5)
+#define BSP_INTPRIO_TIMER1  (2)
+
+#define BSP_INTVEC_TIMER2    (BSP_INTVEC_AVEC6)
+#define BSP_INTLVL_TIMER2    (BSP_INTLVL_AVEC6)
+#define BSP_INTPRIO_TIMER2   (2)
+
+#define BSP_INTVEC_MBUS     (BSP_INTVEC_AVEC4)
+#define BSP_INTLVL_MBUS     (BSP_INTLVL_AVEC4)
+#define BSP_INTPRIO_MBUS    (2)
+
+#define BSP_INTVEC_UART1    (64)
+#define BSP_INTLVL_UART1    (4)
+#define BSP_INTPRIO_UART1   (0)
+
+#define BSP_INTVEC_UART2    (65)
+#define BSP_INTLVL_UART2    (4)
+#define BSP_INTPRIO_UART2   (1)
+
+#define BSP_INTVEC_DMA0     (66)
+#define BSP_INTLVL_DMA0     (3)
+#define BSP_INTPRIO_DMA0    (1)
+
+#define BSP_INTVEC_DMA1     (67)
+#define BSP_INTLVL_DMA1     (3)
+#define BSP_INTPRIO_DMA1    (2)
+
+/* Location of DS1307 Real-Time Clock/NVRAM chip */
+#define DS1307_I2C_BUS_NUMBER (0)
+
+#ifndef ASM
+
+#include <bspopts.h>
+#include <rtems.h>
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System frequency */
+#define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY)
+extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */
+
+/* MBUS I2C bus clock default frequency */
+#define BSP_MBUS_FREQUENCY (16000)
+
+/* Number of I2C buses supported in this board */
+#define I2C_NUMBER_OF_BUSES (1)
+
+/* I2C bus selection */
+#define I2C_SELECT_BUS(bus)
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ */
+
+#define rtems_bsp_delay( microseconds ) \
+  { register uint32_t         _delay=(microseconds); \
+    register uint32_t         _tmp=123; \
+    __asm__ volatile( "0: \
+                     nbcd      %0 ; \
+                     nbcd      %0 ; \
+                     dbf       %1,0b" \
+                  : "=d" (_tmp), "=d" (_delay) \
+                  : "0"  (_tmp), "1"  (_delay) ); \
+  }
+
+
+extern rtems_isr_entry M68Kvec[];   /* vector table address */
+
+extern rtems_isr (*rtems_clock_hook)(rtems_vector_number);
+
+/* functions */
+
+rtems_isr_entry set_vector(
+  rtems_isr_entry     handler,
+  rtems_vector_number vector,
+  int                 type
+);
+
+/*
+ * Prototypes for BSP methods that cross file boundaries
+ */
+void Init5206e(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#endif
Index: bsps/m68k/mcf5206elite/include/ds1307.h
===================================================================
--- bsps/m68k/mcf5206elite/include/ds1307.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/include/ds1307.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,41 @@
+/*
+ * This file contains the definitions for Dallas Semiconductor
+ * DS1307/DS1308 serial real-time clock/NVRAM.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __RTC_DS1307__
+#define __RTC_DS1307__
+
+#define DS1307_I2C_ADDRESS  (0xD0) /* I2C bus address assigned to DS1307 */
+
+#define DS1307_SECOND       (0x00)
+#define DS1307_SECOND_HALT  (0x80) /* High bit is a Clock Halt bit */
+#define DS1307_MINUTE       (0x01)
+#define DS1307_HOUR         (0x02)
+#define DS1307_HOUR_12      (0x40) /* 12-hour mode */
+#define DS1307_HOUR_PM      (0x20) /* PM in 12-hour mode */
+#define DS1307_DAY_OF_WEEK  (0x03)
+#define DS1307_DAY          (0x04)
+#define DS1307_MONTH        (0x05)
+#define DS1307_YEAR         (0x06)
+#define DS1307_CONTROL      (0x07)
+#define DS1307_CONTROL_OUT      (0x80) /* Output control */
+#define DS1307_CONTROL_SQWE     (0x10) /* Sqware Wave Enable */
+#define DS1307_CONTROL_RS_1     (0x00) /* Rate select: 1 Hz */
+#define DS1307_CONTROL_RS_4096  (0x01) /* Rate select: 4096 Hz */
+#define DS1307_CONTROL_RS_8192  (0x02) /* Rate select: 8192 Hz */
+#define DS1307_CONTROL_RS_32768 (0x03) /* Rate select; 32768 Hz */
+
+#define DS1307_NVRAM_START  (0x08) /* Start location of non-volatile memory */
+#define DS1307_NVRAM_END    (0x3F) /* End location of non-volatile memory */
+#define DS1307_NVRAM_SIZE   (56)   /* Size of non-volatile memory */
+
+#endif __RTC_DS1307__
Index: bsps/m68k/mcf5206elite/include/i2c.h
===================================================================
--- bsps/m68k/mcf5206elite/include/i2c.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/include/i2c.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,243 @@
+/*
+ * Generic I2C bus interface for RTEMS
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __RTEMS__I2C_H__
+#define __RTEMS__I2C_H__
+
+#include <rtems.h>
+#include <bsp.h>
+/* This header file define the generic interface to i2c buses available in
+ * system. This interface may be used by user applications or i2c-device
+ * drivers (like RTC, NVRAM, etc).
+ *
+ * Functions i2c_initialize and i2c_transfer declared in this header usually
+ * implemented in particular board support package. Usually this
+ * implementation is a simple wrapper or multiplexor to I2C controller
+ * driver which is available in system.  It may be generic "software
+ * controller" I2C driver which control SDA and SCL signals directly (if SDA
+ * and SCL is general-purpose I/O pins), or driver for hardware I2C
+ * controller (standalone or integrated with processors: MBus controller in
+ * ColdFire processors, I2C controller in PowerQUICC and so on).
+ *
+ * i2c_transfer is a very generic low-level function. Higher-level function
+ * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too.
+ */
+
+/* I2C Bus Number type */
+typedef uint32_t         i2c_bus_number;
+
+/* I2C device address */
+typedef uint16_t         i2c_address;
+
+/* I2C error codes generated during message transfer */
+typedef enum i2c_message_status {
+    I2C_SUCCESSFUL = 0,
+    I2C_TIMEOUT,
+    I2C_NO_DEVICE,
+    I2C_ARBITRATION_LOST,
+    I2C_NO_ACKNOWLEDGE,
+    I2C_NO_DATA,
+    I2C_RESOURCE_NOT_AVAILABLE
+} i2c_message_status;
+
+/* I2C Message */
+typedef struct i2c_message {
+    i2c_address        addr;   /* I2C slave device address */
+    uint16_t           flags;  /* message flags (see below) */
+    i2c_message_status status; /* message transfer status code */
+    uint16_t           len;    /* Number of bytes to read or write */
+    uint8_t           *buf;    /* pointer to data array */
+} i2c_message;
+
+/* I2C message flag */
+#define I2C_MSG_ADDR_10 (0x01)  /* 10-bit address */
+#define I2C_MSG_WR      (0x02)  /* transfer direction for this message
+                                   from master to slave */
+#define I2C_MSG_ERRSKIP (0x04)  /* Skip message if last transfered message
+                                   is failed */
+/* Type for function which is called when transfer over I2C bus is finished */
+typedef void (*i2c_transfer_done) (void *arg);
+
+/* i2c_initialize --
+ *     I2C driver initialization. This function usually called on device
+ *     driver initialization state, before initialization task. All I2C
+ *     buses are initialized; reasonable slow data transfer rate is
+ *     selected for each bus.
+ *
+ * PARAMETERS:
+ *     major - I2C device major number
+ *     minor - I2C device minor number
+ *     arg - RTEMS driver initialization argument
+ *
+ * RETURNS:
+ *     RTEMS status code
+ */
+rtems_device_driver
+i2c_initialize(rtems_device_major_number major,
+               rtems_device_minor_number minor,
+               void *arg);
+
+/* i2c_select_clock_rate --
+ *     select I2C bus clock rate for specified bus. Some bus controller do not
+ *     allow to select arbitrary clock rate; in this case nearest possible
+ *     slower clock rate is selected.
+ *
+ * PARAMETERS:
+ *     bus - I2C bus number
+ *     bps - data transfer rate for this bytes in bits per second
+ *
+ * RETURNS:
+ *     RTEMS_SUCCESSFUL, if operation performed successfully,
+ *     RTEMS_INVALID_NUMBER, if wrong bus number is specified,
+ *     RTEMS_UNSATISFIED, if bus do not support data transfer rate selection
+ *     or specified data transfer rate could not be used.
+ */
+rtems_status_code
+i2c_select_clock_rate(i2c_bus_number bus, int bps);
+
+/* i2c_transfer --
+ *     Initiate multiple-messages transfer over specified I2C bus or
+ *     put request into queue if bus or some other resource is busy. (This
+ *     is non-blocking function).
+ *
+ * PARAMETERS:
+ *     bus - I2C bus number
+ *     nmsg - number of messages
+ *     msg - pointer to messages array
+ *     done - function which is called when transfer is finished
+ *     done_arg_ptr - arbitrary argument ptr passed to done funciton
+ *
+ * RETURNS:
+ *     RTEMS_SUCCESSFUL if transfer initiated successfully, or error
+ *     code if something failed.
+ */
+rtems_status_code
+i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg,
+             i2c_transfer_done done, void * done_arg_ptr);
+
+/* i2c_transfer_wait --
+ *     Initiate I2C bus transfer and block until this transfer will be
+ *     finished. This function wait the semaphore if system in
+ *     SYSTEM_STATE_UP state, or poll done flag in other states.
+ *
+ * PARAMETERS:
+ *     bus - I2C bus number
+ *     msg - pointer to transfer messages array
+ *     nmsg - number of messages in transfer
+ *
+ * RETURNS:
+ *     I2C_SUCCESSFUL, if transfer finished successfully,
+ *     I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed,
+ *     value of status field of first error-finished message in transfer,
+ *     if something wrong.
+ */
+i2c_message_status
+i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg);
+
+/* i2c_poll --
+ *     Poll I2C bus controller for events and hanle it. This function is
+ *     used when I2C driver operates in poll-driven mode.
+ *
+ * PARAMETERS:
+ *     bus - bus number to be polled
+ *
+ * RETURNS:
+ *     none
+ */
+void
+i2c_poll(i2c_bus_number bus);
+
+/* i2c_write --
+ *     Send single message over specified I2C bus to addressed device and
+ *     wait while transfer is finished.
+ *
+ * PARAMETERS:
+ *     bus  - I2C bus number
+ *     addr - address of I2C device
+ *     buf  - data to be sent to device
+ *     size - data buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size);
+
+/* i2c_wrbyte --
+ *     Send single one-byte long message over specified I2C bus to
+ *     addressed device and wait while transfer is finished.
+ *
+ * PARAMETERS:
+ *     bus  - I2C bus number
+ *     addr - address of I2C device
+ *     cmd  - byte message to be sent to device
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t         cmd);
+
+/* i2c_read --
+ *     receive single message over specified I2C bus from addressed device.
+ *     This call will wait while transfer is finished.
+ *
+ * PARAMETERS:
+ *     bus  - I2C bus number
+ *     addr - address of I2C device
+ *     buf  - buffer for received message
+ *     size - receive buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size);
+
+/* i2c_wrrd --
+ *     Send message over I2C bus to specified device and receive message
+ *     from the same device during single transfer.
+ *
+ * PARAMETERS:
+ *     bus   - I2C bus number
+ *     addr  - address of I2C device
+ *     bufw  - data to be sent to device
+ *     sizew - send data buffer size
+ *     bufr  - buffer for received message
+ *     sizer - receive buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew,
+         void *bufr, int sizer);
+
+/* i2c_wbrd --
+ *     Send one-byte message over I2C bus to specified device and receive
+ *     message from the same device during single transfer.
+ *
+ * PARAMETERS:
+ *     bus   - I2C bus number
+ *     addr  - address of I2C device
+ *     cmd   - one-byte message to be sent over I2C bus
+ *     bufr  - buffer for received message
+ *     sizer - receive buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t         cmd,
+         void *bufr, int sizer);
+
+#endif
Index: bsps/m68k/mcf5206elite/include/i2cdrv.h
===================================================================
--- bsps/m68k/mcf5206elite/include/i2cdrv.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/include/i2cdrv.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,35 @@
+/*
+ * i2cdrv.h -- I2C bus driver prototype and definitions
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __I2CDRV_H__
+#define __I2CDRV_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define I2C_DRIVER_TABLE_ENTRY \
+  { i2cdrv_initialize, NULL, NULL, NULL, NULL, NULL }
+
+/* i2cdrv_initialize --
+ *     I2C driver initialization (rtems I/O driver primitive)
+ */
+rtems_device_driver
+i2cdrv_initialize(rtems_device_major_number major,
+                  rtems_device_minor_number minor,
+                  void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2CDRV_H__ */
Index: bsps/m68k/mcf5206elite/include/nvram.h
===================================================================
--- bsps/m68k/mcf5206elite/include/nvram.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/include/nvram.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,71 @@
+/*
+ * nvram.h -- DS1307-based non-volatile memory device driver.
+ *
+ * This driver support file-like operations to 56-bytes long non-volatile
+ * memory of DS1307 I2C real-time clock chip.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __DRIVER__NVRAM_H__
+#define __DRIVER__NVRAM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVRAM_DRIVER_TABLE_ENTRY \
+  { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \
+    nvram_driver_read, nvram_driver_write, NULL }
+
+/* nvram_driver_initialize --
+ *     Non-volatile memory device driver initialization.
+ */
+rtems_device_driver
+nvram_driver_initialize(rtems_device_major_number major,
+                        rtems_device_minor_number minor,
+                        void *arg);
+
+/* nvram_driver_open --
+ *     Non-volatile memory device driver open primitive.
+ */
+rtems_device_driver
+nvram_driver_open(rtems_device_major_number major,
+                  rtems_device_minor_number minor,
+                  void *arg);
+
+/* nvram_driver_close --
+ *     Non-volatile memory device driver close primitive.
+ */
+rtems_device_driver
+nvram_driver_close(rtems_device_major_number major,
+                   rtems_device_minor_number minor,
+                   void *arg);
+
+/* nvram_driver_read --
+ *     Non-volatile memory device driver read primitive.
+ */
+rtems_device_driver
+nvram_driver_read(rtems_device_major_number major,
+                  rtems_device_minor_number minor,
+                  void *arg);
+
+/* nvram_driver_write --
+ *     Non-volatile memory device driver write primitive.
+ */
+rtems_device_driver
+nvram_driver_write(rtems_device_major_number major,
+                   rtems_device_minor_number minor,
+                   void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __VFDDRV_H__ */
Index: bsps/m68k/mcf5206elite/include/tm27.h
===================================================================
--- bsps/m68k/mcf5206elite/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/m68k/mcf5206elite/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,35 @@
+/*
+ * @file
+ * @ingroup m68k_mcf5206elite
+ * @brief Implementations for interrupt mechanisms for Time Test 27
+ */
+
+/*
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ *  Stuff for Time Test 27
+ *  Don't bother with hardware -- just use a software-interrupt
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 )
+
+#define Cause_tm27_intr()	asm volatile ("trap #2");
+
+#define Clear_tm27_intr() /* empty */
+
+#define Lower_tm27_intr() /* empty */
+
+#endif
