Index: bsps/arm/raspberrypi/include/bsp/fbcons.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/fbcons.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/fbcons.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,47 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_console
+ *
+ * @brief framebuffer graphic console support.
+ */
+
+/*
+ * Copyright (c) 2015 Yang Qiao
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef _FBCONS_H_
+#define _FBCONS_H_
+
+#include <libchip/serial.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This is the ASCII for "PI" in the upper word and 2835
+ *  in the lower which should be unique enough to
+ *  distinguish this type of serial device from others.
+ */
+
+#define FB_CONSOLE 0x50492835
+
+bool fbcons_probe( int minor );
+
+/*
+ * Driver function table
+ */
+extern const console_fns fbcons_fns;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FBCONS_H_ */
Index: bsps/arm/raspberrypi/include/bsp/i2c.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/i2c.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/i2c.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,95 @@
+/**
+ * @file i2c.h
+ *
+ * @ingroup raspberrypi_i2c
+ *
+ * @brief Raspberry Pi specific I2C definitions.
+ */
+
+/*
+ *  Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_I2C_H
+#define LIBBSP_ARM_RASPBERRYPI_I2C_H
+
+#include <dev/i2c/i2c.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name I2C constants.
+ *
+ * @{
+ */
+
+/**
+ * @brief BSC controller core clock rate in Hz.
+ *
+ * This is set to 150 MHz as per the BCM2835 datasheet.
+ */
+#define BSC_CORE_CLK_HZ 150000000
+
+/**
+ * @brief Default bus clock.
+ *
+ * This sets the bus with a 100 kHz clock speed.
+ */
+#define DEFAULT_BUS_CLOCK 100000
+
+/** @} */
+
+/**
+ * @name  I2C directives.
+ *
+ * @{
+ */
+
+/**
+ * @brief Setups the Raspberry Pi GPIO header to activate the BSC I2C bus.
+ */
+extern void rpi_i2c_init(void);
+
+/**
+ * @brief Registers the Raspberry Pi BSC I2C bus with the
+ *        Linux I2C User-Space API.
+ *
+ * @param[in] bus_path Path to the bus device file.
+ * @param[in] bus_clock Bus clock in Hz.
+ *
+ * @retval 0 Bus registered successfully.
+ * @retval <0 Could not register the bus. The return value is a negative
+ *            errno code.
+ */
+extern int rpi_i2c_register_bus(
+  const char *bus_path,
+  uint32_t bus_clock
+);
+
+/**
+ * @brief Setups the Raspberry Pi BSC I2C bus (located on the GPIO header)
+ *        on the "/dev/i2c" device file, using the default bus clock.
+ *
+ * @retval 0 Bus configured and registered successfully.
+ * @retval <0 See @see rpi_i2c_register_bus().
+ */
+static inline int rpi_setup_i2c_bus(void)
+{
+  rpi_i2c_init();
+
+  return rpi_i2c_register_bus("/dev/i2c", DEFAULT_BUS_CLOCK);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_I2C_H */
Index: bsps/arm/raspberrypi/include/bsp/irq.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_interrupt
+ *
+ * @brief Interrupt definitions.
+ */
+
+/**
+ * Copyright (c) 2013 Alan Cudmore
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASBPERRYPI_IRQ_H
+#define LIBBSP_ARM_RASPBERRYPI_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/**
+ * @defgroup raspberrypi_interrupt Interrrupt Support
+ *
+ * @ingroup arm_raspberrypi
+ *
+ * @brief Interrupt support.
+ */
+
+#define BCM2835_INTC_TOTAL_IRQ       64 + 8
+
+
+#define BCM2835_IRQ_ID_GPU_TIMER_M0  0
+#define BCM2835_IRQ_ID_GPU_TIMER_M1  1
+#define BCM2835_IRQ_ID_GPU_TIMER_M2  2
+#define BCM2835_IRQ_ID_GPU_TIMER_M3  3
+
+#define BCM2835_IRQ_ID_USB           9
+#define BCM2835_IRQ_ID_AUX           29
+#define BCM2835_IRQ_ID_SPI_SLAVE     43
+#define BCM2835_IRQ_ID_PWA0          45
+#define BCM2835_IRQ_ID_PWA1          46
+#define BCM2835_IRQ_ID_SMI           48
+#define BCM2835_IRQ_ID_GPIO_0        49
+#define BCM2835_IRQ_ID_GPIO_1        50
+#define BCM2835_IRQ_ID_GPIO_2        51
+#define BCM2835_IRQ_ID_GPIO_3        52
+#define BCM2835_IRQ_ID_I2C           53
+#define BCM2835_IRQ_ID_SPI           54
+#define BCM2835_IRQ_ID_PCM           55
+#define BCM2835_IRQ_ID_UART          57
+#define BCM2835_IRQ_ID_SD            62
+
+#define BCM2835_IRQ_ID_BASIC_BASE_ID 64
+#define BCM2835_IRQ_ID_TIMER_0       64
+#define BCM2835_IRQ_ID_MAILBOX_0     65
+#define BCM2835_IRQ_ID_DOORBELL_0    66
+#define BCM2835_IRQ_ID_DOORBELL_1    67
+#define BCM2835_IRQ_ID_GPU0_HALTED   68
+#define BCM2835_IRQ_ID_GPU1_HALTED   69
+#define BCM2835_IRQ_ID_ILL_ACCESS_1  70
+#define BCM2835_IRQ_ID_ILL_ACCESS_0  71
+
+#define BSP_INTERRUPT_VECTOR_MIN    (0)
+#define BSP_INTERRUPT_VECTOR_MAX    (BCM2835_INTC_TOTAL_IRQ - 1)
+
+#define BSP_IRQ_COUNT               (BCM2835_INTC_TOTAL_IRQ)
+
+#endif /* ASM */
+#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
Index: bsps/arm/raspberrypi/include/bsp/mailbox.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/mailbox.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/mailbox.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,32 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi
+ *
+ * @brief mailbox support.
+ */
+/*
+ * Copyright (c) 2015 Yang Qiao
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_MAILBOX_H
+#define LIBBSP_ARM_RASPBERRYPI_MAILBOX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern unsigned int  raspberrypi_mailbox_read(unsigned int channel);
+extern void raspberrypi_mailbox_write(unsigned int channel, unsigned int data);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif  /* LIBBSP_ARM_RASPBERRYPI_MAILBOX_H */
Index: bsps/arm/raspberrypi/include/bsp/mmu.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/mmu.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/mmu.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * @ingroup rapberrypi_mmu
+ *
+ * @brief MMU API.
+ */
+
+/*
+ * Copyright (c) 2013 Alan Cudmore.
+ * based on work by:
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_MMU_H
+#define LIBBSP_ARM_RASPBERRYPI_MMU_H
+
+#include <libcpu/arm-cp15.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup raspberrypi_mmu MMU Support
+ *
+ * @ingroup arm_raspberrypi
+ *
+ * @brief MMU support.
+ *
+ * @{
+ */
+
+#define RASPBERRYPI_MMU_CLIENT_DOMAIN 15U
+
+#define RASPBERRYPI_MMU_READ_ONLY \
+  ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
+    | ARM_MMU_SECT_DEFAULT)
+
+#define RASPBERRYPI_MMU_READ_ONLY_CACHED \
+  (RASPBERRYPI_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
+
+#define RASPBERRYPI_MMU_READ_WRITE \
+  ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
+    | ARM_MMU_SECT_AP_0 \
+    | ARM_MMU_SECT_DEFAULT)
+
+#define RASPBERRYPI_MMU_READ_WRITE_CACHED \
+  (RASPBERRYPI_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_MMU_H */
Index: bsps/arm/raspberrypi/include/bsp/raspberrypi.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/raspberrypi.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/raspberrypi.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,572 @@
+/**
+ * @file raspberrypi.h
+ *
+ * @ingroup raspberrypi_reg
+ *
+ * @brief Register definitions.
+ */
+
+/*
+ *  Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
+ *  Copyright (c) 2013 Alan Cudmore.
+ *  Copyright (c) 2015 Yang Qiao
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
+#define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
+
+#include <bspopts.h>
+#include <stdint.h>
+#include <bsp/utility.h>
+
+/**
+ * @defgroup raspberrypi_reg Register Definitions
+ *
+ * @ingroup arm_raspberrypi
+ *
+ * @brief Register Definitions
+ *
+ * @{
+ */
+
+/**
+ * @name Register Macros
+ *
+ * @{
+ */
+
+#define BCM2835_REG(x)           (*(volatile uint32_t *)(x))
+#define BCM2835_BIT(n)           (1 << (n))
+
+/** @} */
+
+/**
+ * @name Peripheral Base Register Address
+ *
+ * @{
+ */
+
+#if (BSP_IS_RPI2 == 1)
+   #define RPI_PERIPHERAL_BASE      0x3F000000
+#else
+   #define RPI_PERIPHERAL_BASE      0x20000000
+#endif
+
+#define RPI_PERIPHERAL_SIZE         0x01000000
+
+/**
+ * @name Internal ARM Timer Registers
+ *
+ * @{
+ */
+
+#define BCM2835_CLOCK_FREQ       250000000
+
+#define BCM2835_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0xB400)
+
+#define BCM2835_TIMER_LOD        (BCM2835_TIMER_BASE + 0x00)
+#define BCM2835_TIMER_VAL        (BCM2835_TIMER_BASE + 0x04)
+#define BCM2835_TIMER_CTL        (BCM2835_TIMER_BASE + 0x08)
+#define BCM2835_TIMER_CLI        (BCM2835_TIMER_BASE + 0x0C)
+#define BCM2835_TIMER_RIS        (BCM2835_TIMER_BASE + 0x10)
+#define BCM2835_TIMER_MIS        (BCM2835_TIMER_BASE + 0x14)
+#define BCM2835_TIMER_RLD        (BCM2835_TIMER_BASE + 0x18)
+#define BCM2835_TIMER_DIV        (BCM2835_TIMER_BASE + 0x1C)
+#define BCM2835_TIMER_CNT        (BCM2835_TIMER_BASE + 0x20)
+
+#define BCM2835_TIMER_PRESCALE    0xF9
+
+/** @} */
+
+/**
+ * @name Power Management and Watchdog  Registers
+ *
+ * @{
+ */
+
+#define BCM2835_PM_PASSWD_MAGIC  0x5a000000
+
+#define BCM2835_PM_BASE          (RPI_PERIPHERAL_BASE + 0x100000)
+
+#define BCM2835_PM_GNRIC         (BCM2835_PM_BASE + 0x00)
+#define BCM2835_PM_GNRIC_POWUP   0x00000001
+#define BCM2835_PM_GNRIC_POWOK   0x00000002
+#define BCM2835_PM_GNRIC_ISPOW   0x00000004
+#define BCM2835_PM_GNRIC_MEMREP  0x00000008
+#define BCM2835_PM_GNRIC_MRDONE  0x00000010
+#define BCM2835_PM_GNRIC_ISFUNC  0x00000020
+#define BCM2835_PM_GNRIC_RSTN    0x00000fc0
+#define BCM2835_PM_GNRIC_ENAB    0x00001000
+#define BCM2835_PM_GNRIC_CFG     0x007f0000
+
+#define BCM2835_PM_AUDIO         (BCM2835_PM_BASE + 0x04)
+#define BCM2835_PM_AUDIO_APSM    0x000fffff
+#define BCM2835_PM_AUDIO_CTRLEN  0x00100000
+#define BCM2835_PM_AUDIO_RSTN    0x00200000
+
+#define BCM2835_PM_STATUS        (BCM2835_PM_BASE + 0x18)
+
+#define BCM2835_PM_RSTC          (BCM2835_PM_BASE + 0x1c)
+#define BCM2835_PM_RSTC_DRCFG    0x00000003
+#define BCM2835_PM_RSTC_WRCFG    0x00000030
+#define BCM2835_PM_RSTC_WRCFG_FULL   0x00000020
+#define BCM2835_PM_RSTC_SRCFG    0x00000300
+#define BCM2835_PM_RSTC_QRCFG    0x00003000
+#define BCM2835_PM_RSTC_FRCFG    0x00030000
+#define BCM2835_PM_RSTC_HRCFG    0x00300000
+
+#define BCM2835_PM_RSTS          (BCM2835_PM_BASE + 0x20)
+#define BCM2835_PM_RSTS_HADDRQ   0x00000001
+#define BCM2835_PM_RSTS_HADDRF   0x00000002
+#define BCM2835_PM_RSTS_HADDRH   0x00000004
+#define BCM2835_PM_RSTS_HADWRQ   0x00000010
+#define BCM2835_PM_RSTS_HADWRF   0x00000020
+#define BCM2835_PM_RSTS_HADWRH   0x00000040
+#define BCM2835_PM_RSTS_HADSRQ   0x00000100
+#define BCM2835_PM_RSTS_HADSRF   0x00000200
+#define BCM2835_PM_RSTS_HADSRH   0x00000400
+#define BCM2835_PM_RSTS_HADPOR   0x00001000
+
+#define BCM2835_PM_WDOG          (BCM2835_PM_BASE + 0x24)
+
+/** @} */
+
+/**
+ * @name GPIO Registers
+ *
+ * @{
+ */
+
+#define BCM2835_GPIO_REGS_BASE   (RPI_PERIPHERAL_BASE + 0x200000)
+
+#define BCM2835_GPIO_GPFSEL1     (BCM2835_GPIO_REGS_BASE + 0x04)
+#define BCM2835_GPIO_GPSET0      (BCM2835_GPIO_REGS_BASE + 0x1C)
+#define BCM2835_GPIO_GPCLR0      (BCM2835_GPIO_REGS_BASE + 0x28)
+#define BCM2835_GPIO_GPLEV0      (BCM2835_GPIO_REGS_BASE + 0x34)
+#define BCM2835_GPIO_GPEDS0      (BCM2835_GPIO_REGS_BASE + 0x40)
+#define BCM2835_GPIO_GPREN0      (BCM2835_GPIO_REGS_BASE + 0x4C)
+#define BCM2835_GPIO_GPFEN0      (BCM2835_GPIO_REGS_BASE + 0x58)
+#define BCM2835_GPIO_GPHEN0      (BCM2835_GPIO_REGS_BASE + 0x64)
+#define BCM2835_GPIO_GPLEN0      (BCM2835_GPIO_REGS_BASE + 0x70)
+#define BCM2835_GPIO_GPAREN0     (BCM2835_GPIO_REGS_BASE + 0x7C)
+#define BCM2835_GPIO_GPAFEN0     (BCM2835_GPIO_REGS_BASE + 0x88)
+#define BCM2835_GPIO_GPPUD       (BCM2835_GPIO_REGS_BASE + 0x94)
+#define BCM2835_GPIO_GPPUDCLK0   (BCM2835_GPIO_REGS_BASE + 0x98)
+
+/** @} */
+
+/**
+ * @name AUX Registers
+ *
+ * @{
+ */
+
+#define BCM2835_AUX_BASE         (RPI_PERIPHERAL_BASE + 0x215000)
+
+#define AUX_ENABLES              (BCM2835_AUX_BASE + 0x04)
+#define AUX_MU_IO_REG            (BCM2835_AUX_BASE + 0x40)
+#define AUX_MU_IER_REG           (BCM2835_AUX_BASE + 0x44)
+#define AUX_MU_IIR_REG           (BCM2835_AUX_BASE + 0x48)
+#define AUX_MU_LCR_REG           (BCM2835_AUX_BASE + 0x4C)
+#define AUX_MU_MCR_REG           (BCM2835_AUX_BASE + 0x50)
+#define AUX_MU_LSR_REG           (BCM2835_AUX_BASE + 0x54)
+#define AUX_MU_MSR_REG           (BCM2835_AUX_BASE + 0x58)
+#define AUX_MU_SCRATCH           (BCM2835_AUX_BASE + 0x5C)
+#define AUX_MU_CNTL_REG          (BCM2835_AUX_BASE + 0x60)
+#define AUX_MU_STAT_REG          (BCM2835_AUX_BASE + 0x64)
+#define AUX_MU_BAUD_REG          (BCM2835_AUX_BASE + 0x68)
+
+/** @} */
+
+/**
+ * @name UART 0 (PL011) Registers
+ *
+ * @{
+ */
+
+#define BCM2835_UART0_BASE       (RPI_PERIPHERAL_BASE + 0x201000)
+
+#define BCM2835_UART0_DR         (BCM2835_UART0_BASE + 0x00)
+#define BCM2835_UART0_RSRECR     (BCM2835_UART0_BASE + 0x04)
+#define BCM2835_UART0_FR         (BCM2835_UART0_BASE + 0x18)
+#define BCM2835_UART0_ILPR       (BCM2835_UART0_BASE + 0x20)
+#define BCM2835_UART0_IBRD       (BCM2835_UART0_BASE + 0x24)
+#define BCM2835_UART0_FBRD       (BCM2835_UART0_BASE + 0x28)
+#define BCM2835_UART0_LCRH       (BCM2835_UART0_BASE + 0x2C)
+#define BCM2835_UART0_CR         (BCM2835_UART0_BASE + 0x30)
+#define BCM2835_UART0_IFLS       (BCM2835_UART0_BASE + 0x34)
+#define BCM2835_UART0_IMSC       (BCM2835_UART0_BASE + 0x38)
+#define BCM2835_UART0_RIS        (BCM2835_UART0_BASE + 0x3C)
+#define BCM2835_UART0_MIS        (BCM2835_UART0_BASE + 0x40)
+#define BCM2835_UART0_ICR        (BCM2835_UART0_BASE + 0x44)
+#define BCM2835_UART0_DMACR      (BCM2835_UART0_BASE + 0x48)
+#define BCM2835_UART0_ITCR       (BCM2835_UART0_BASE + 0x80)
+#define BCM2835_UART0_ITIP       (BCM2835_UART0_BASE + 0x84)
+#define BCM2835_UART0_ITOP       (BCM2835_UART0_BASE + 0x88)
+#define BCM2835_UART0_TDR        (BCM2835_UART0_BASE + 0x8C)
+
+#define BCM2835_UART0_MIS_RX    0x10
+#define BCM2835_UART0_MIS_TX    0x20
+#define BCM2835_UART0_IMSC_RX   0x10
+#define BCM2835_UART0_IMSC_TX   0x20
+#define BCM2835_UART0_FR_RXFE   0x10
+#define BCM2835_UART0_FR_TXFF   0x20
+#define BCM2835_UART0_ICR_RX    0x10
+#define BCM2835_UART0_ICR_TX    0x20
+
+/** @} */
+
+/**
+ * @name I2C (BSC) Registers
+ *
+ * @{
+ */
+
+#define BCM2835_I2C_BASE           (RPI_PERIPHERAL_BASE + 0x804000)
+
+#define BCM2835_I2C_C              (BCM2835_I2C_BASE + 0x00)
+#define BCM2835_I2C_S              (BCM2835_I2C_BASE + 0x04)
+#define BCM2835_I2C_DLEN           (BCM2835_I2C_BASE + 0x08)
+#define BCM2835_I2C_A              (BCM2835_I2C_BASE + 0x0C)
+#define BCM2835_I2C_FIFO           (BCM2835_I2C_BASE + 0x10)
+#define BCM2835_I2C_DIV            (BCM2835_I2C_BASE + 0x14)
+#define BCM2835_I2C_DEL            (BCM2835_I2C_BASE + 0x18)
+#define BCM2835_I2C_CLKT           (BCM2835_I2C_BASE + 0x1C)
+
+/** @} */
+
+/**
+ * @name SPI Registers
+ *
+ * @{
+ */
+
+#define BCM2835_SPI_BASE           (RPI_PERIPHERAL_BASE + 0x204000)
+
+#define BCM2835_SPI_CS             (BCM2835_SPI_BASE + 0x00)
+#define BCM2835_SPI_FIFO           (BCM2835_SPI_BASE + 0x04)
+#define BCM2835_SPI_CLK            (BCM2835_SPI_BASE + 0x08)
+#define BCM2835_SPI_DLEN           (BCM2835_SPI_BASE + 0x0C)
+#define BCM2835_SPI_LTOH           (BCM2835_SPI_BASE + 0x10)
+#define BCM2835_SPI_DC             (BCM2835_SPI_BASE + 0x14)
+
+/** @} */
+
+/**
+ * @name I2C/SPI slave BSC Registers
+ *
+ * @{
+ */
+
+#define BCM2835_I2C_SPI_BASE       (RPI_PERIPHERAL_BASE + 0x214000)
+
+#define BCM2835_I2C_SPI_DR         (BCM2835_I2C_SPI_BASE + 0x00)
+#define BCM2835_I2C_SPI_RSR        (BCM2835_I2C_SPI_BASE + 0x04)
+#define BCM2835_I2C_SPI_SLV        (BCM2835_I2C_SPI_BASE + 0x08)
+#define BCM2835_I2C_SPI_CR         (BCM2835_I2C_SPI_BASE + 0x0C)
+#define BCM2835_I2C_SPI_FR         (BCM2835_I2C_SPI_BASE + 0x10)
+#define BCM2835_I2C_SPI_IFLS       (BCM2835_I2C_SPI_BASE + 0x14)
+#define BCM2835_I2C_SPI_IMSC       (BCM2835_I2C_SPI_BASE + 0x18)
+#define BCM2835_I2C_SPI_RIS        (BCM2835_I2C_SPI_BASE + 0x1C)
+#define BCM2835_I2C_SPI_MIS        (BCM2835_I2C_SPI_BASE + 0x20)
+#define BCM2835_I2C_SPI_ICR        (BCM2835_I2C_SPI_BASE + 0x24)
+#define BCM2835_I2C_SPI_DMACR      (BCM2835_I2C_SPI_BASE + 0x28)
+#define BCM2835_I2C_SPI_TDR        (BCM2835_I2C_SPI_BASE + 0x2C)
+#define BCM2835_I2C_SPI_GPUSTAT    (BCM2835_I2C_SPI_BASE + 0x30)
+#define BCM2835_I2C_SPI_HCTRL      (BCM2835_I2C_SPI_BASE + 0x34)
+
+/** @} */
+
+/**
+ * @name IRQ Registers
+ *
+ * @{
+ */
+
+#define BCM2835_BASE_INTC         (RPI_PERIPHERAL_BASE + 0xB200)
+
+#define BCM2835_IRQ_BASIC         (BCM2835_BASE_INTC + 0x00)
+#define BCM2835_IRQ_PENDING1      (BCM2835_BASE_INTC + 0x04)
+#define BCM2835_IRQ_PENDING2      (BCM2835_BASE_INTC + 0x08)
+#define BCM2835_IRQ_FIQ_CTRL      (BCM2835_BASE_INTC + 0x0C)
+#define BCM2835_IRQ_ENABLE1       (BCM2835_BASE_INTC + 0x10)
+#define BCM2835_IRQ_ENABLE2       (BCM2835_BASE_INTC + 0x14)
+#define BCM2835_IRQ_ENABLE_BASIC  (BCM2835_BASE_INTC + 0x18)
+#define BCM2835_IRQ_DISABLE1      (BCM2835_BASE_INTC + 0x1C)
+#define BCM2835_IRQ_DISABLE2      (BCM2835_BASE_INTC + 0x20)
+#define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24)
+
+/** @} */
+
+/**
+ * @name GPU Timer Registers
+ *
+ * @{
+ */
+
+/**
+ * NOTE: The GPU uses Compare registers 0 and 2 for
+ *       it's own RTOS. 1 and 3 are available for use in
+ *       RTEMS.
+ */
+#define BCM2835_GPU_TIMER_BASE    (RPI_PERIPHERAL_BASE + 0x3000)
+
+#define BCM2835_GPU_TIMER_CS      (BCM2835_GPU_TIMER_BASE + 0x00)
+#define BCM2835_GPU_TIMER_CS_M0   0x00000001
+#define BCM2835_GPU_TIMER_CS_M1   0x00000002
+#define BCM2835_GPU_TIMER_CS_M2   0x00000004
+#define BCM2835_GPU_TIMER_CS_M3   0x00000008
+#define BCM2835_GPU_TIMER_CLO     (BCM2835_GPU_TIMER_BASE + 0x04)
+#define BCM2835_GPU_TIMER_CHI     (BCM2835_GPU_TIMER_BASE + 0x08)
+#define BCM2835_GPU_TIMER_C0      (BCM2835_GPU_TIMER_BASE + 0x0C)
+#define BCM2835_GPU_TIMER_C1      (BCM2835_GPU_TIMER_BASE + 0x10)
+#define BCM2835_GPU_TIMER_C2      (BCM2835_GPU_TIMER_BASE + 0x14)
+#define BCM2835_GPU_TIMER_C3      (BCM2835_GPU_TIMER_BASE + 0x18)
+
+/** @} */
+
+/**
+ * @name EMMC Registers
+ *
+ * @{
+ */
+
+/**
+ * NOTE: Since the SD controller follows the SDHCI standard,
+ *       the rtems-libbsd tree already provides the remaining registers.
+ */
+
+#define BCM2835_EMMC_BASE              (RPI_PERIPHERAL_BASE + 0x300000)
+
+/** @} */
+
+/**
+* @name Mailbox Registers
+*
+* @{
+*/
+
+#define BCM2835_MBOX_BASE   (RPI_PERIPHERAL_BASE+0xB880)
+
+#define BCM2835_MBOX_PEEK   (BCM2835_MBOX_BASE+0x10)
+#define BCM2835_MBOX_READ   (BCM2835_MBOX_BASE+0x00)
+#define BCM2835_MBOX_WRITE  (BCM2835_MBOX_BASE+0x20)
+#define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18)
+#define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14)
+#define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C)
+
+#define BCM2835_MBOX_FULL   0x80000000
+#define BCM2835_MBOX_EMPTY  0x40000000
+
+/** @} */
+
+/**
+* @name Mailbox Channels
+*
+* @{
+*/
+
+/* Power Manager channel */
+#define BCM2835_MBOX_CHANNEL_PM         0
+/* Framebuffer channel */
+#define BCM2835_MBOX_CHANNEL_FB         1
+ /* Virtual UART channel */
+#define BCM2835_MBOX_CHANNEL_VUART      2
+ /* VCHIQ channel */
+#define BCM2835_MBOX_CHANNEL_VCHIQ      3
+ /* LEDs channel */
+#define BCM2835_MBOX_CHANNEL_LED        4
+ /* Button channel */
+#define BCM2835_MBOX_CHANNEL_BUTTON     5
+ /* Touch screen channel */
+#define BCM2835_MBOX_CHANNEL_TOUCHS     6
+/* Property tags (ARM <-> VC) channel */
+#define BCM2835_MBOX_CHANNEL_PROP_AVC   8
+ /* Property tags (VC <-> ARM) channel */
+#define BCM2835_MBOX_CHANNEL_PROP_VCA   9
+
+/** @} */
+
+/**
+* @name USB Registers
+*
+* @{
+*/
+
+#define BCM2835_USB_BASE	(RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 CPU Cores Local Peripherals
+ *
+ * @{
+ */
+
+#define BCM2836_CORE_LOCAL_PERIPH_BASE    0x40000000
+#define BCM2836_CORE_LOCAL_PERIPH_SIZE    0x00040000
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 Mailbox Register Defines
+ *
+ * @{
+ */
+
+#define BCM2836_MAILBOX_0_WRITE_SET_BASE  0x40000080
+#define BCM2836_MAILBOX_1_WRITE_SET_BASE  0x40000084
+#define BCM2836_MAILBOX_2_WRITE_SET_BASE  0x40000088
+#define BCM2836_MAILBOX_3_WRITE_SET_BASE  0x4000008C
+#define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0
+#define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4
+#define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8
+#define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 Core Timer
+ *
+ * @{
+ */
+
+#define BCM2836_CORE_TIMER_CTRL           0x40000000
+
+#define BCM2836_CORE_TIMER_CTRL_APB_CLK   0x00000100
+#define BCM2836_CORE_TIMER_CTRL_INC_2     0x00000200
+
+#define BCM2836_CORE_TIMER_PRESCALER      0x40000008
+
+#define BCM2836_CORE_TIMER_LS32           0x4000001C
+#define BCM2836_CORE_TIMER_MS32           0x40000020
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 Local Timer
+ *
+ * @{
+ */
+
+#define BCM2836_LOCAL_TIMER_CTRL          0x40000034
+
+#define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000
+#define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN   0x20000000
+#define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000
+#define BCM2836_LOCAL_TIMER_RELOAD        0x0FFFFFFF
+
+#define BCM2836_LOCAL_TIMER_IRQ_RELOAD    0x40000038
+
+#define BCM2836_LOCAL_TIMER_IRQ_CLEAR     0x80000000
+#define BCM2836_LOCAL_TIMER_RELOAD_NOW    0x40000000
+
+#define BCM2836_LOCAL_TIMER_IRQ_ROUTING   0x40000024
+#define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ       0x00
+#define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ       0x01
+#define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ       0x02
+#define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ       0x03
+#define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ       0x04
+#define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ       0x05
+#define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ       0x06
+#define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ       0x07
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 IRQ Routing
+ *
+ * @{
+ */
+
+#define BCM2836_GPU_IRQ_ROUTING           0x4000000C
+
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003
+
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
+
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
+
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 Interrupt Register Defines
+ *
+ * @{
+ */
+
+/* Timers interrupt control registers */
+#define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040
+#define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044
+#define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048
+#define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C
+
+#define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \
+  (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
+
+/*
+ * Where to route timer interrupt to, IRQ/FIQ
+ * Setting both the IRQ and FIQ bit gives an FIQ
+ */
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ  0x01
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ  0x02
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ  0x04
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ  0x08
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ  0x10
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ  0x20
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ  0x40
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ  0x80
+
+/* CPU mailbox registers */
+#define BCM2836_MAILBOX_IRQ_CTRL_BASE     0x40000050
+#define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \
+  (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx))
+/*
+ * Where to route mailbox interrupt to, IRQ/FIQ
+ * Setting both the IRQ and FIQ bit gives an FIQ
+ */
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ      0x01
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ      0x02
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ      0x04
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ      0x08
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ      0x10
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ      0x20
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ      0x40
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ      0x80
+
+#define BCM2836_IRQ_SOURCE_REG_BASE       0x40000060
+#define BCM2836_IRQ_SOURCE_REG(cpuidx) \
+  (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
+
+#define BCM2836_FIQ_SOURCE_REG_BASE       0x40000070
+#define BCM2836_FIQ_SOURCE_REG(cpuidx) \
+  (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
+
+#define BCM2836_IRQ_SOURCE_TIMER0         0x00000001
+#define BCM2836_IRQ_SOURCE_TIMER1         0x00000002
+#define BCM2836_IRQ_SOURCE_TIMER2         0x00000004
+#define BCM2836_IRQ_SOURCE_TIMER3         0x00000008
+#define BCM2836_IRQ_SOURCE_MBOX0          0x00000010
+#define BCM2836_IRQ_SOURCE_MBOX1          0x00000020
+#define BCM2836_IRQ_SOURCE_MBOX2          0x00000040
+#define BCM2836_IRQ_SOURCE_MBOX3          0x00000080
+#define BCM2836_IRQ_SOURCE_GPU            0x00000100
+#define BCM2836_IRQ_SOURCE_PMU            0x00000200
+#define BCM2836_IRQ_SOURCE_LOCAL_TIMER    0x00000800
+
+/** @} */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
Index: bsps/arm/raspberrypi/include/bsp/rpi-fb.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/rpi-fb.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/rpi-fb.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,55 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_fb
+ *
+ * @brief framebuffer support and setup
+ *
+ */
+
+/*
+ * Copyright (c) 2015 Yang Qiao
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_FB_H
+#define LIBBSP_ARM_RASPBERRYPI_FB_H
+
+#include <rtems/fb.h>
+
+/**
+ * @defgroup raspberrypi_fb
+ *
+ * @ingroup arm_raspberrypi
+ *
+ * @brief Framebuffer support and setup
+ *
+ * @{
+ */
+
+enum rpi_fb_init_result {
+  RPI_FB_INIT_OK = 0,
+  RPI_FB_INIT_ALREADY_INITIALIZED = 1,
+  RPI_FB_INIT_GENERIC_ERROR = -1,
+  RPI_FB_INIT_NO_DISPLAY = -2,
+  RPI_FB_INIT_CMDLINE_BAD_FORMAT = -3,
+  RPI_FB_INIT_CMDLINE_DONT_INIT = -4,
+  RPI_FB_INIT_CMDLINE_NO_MODE_REQ = -5,
+  RPI_FB_INIT_MODE_PROBE_ERROR = -6,
+  RPI_FB_INIT_SETUP_FAILED = -7,
+  RPI_FB_INIT_START_ADDR_UNKNOWN = -8,
+};
+
+int rpi_fb_init( void );
+int rpi_get_fix_screen_info( struct fb_fix_screeninfo *info );
+int rpi_get_var_screen_info( struct fb_var_screeninfo *info );
+bool rpi_fb_hdmi_is_present( void );
+
+/** @} */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_FB_H */
Index: bsps/arm/raspberrypi/include/bsp/rpi-gpio.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/rpi-gpio.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/rpi-gpio.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,70 @@
+/**
+ * @file rpi-gpio.h
+ *
+ * @ingroup raspberrypi_gpio
+ *
+ * @brief Raspberry Pi specific GPIO definitions.
+ */
+
+/*
+ *  Copyright (c) 2015 Andre Marques <andre.lousa.marques at gmail.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H
+#define LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H
+
+#include <rtems.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief  Raspberry Pi GPIO functions.
+ */
+#define RPI_DIGITAL_IN  0
+#define RPI_DIGITAL_OUT 1
+#define RPI_ALT_FUNC_0  4
+#define RPI_ALT_FUNC_1  5
+#define RPI_ALT_FUNC_2  6
+#define RPI_ALT_FUNC_3  7
+#define RPI_ALT_FUNC_4  3
+#define RPI_ALT_FUNC_5  2
+#define RPI_ALT_FUNC_MASK 7
+
+/**
+ * @brief Setups a JTAG interface.
+ *
+ * @retval RTEMS_SUCCESSFUL JTAG interface successfully configured.
+ * @retval * At least one of the required pins is currently
+ *            occupied, @see rtems_gpio_request_pin_group().
+ */
+extern rtems_status_code rpi_gpio_select_jtag(void);
+
+/**
+ * @brief Setups a SPI interface.
+ *
+ * @retval RTEMS_SUCCESSFUL SPI interface successfully configured.
+ * @retval * At least one of the required pins is currently
+ *            occupied, @see rtems_gpio_request_pin_group().
+ */
+extern rtems_status_code rpi_gpio_select_spi(void);
+
+/**
+ * @brief Setups a I2C interface.
+ *
+ * @retval RTEMS_SUCCESSFUL I2C interface successfully configured.
+ * @retval * At least one of the required pins is currently
+ *            occupied, @see rtems_gpio_request_pin_group().
+ */
+extern rtems_status_code rpi_gpio_select_i2c(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_RPI_GPIO_H */
Index: bsps/arm/raspberrypi/include/bsp/spi.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/spi.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/spi.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,77 @@
+/**
+ * @file spi.h
+ *
+ * @ingroup raspberrypi_spi
+ *
+ * @brief Raspberry Pi specific SPI definitions.
+ */
+
+/*
+ *  Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_SPI_H
+#define LIBBSP_ARM_RASPBERRYPI_SPI_H
+
+#include <rtems/libi2c.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name SPI constants.
+ *
+ * @{
+ */
+
+/**
+ * @brief GPU processor core clock rate in Hz.
+ *
+ * Unless configured otherwise on a "config.txt" file present on the SD card
+ * the GPU defaults to 250 MHz. Currently only 250 MHz is supported.
+ */
+
+/* TODO: It would be nice if this value could be probed at startup, probably
+ *       using the Mailbox interface since the usual way of setting this on
+ *       the hardware is through a "config.txt" text file on the SD card.
+ *       Having this setup on the configure.ac script would require changing
+ *       the same setting on two different places. */
+#define GPU_CORE_CLOCK_RATE 250000000
+
+/** @} */
+
+/**
+ * @name SPI directives.
+ *
+ * @{
+ */
+
+/**
+ * @brief Setups the Raspberry Pi SPI bus (located on the GPIO header)
+ *        on the "/dev/spi" device file, and registers the bus on the
+ *        libi2c API.
+ *
+ * @param[in] bidirectional_mode If TRUE sets the SPI bus to use 2-wire SPI,
+ *                               where the MOSI data line doubles as the
+ *                               slave out (SO) and slave in (SI) data lines.
+ *                               If FALSE the bus defaults to the usual
+ *                               3-wire SPI, with 2 separate data lines
+ *                               (MOSI and MISO).
+ *
+ * @retval Returns libi2c bus number.
+ * @retval <0 Could not register the bus. See @see rtems_libi2c_register_bus().
+ */
+extern int rpi_spi_init(bool bidirectional_mode);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_SPI_H */
Index: bsps/arm/raspberrypi/include/bsp/usart.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/usart.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/usart.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,43 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_usart
+ *
+ * @brief USART support.
+ */
+
+
+/**
+ * @defgroup raspberrypi_usart USART Support
+ *
+ * @ingroup arm_raspberrypi
+ *
+ * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Support
+ */
+
+/*
+ * Copyright (c) 2013 Alan Cudmore.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_USART_H
+#define LIBBSP_ARM_RASPBERRYPI_USART_H
+
+#include <libchip/serial.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define USART0_DEFAULT_BAUD 115000
+
+extern const console_fns bcm2835_usart_fns;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_USART_H */
Index: bsps/arm/raspberrypi/include/bsp/vc.h
===================================================================
--- bsps/arm/raspberrypi/include/bsp/vc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/raspberrypi/include/bsp/vc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,157 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_vc
+ *
+ * @brief video core support.
+ *
+ */
+
+/*
+ * Copyright (c) 2015 Yang Qiao
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_VC_H
+#define LIBBSP_ARM_RASPBERRYPI_VC_H
+
+/**
+ * @defgroup raspberrypi_vc Register Definitions
+ *
+ * @ingroup arm_raspberrypi
+ *
+ * @brief Register Definitions
+ *
+ * @{
+ */
+
+typedef struct {
+  uint32_t width;
+  uint32_t height;
+} bcm2835_get_display_size_entries;
+
+int bcm2835_mailbox_get_display_size(
+  bcm2835_get_display_size_entries *_entries );
+
+typedef enum {
+  bcm2835_mailbox_pixel_order_bgr = 0,
+  bcm2835_mailbox_pixel_order_rgb = 1
+} bcm2835_pixel_order;
+
+typedef enum {
+  bcm2835_mailbox_alpha_mode_0_opaque       = 0,
+  bcm2835_mailbox_alpha_mode_0_transparent  = 1,
+  bcm2835_mailbox_alpha_mode_ignored        = 2
+} bcm2835_alpha_mode;
+
+typedef struct {
+  uint32_t xres;
+  uint32_t yres;
+  uint32_t xvirt;
+  uint32_t yvirt;
+  uint32_t depth;
+  bcm2835_pixel_order pixel_order;
+  bcm2835_alpha_mode alpha_mode;
+  uint32_t voffset_x;
+  uint32_t voffset_y;
+  uint32_t overscan_left;
+  uint32_t overscan_right;
+  uint32_t overscan_top;
+  uint32_t overscan_bottom;
+  uint32_t base;
+  size_t size;
+  uint32_t pitch;
+} bcm2835_init_frame_buffer_entries;
+
+int bcm2835_mailbox_init_frame_buffer(
+  bcm2835_init_frame_buffer_entries *_entries );
+
+typedef struct {
+  uint32_t pitch;
+} bcm2835_get_pitch_entries;
+
+int bcm2835_mailbox_get_pitch( bcm2835_get_pitch_entries *_entries );
+
+typedef struct {
+  char cmdline[ 1024 ];
+} bcm2835_get_cmdline_entries;
+
+int bcm2835_mailbox_get_cmdline( bcm2835_get_cmdline_entries *_entries );
+
+typedef enum {
+  bcm2835_mailbox_power_udid_sd_card = 0x00000000u,
+  bcm2835_mailbox_power_udid_uart0 = 0x00000001u,
+  bcm2835_mailbox_power_udid_uart1 = 0x00000002u,
+  bcm2835_mailbox_power_udid_usb_hcd = 0x00000003u,
+  bcm2835_mailbox_power_udid_i2c0 = 0x00000004u,
+  bcm2835_mailbox_power_udid_i2c1 = 0x00000005u,
+  bcm2835_mailbox_power_udid_i2c2 = 0x00000006u,
+  bcm2835_mailbox_power_udid_spi = 0x00000007u,
+  bcm2835_mailbox_power_udid_ccp2tx = 0x00000008u,
+} bcm2835_power_device_id;
+
+typedef struct {
+  bcm2835_power_device_id dev_id;
+  uint32_t state;
+} bcm2835_set_power_state_entries;
+
+#define BCM2835_MAILBOX_SET_POWER_STATE_REQ_ON ( 1 << 0 )
+#define BCM2835_MAILBOX_SET_POWER_STATE_REQ_WAIT ( 1 << 1 )
+#define BCM2835_MAILBOX_POWER_STATE_ON ( 1 << 0 )
+#define BCM2835_MAILBOX_POWER_STATE_NODEV ( 1 << 1 )
+int bcm2835_mailbox_set_power_state( bcm2835_set_power_state_entries *_entries );
+
+int bcm2835_mailbox_get_power_state( bcm2835_set_power_state_entries *_entries );
+
+typedef struct {
+  uint32_t base;
+  size_t size;
+} bcm2835_get_arm_memory_entries;
+
+int bcm2835_mailbox_get_arm_memory( bcm2835_get_arm_memory_entries *_entries );
+
+typedef struct {
+  uint32_t base;
+  size_t size;
+} bcm2835_get_vc_memory_entries;
+
+int bcm2835_mailbox_get_vc_memory( bcm2835_get_vc_memory_entries *_entries );
+
+typedef struct {
+  uint32_t fw_rev;
+} bcm2835_mailbox_get_fw_rev_entries;
+
+int bcm2835_mailbox_get_firmware_revision(
+  bcm2835_mailbox_get_fw_rev_entries *_entries );
+
+typedef struct {
+  uint32_t spec;
+} bcm2835_get_board_spec_entries;
+
+int bcm2835_mailbox_get_board_model( bcm2835_get_board_spec_entries *_entries );
+
+int bcm2835_mailbox_get_board_revision(
+  bcm2835_get_board_spec_entries *_entries );
+
+typedef struct {
+  uint64_t board_serial;
+} bcm2835_get_board_serial_entries;
+
+int bcm2835_mailbox_get_board_serial(
+  bcm2835_get_board_serial_entries *_entries );
+
+typedef struct {
+  uint32_t clock_id;
+  uint32_t clock_rate;
+} bcm2835_get_clock_rate_entries;
+
+int bcm2835_mailbox_get_clock_rate(
+  bcm2835_get_clock_rate_entries *_entries );
+/** @} */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_VC_H */
