Index: bsps/arm/include/bsp/arm-a8core-start.h
===================================================================
--- bsps/arm/include/bsp/arm-a8core-start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-a8core-start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,55 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief A8CORE_START Support
+ */
+
+/*
+ * Copyright (c) 2014 Chris Johns <chrisj@rtems.org>.  All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_A8CORE_START_H
+#define LIBBSP_ARM_SHARED_ARM_A8CORE_START_H
+
+#include <libcpu/arm-cp15.h>
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/arm-errata.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+BSP_START_TEXT_SECTION static inline arm_a8core_start_set_vector_base(void)
+{
+  /*
+   * Do not use bsp_vector_table_begin == 0, since this will get optimized away.
+  */
+  if (bsp_vector_table_end != bsp_vector_table_size) {
+    uint32_t ctrl;
+
+    arm_cp15_set_vector_base_address(bsp_vector_table_begin);
+
+    ctrl = arm_cp15_get_control();
+    ctrl &= ~ARM_CP15_CTRL_V;
+    arm_cp15_set_control(ctrl);
+  }
+}
+
+BSP_START_TEXT_SECTION static inline arm_a8core_start_hook_1(void)
+{
+  arm_a8core_start_set_vector_base();
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_A8CORE_START_H */
Index: bsps/arm/include/bsp/arm-a9mpcore-clock.h
===================================================================
--- bsps/arm/include/bsp/arm-a9mpcore-clock.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-a9mpcore-clock.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013 Chris Johns <chrisj@rtems.org>.  All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H
+#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H
+
+#include <rtems/counter.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Return the peripheral clock. For systems such as the zynq this
+ * is controlled by the PL logic generation and can vary. Provide this
+ * function in your application to override the BSP default.
+ */
+uint32_t a9mpcore_clock_periphclk(void);
+
+/**
+ * @brief Do early clock initialization so that the CPU counter conversion
+ * works.
+ */
+static inline void a9mpcore_clock_initialize_early(void)
+{
+  rtems_counter_initialize_converter(a9mpcore_clock_periphclk());
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H */
Index: bsps/arm/include/bsp/arm-a9mpcore-irq.h
===================================================================
--- bsps/arm/include/bsp/arm-a9mpcore-irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-a9mpcore-irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,40 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM_A9MPCORE_IRQ Support
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H
+#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define A9MPCORE_IRQ_GT 27
+#define A9MPCORE_IRQ_NFIQ 28
+#define A9MPCORE_IRQ_PT 29
+#define A9MPCORE_IRQ_PW 30
+#define A9MPCORE_IRQ_NIRQ 31
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H */
Index: bsps/arm/include/bsp/arm-a9mpcore-regs.h
===================================================================
--- bsps/arm/include/bsp/arm-a9mpcore-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-a9mpcore-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,133 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM_A9MPCORE_REGS Support
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+  uint32_t ctrl;
+#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
+#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
+#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
+#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
+#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
+#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
+#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
+  uint32_t cfg;
+#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
+#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
+#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
+#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
+#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
+#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
+#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+  uint32_t pwrst;
+  uint32_t invss;
+#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
+#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */
+#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
+#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */
+#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
+#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */
+#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
+#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
+#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
+#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+  uint32_t reserved_09[8];
+  uint32_t diagn_ctrl;
+#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
+  uint32_t reserved_10[3];
+  uint32_t fltstart;
+  uint32_t fltend;
+  uint32_t reserved_48[2];
+  uint32_t sac;
+  uint32_t snsac;
+} a9mpcore_scu;
+
+typedef struct {
+} a9mpcore_gic;
+
+typedef struct {
+  uint32_t cntrlower;
+  uint32_t cntrupper;
+#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
+#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
+#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
+#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
+#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
+  uint32_t ctrl;
+#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
+  uint32_t irqst;
+  uint32_t cmpvallower;
+  uint32_t cmpvalupper;
+  uint32_t autoinc;
+} a9mpcore_gt;
+
+typedef struct {
+  uint32_t load;
+  uint32_t cntr;
+  uint32_t ctrl;
+#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
+#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
+#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
+#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
+  uint32_t irqst;
+#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
+} a9mpcore_pt;
+
+typedef struct {
+  uint32_t load;
+  uint32_t cntr;
+  uint32_t ctrl;
+  uint32_t irqst;
+  uint32_t rstst;
+  uint32_t dis;
+} a9mpcore_pw;
+
+typedef struct {
+} a9mpcore_idist;
+
+typedef struct {
+  a9mpcore_scu scu;
+  uint32_t reserved_58[42];
+  a9mpcore_gic gic;
+  uint32_t reserved_100[64];
+  a9mpcore_gt gt;
+  uint32_t reserved_21c[249];
+  a9mpcore_pt pt;
+  uint32_t reserved_610[4];
+  a9mpcore_pw pw;
+  uint32_t reserved_638[626];
+  a9mpcore_idist idist;
+} a9mpcore;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */
Index: bsps/arm/include/bsp/arm-a9mpcore-start.h
===================================================================
--- bsps/arm/include/bsp/arm-a9mpcore-start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-a9mpcore-start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,172 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief A9MPCORE_START Support
+ */
+
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
+#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
+
+#include <rtems/score/smpimpl.h>
+
+#include <libcpu/arm-cp15.h>
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/arm-a9mpcore-regs.h>
+#include <bsp/arm-errata.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+BSP_START_TEXT_SECTION static inline void
+arm_a9mpcore_start_set_vector_base(void)
+{
+  /*
+   * Do not use bsp_vector_table_begin == 0, since this will get optimized away.
+  */
+  if (bsp_vector_table_end != bsp_vector_table_size) {
+    uint32_t ctrl;
+
+    /*
+     * For now we assume that every Cortex-A9 MPCore has the Security Extensions.
+     * Later it might be necessary to evaluate the ID_PFR1 register.
+     */
+    arm_cp15_set_vector_base_address(bsp_vector_table_begin);
+
+    ctrl = arm_cp15_get_control();
+    ctrl &= ~ARM_CP15_CTRL_V;
+    arm_cp15_set_control(ctrl);
+  }
+}
+
+BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate(
+  volatile a9mpcore_scu *scu,
+  uint32_t cpu_id,
+  uint32_t ways
+)
+{
+  scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
+}
+
+BSP_START_TEXT_SECTION static inline void
+arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
+{
+  if (arm_errata_is_applicable_processor_errata_764369()) {
+    scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
+  }
+}
+
+BSP_START_TEXT_SECTION static inline void
+arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
+{
+  scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
+  arm_a9mpcore_start_errata_764369_handler(scu);
+}
+
+#ifdef RTEMS_SMP
+BSP_START_TEXT_SECTION static inline void
+arm_a9mpcore_start_on_secondary_processor(void)
+{
+  uint32_t ctrl;
+
+  arm_a9mpcore_start_set_vector_base();
+
+  arm_gic_irq_initialize_secondary_cpu();
+
+  ctrl = arm_cp15_start_setup_mmu_and_cache(
+    0,
+    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
+  );
+
+  arm_cp15_set_domain_access_control(
+    ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
+  );
+
+  /* FIXME: Sharing the translation table between processors is brittle */
+  arm_cp15_set_translation_table_base(
+    (uint32_t *) bsp_translation_table_base
+  );
+
+  ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
+  arm_cp15_set_control(ctrl);
+
+  _SMP_Start_multitasking_on_secondary_processor();
+}
+
+BSP_START_TEXT_SECTION static inline void
+arm_a9mpcore_start_enable_smp_in_auxiliary_control(void)
+{
+  /*
+   * Enable cache coherency support and cache/MMU maintenance broadcasts for
+   * this processor.
+   */
+  uint32_t actlr = arm_cp15_get_auxiliary_control();
+  actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
+  arm_cp15_set_auxiliary_control(actlr);
+}
+#endif
+
+BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
+{
+  volatile a9mpcore_scu *scu =
+    (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
+  uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
+
+  arm_cp15_branch_predictor_invalidate_all();
+
+  if (cpu_id == 0) {
+    arm_a9mpcore_start_scu_enable(scu);
+  }
+
+#ifdef RTEMS_SMP
+  arm_a9mpcore_start_enable_smp_in_auxiliary_control();
+#endif
+
+  arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
+
+#ifdef RTEMS_SMP
+  if (cpu_id != 0) {
+    arm_a9mpcore_start_on_secondary_processor();
+  }
+#endif
+}
+
+BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void)
+{
+  volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE;
+
+  gt->ctrl = 0;
+  gt->cntrlower = 0;
+  gt->cntrupper = 0;
+  gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
+}
+
+BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void)
+{
+  arm_a9mpcore_start_global_timer();
+  arm_a9mpcore_start_set_vector_base();
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */
Index: bsps/arm/include/bsp/arm-cp15-start.h
===================================================================
--- bsps/arm/include/bsp/arm-cp15-start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-cp15-start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,187 @@
+/**
+ * @file
+ *
+ * @ingroup arm_start
+ *
+ * @brief Arm CP15 start.
+ */
+
+
+/*
+ * Copyright (c) 2013 Hesham AL-Matary.
+ * Copyright (c) 2009-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H
+#define LIBBSP_ARM_SHARED_ARM_CP15_START_H
+
+#include <libcpu/arm-cp15.h>
+#include <bsp/start.h>
+#include <bsp/linker-symbols.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+  uint32_t begin;
+  uint32_t end;
+  uint32_t flags;
+} arm_cp15_start_section_config;
+
+#define ARMV7_CP15_START_DEFAULT_SECTIONS \
+  { \
+    .begin = (uint32_t) bsp_section_fast_text_begin, \
+    .end = (uint32_t) bsp_section_fast_text_end, \
+    .flags = ARMV7_MMU_CODE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_fast_data_begin, \
+    .end = (uint32_t) bsp_section_fast_data_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_start_begin, \
+    .end = (uint32_t) bsp_section_start_end, \
+    .flags = ARMV7_MMU_CODE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_vector_begin, \
+    .end = (uint32_t) bsp_section_vector_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_text_begin, \
+    .end = (uint32_t) bsp_section_text_end, \
+    .flags = ARMV7_MMU_CODE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_rodata_begin, \
+    .end = (uint32_t) bsp_section_rodata_end, \
+    .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_data_begin, \
+    .end = (uint32_t) bsp_section_data_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_bss_begin, \
+    .end = (uint32_t) bsp_section_bss_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_work_begin, \
+    .end = (uint32_t) bsp_section_work_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_stack_begin, \
+    .end = (uint32_t) bsp_section_stack_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }, { \
+    .begin = (uint32_t) bsp_section_nocache_begin, \
+    .end = (uint32_t) bsp_section_nocache_end, \
+    .flags = ARMV7_MMU_DEVICE \
+  }, { \
+    .begin = (uint32_t) bsp_section_nocachenoload_begin, \
+    .end = (uint32_t) bsp_section_nocachenoload_end, \
+    .flags = ARMV7_MMU_DEVICE \
+  }, { \
+    .begin = (uint32_t) bsp_translation_table_base, \
+    .end = (uint32_t) bsp_translation_table_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
+  }
+
+BSP_START_DATA_SECTION extern const arm_cp15_start_section_config
+  arm_cp15_start_mmu_config_table[];
+
+BSP_START_DATA_SECTION extern const size_t
+  arm_cp15_start_mmu_config_table_size;
+
+BSP_START_TEXT_SECTION static inline void
+arm_cp15_start_set_translation_table_entries(
+  uint32_t *ttb,
+  const arm_cp15_start_section_config *config
+)
+{
+  uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
+  uint32_t iend =
+    ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
+  uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
+
+  if (config->begin != config->end) {
+    while (i != iend) {
+      ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
+      i = (i + 1U) & index_mask;
+    }
+  }
+}
+
+BSP_START_TEXT_SECTION static inline void
+arm_cp15_start_setup_translation_table(
+  uint32_t *ttb,
+  uint32_t client_domain,
+  const arm_cp15_start_section_config *config_table,
+  size_t config_count
+)
+{
+  uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT);
+  size_t i;
+
+  arm_cp15_set_domain_access_control(dac);
+  arm_cp15_set_translation_table_base(ttb);
+
+  /* Initialize translation table with invalid entries */
+  for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
+    ttb [i] = 0;
+  }
+
+  for (i = 0; i < config_count; ++i) {
+    arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]);
+  }
+}
+
+BSP_START_TEXT_SECTION static inline void
+arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
+  uint32_t ctrl,
+  uint32_t *ttb,
+  uint32_t client_domain,
+  const arm_cp15_start_section_config *config_table,
+  size_t config_count
+)
+{
+  arm_cp15_start_setup_translation_table(
+    ttb,
+    client_domain,
+    config_table,
+    config_count
+  );
+
+  /* Enable MMU and cache */
+  ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
+
+  arm_cp15_set_control(ctrl);
+}
+
+BSP_START_TEXT_SECTION static inline uint32_t
+arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set)
+{
+  uint32_t ctrl = arm_cp15_get_control();
+
+  ctrl &= ~ctrl_clear;
+  ctrl |= ctrl_set;
+
+  arm_cp15_set_control(ctrl);
+
+  arm_cp15_tlb_invalidate();
+
+  return ctrl;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */
Index: bsps/arm/include/bsp/arm-errata.h
===================================================================
--- bsps/arm/include/bsp/arm-errata.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-errata.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,121 @@
+/**
+ * @file arm-errata.h
+ *
+ * @ingroup arm_shared
+ *
+ * @brief Create #defines which state which erratas shall get applied
+ */
+
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef ARM_ERRATA_H_
+#define ARM_ERRATA_H_
+
+#include <bsp/arm-release-id.h>
+#include <libcpu/arm-cp15.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+static inline arm_release_id arm_errata_get_processor_release(void)
+{
+  const uint32_t MIDR          = arm_cp15_get_id_code();
+  const uint8_t  REVISION      = (MIDR & 0xF00000U) >> 20;
+  const uint8_t  PATCH_LEVEL   = (MIDR & 0xFU);
+
+  return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL(
+    REVISION,
+    PATCH_LEVEL
+  );
+}
+
+static inline bool arm_errata_is_applicable_processor_errata_764369(void)
+{
+#if defined(RTEMS_SMP)
+  const arm_release_id RELEASE       = arm_errata_get_processor_release();
+  bool                 is_applicable = false;
+
+  /* Errata information for Cortex-A9 processors.
+   * Information taken from ARMs
+   * "Cortex-A series processors
+   * - Cortex-A9
+   * - Software Developers Errata Notice
+   * - Revision r4 revisions
+   * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice"
+   * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
+   * Please see this document for more information on these erratas */
+
+  switch( RELEASE ) {
+    case ARM_RELEASE_ID_R4_P1:
+    case ARM_RELEASE_ID_R4_P4:
+    case ARM_RELEASE_ID_R3_P0:
+    case ARM_RELEASE_ID_R2_P10:
+    case ARM_RELEASE_ID_R2_P8:
+    case ARM_RELEASE_ID_R2_P6:
+    case ARM_RELEASE_ID_R2_P4:
+    case ARM_RELEASE_ID_R2_P3:
+    case ARM_RELEASE_ID_R2_P2:
+    case ARM_RELEASE_ID_R2_P0:
+      is_applicable = true;
+      break;
+    default:
+      is_applicable = false;
+      break;
+  }
+
+  return is_applicable;
+#else
+  return false;
+#endif
+}
+
+static inline bool arm_errata_is_applicable_processor_errata_775420(void)
+{
+  const arm_release_id RELEASE       = arm_errata_get_processor_release();
+  bool                 is_applicable = false;
+
+  /* Errata information for Cortex-A9 processors.
+  * Information taken from ARMs
+  * "Cortex-A series processors
+  * - Cortex-A9
+  * - Software Developers Errata Notice
+  * - Revision r4 revisions
+  * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice"
+  * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
+  * Please see this document for more information on these erratas */
+
+  switch( RELEASE ) {
+    case ARM_RELEASE_ID_R2_P10:
+    case ARM_RELEASE_ID_R2_P8:
+    case ARM_RELEASE_ID_R2_P6:
+    case ARM_RELEASE_ID_R2_P4:
+    case ARM_RELEASE_ID_R2_P3:
+    case ARM_RELEASE_ID_R2_P2:
+      is_applicable = true;
+      break;
+    default:
+      is_applicable = false;
+      break;
+  }
+
+  return is_applicable;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ARM_ERRATA_H_ */
Index: bsps/arm/include/bsp/arm-gic-irq.h
===================================================================
--- bsps/arm/include/bsp/arm-gic-irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-gic-irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,112 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_gic
+ *
+ *  @brief ARM GIC IRQ
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
+#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
+
+#include <bsp.h>
+#include <bsp/arm-gic.h>
+#include <rtems/score/processormask.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define ARM_GIC_IRQ_SGI_0 0
+#define ARM_GIC_IRQ_SGI_1 1
+#define ARM_GIC_IRQ_SGI_2 2
+#define ARM_GIC_IRQ_SGI_3 3
+#define ARM_GIC_IRQ_SGI_5 5
+#define ARM_GIC_IRQ_SGI_6 6
+#define ARM_GIC_IRQ_SGI_7 7
+#define ARM_GIC_IRQ_SGI_8 8
+#define ARM_GIC_IRQ_SGI_9 9
+#define ARM_GIC_IRQ_SGI_10 10 
+#define ARM_GIC_IRQ_SGI_11 11
+#define ARM_GIC_IRQ_SGI_12 12
+#define ARM_GIC_IRQ_SGI_13 13
+#define ARM_GIC_IRQ_SGI_14 14
+#define ARM_GIC_IRQ_SGI_15 15
+
+#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
+
+rtems_status_code arm_gic_irq_set_priority(
+  rtems_vector_number vector,
+  uint8_t priority
+);
+
+rtems_status_code arm_gic_irq_get_priority(
+  rtems_vector_number vector,
+  uint8_t *priority
+);
+
+void bsp_interrupt_set_affinity(
+  rtems_vector_number vector,
+  const Processor_mask *affinity
+);
+
+void bsp_interrupt_get_affinity(
+  rtems_vector_number vector,
+  Processor_mask *affinity
+);
+
+typedef enum {
+  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
+  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF
+} arm_gic_irq_software_irq_target_filter;
+
+static inline rtems_status_code arm_gic_irq_generate_software_irq(
+  rtems_vector_number vector,
+  arm_gic_irq_software_irq_target_filter filter,
+  uint8_t targets
+)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if (vector <= ARM_GIC_IRQ_SGI_15) {
+    volatile gic_dist *dist = ARM_GIC_DIST;
+
+    dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
+      | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
+      | GIC_DIST_ICDSGIR_SGIINTID(vector);
+  } else {
+    sc = RTEMS_INVALID_ID;
+  }
+
+  return sc;
+}
+
+static inline uint32_t arm_gic_irq_processor_count(void)
+{
+  volatile gic_dist *dist = ARM_GIC_DIST;
+
+  return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
+}
+
+void arm_gic_irq_initialize_secondary_cpu(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
Index: bsps/arm/include/bsp/arm-gic-regs.h
===================================================================
--- bsps/arm/include/bsp/arm-gic-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-gic-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,138 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_gic
+ *
+ *  @brief ARM GIC Register definitions
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+  uint32_t iccicr;
+#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
+  uint32_t iccpmr;
+#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
+#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+  uint32_t iccbpr;
+#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
+#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+  uint32_t icciar;
+#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12)
+#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
+#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
+#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9)
+#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+  uint32_t icceoir;
+#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12)
+#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
+#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
+#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9)
+#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+  uint32_t iccrpr;
+#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7)
+#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+  uint32_t icchpir;
+#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12)
+#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
+#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
+#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9)
+#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+  uint32_t iccabpr;
+#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
+#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+  uint32_t reserved_20[55];
+  uint32_t icciidr;
+#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
+#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19)
+#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19)
+#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
+#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
+#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
+#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
+#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
+} gic_cpuif;
+
+typedef struct {
+  uint32_t icddcr;
+#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
+  uint32_t icdictr;
+#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
+#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15)
+#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
+#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10)
+#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7)
+#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7)
+#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
+#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4)
+#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+  uint32_t icdiidr;
+#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
+#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19)
+#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19)
+#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
+#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
+#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
+#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
+#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
+  uint32_t reserved_0c[29];
+  uint32_t icdisr[32];
+  uint32_t icdiser[32];
+  uint32_t icdicer[32];
+  uint32_t icdispr[32];
+  uint32_t icdicpr[32];
+  uint32_t icdabr[32];
+  uint32_t reserved_380[32];
+  uint8_t icdipr[256];
+  uint32_t reserved_500[192];
+  uint8_t icdiptr[256];
+  uint32_t reserved_900[192];
+  uint32_t icdicfr[64];
+  uint32_t reserved_d00[128];
+  uint32_t icdsgir;
+#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25)
+#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25)
+#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
+#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23)
+#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define GIC_DIST_ICDSGIR_SATT BSP_BIT32(15)
+#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
+#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+} gic_dist;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */
Index: bsps/arm/include/bsp/arm-gic-tm27.h
===================================================================
--- bsps/arm/include/bsp/arm-gic-tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-gic-tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,103 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_gic
+ *
+ *  @brief ARM GIC TM27 Support
+ */
+
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
+#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
+
+#include <assert.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12
+
+#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13
+
+#define ARM_GIC_TM27_PRIO_LOW 0x80
+
+#define ARM_GIC_TM27_PRIO_HIGH 0x00
+
+static inline void Install_tm27_vector(void (*handler)(rtems_vector_number))
+{
+  rtems_status_code sc = rtems_interrupt_handler_install(
+    ARM_GIC_TM27_IRQ_LOW,
+    "tm27 low",
+    RTEMS_INTERRUPT_UNIQUE,
+    (rtems_interrupt_handler) handler,
+    NULL
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+
+  sc = arm_gic_irq_set_priority(
+    ARM_GIC_TM27_IRQ_LOW,
+    ARM_GIC_TM27_PRIO_LOW
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+
+  sc = rtems_interrupt_handler_install(
+    ARM_GIC_TM27_IRQ_HIGH,
+    "tm27 high",
+    RTEMS_INTERRUPT_UNIQUE,
+    (rtems_interrupt_handler) handler,
+    NULL
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+
+  sc = arm_gic_irq_set_priority(
+    ARM_GIC_TM27_IRQ_HIGH,
+    ARM_GIC_TM27_PRIO_HIGH
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+static inline void Cause_tm27_intr(void)
+{
+  rtems_status_code sc = arm_gic_irq_generate_software_irq(
+    ARM_GIC_TM27_IRQ_LOW,
+    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
+    0
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+static inline void Clear_tm27_intr(void)
+{
+  /* Nothing to do */
+}
+
+static inline void Lower_tm27_intr(void)
+{
+  rtems_status_code sc = arm_gic_irq_generate_software_irq(
+    ARM_GIC_TM27_IRQ_HIGH,
+    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
+    0
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */
Index: bsps/arm/include/bsp/arm-gic.h
===================================================================
--- bsps/arm/include/bsp/arm-gic.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-gic.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,207 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_gic
+ *
+ *  @brief ARM GIC Support
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H
+#define LIBBSP_ARM_SHARED_ARM_GIC_H
+
+#include <bsp/arm-gic-regs.h>
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ *  @defgroup arm_gic ARM GIC
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM_GIC Support Package
+ */
+
+#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5)
+#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU))
+
+#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4)
+#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1)
+
+static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  return (dist->icdiser[i] & bit) != 0;
+}
+
+static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  dist->icdiser[i] = bit;
+}
+
+static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  dist->icdicer[i] = bit;
+}
+
+static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  return (dist->icdispr[i] & bit) != 0;
+}
+
+static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  dist->icdispr[i] = bit;
+}
+
+static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  dist->icdicpr[i] = bit;
+}
+
+static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  return (dist->icdabr[i] & bit) != 0;
+}
+
+static inline void gic_id_set_priority(
+  volatile gic_dist *dist,
+  uint32_t id,
+  uint8_t priority
+)
+{
+  dist->icdipr[id] = priority;
+}
+
+static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id)
+{
+  return dist->icdipr[id];
+}
+
+static inline void gic_id_set_targets(
+  volatile gic_dist *dist,
+  uint32_t id,
+  uint8_t targets
+)
+{
+  dist->icdiptr[id] = targets;
+}
+
+static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id)
+{
+  return dist->icdiptr[id];
+}
+
+typedef enum {
+  GIC_LEVEL_SENSITIVE,
+  GIC_EDGE_TRIGGERED
+} gic_trigger_mode;
+
+static inline gic_trigger_mode gic_id_get_trigger_mode(
+  volatile gic_dist *dist,
+  uint32_t id
+)
+{
+  uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id);
+  uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1;
+  uint32_t bit = 1U << o;
+
+  return (dist->icdicfr[i] & bit) != 0 ?
+    GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE;
+}
+
+static inline void gic_id_set_trigger_mode(
+  volatile gic_dist *dist,
+  uint32_t id,
+  gic_trigger_mode mode
+)
+{
+  uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id);
+  uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1;
+  uint32_t bit = mode << o;
+  uint32_t mask = 1U << o;
+  uint32_t icdicfr = dist->icdicfr[i];
+
+  icdicfr &= ~mask;
+  icdicfr |= bit;
+
+  dist->icdicfr[i] = icdicfr;
+}
+
+typedef enum {
+  GIC_N_TO_N,
+  GIC_1_TO_N
+} gic_handling_model;
+
+static inline gic_handling_model gic_id_get_handling_model(
+  volatile gic_dist *dist,
+  uint32_t id
+)
+{
+  uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id);
+  uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id);
+  uint32_t bit = 1U << o;
+
+  return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N;
+}
+
+static inline void gic_id_set_handling_model(
+  volatile gic_dist *dist,
+  uint32_t id,
+  gic_handling_model model
+)
+{
+  uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id);
+  uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id);
+  uint32_t bit = model << o;
+  uint32_t mask = 1U << o;
+  uint32_t icdicfr = dist->icdicfr[i];
+
+  icdicfr &= ~mask;
+  icdicfr |= bit;
+
+  dist->icdicfr[i] = icdicfr;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */
Index: bsps/arm/include/bsp/arm-pl011-regs.h
===================================================================
--- bsps/arm/include/bsp/arm-pl011-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-pl011-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,130 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM PL011 Register definitions
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+  uint32_t uartdr;
+#define PL011_UARTDR_OE BSP_BIT32(11)
+#define PL011_UARTDR_BE BSP_BIT32(10)
+#define PL011_UARTDR_PE BSP_BIT32(9)
+#define PL011_UARTDR_FE BSP_BIT32(8)
+#define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7)
+#define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+  uint32_t uartrsr_uartecr;
+#define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3)
+#define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2)
+#define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1)
+#define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0)
+  uint32_t reserved_08[4];
+  uint32_t uartfr;
+#define PL011_UARTFR_RI BSP_BIT32(8)
+#define PL011_UARTFR_TXFE BSP_BIT32(7)
+#define PL011_UARTFR_RXFF BSP_BIT32(6)
+#define PL011_UARTFR_TXFF BSP_BIT32(5)
+#define PL011_UARTFR_RXFE BSP_BIT32(4)
+#define PL011_UARTFR_BUSY BSP_BIT32(3)
+#define PL011_UARTFR_DCD BSP_BIT32(2)
+#define PL011_UARTFR_DSR BSP_BIT32(1)
+#define PL011_UARTFR_CTS BSP_BIT32(0)
+  uint32_t reserved_1c;
+  uint32_t uartilpr;
+#define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7)
+#define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+  uint32_t uartibrd;
+#define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15)
+#define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+  uint32_t uartfbrd;
+#define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5)
+#define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+  uint32_t uartlcr_h;
+#define PL011_UARTLCR_H_SPS BSP_BIT32(7)
+#define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6)
+#define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6)
+#define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
+#define PL011_UARTLCR_H_WLEN_5 0x00U
+#define PL011_UARTLCR_H_WLEN_6 0x01U
+#define PL011_UARTLCR_H_WLEN_7 0x02U
+#define PL011_UARTLCR_H_WLEN_8 0x03U
+#define PL011_UARTLCR_H_FEN BSP_BIT32(4)
+#define PL011_UARTLCR_H_STP2 BSP_BIT32(3)
+#define PL011_UARTLCR_H_EPS BSP_BIT32(2)
+#define PL011_UARTLCR_H_PEN BSP_BIT32(1)
+#define PL011_UARTLCR_H_BRK BSP_BIT32(0)
+  uint32_t uartcr;
+#define PL011_UARTCR_CTSEN BSP_BIT32(15)
+#define PL011_UARTCR_RTSEN BSP_BIT32(14)
+#define PL011_UARTCR_OUT2 BSP_BIT32(13)
+#define PL011_UARTCR_OUT1 BSP_BIT32(12)
+#define PL011_UARTCR_RTS BSP_BIT32(11)
+#define PL011_UARTCR_DTR BSP_BIT32(10)
+#define PL011_UARTCR_RXE BSP_BIT32(9)
+#define PL011_UARTCR_TXE BSP_BIT32(8)
+#define PL011_UARTCR_LBE BSP_BIT32(7)
+#define PL011_UARTCR_SIRLP BSP_BIT32(3)
+#define PL011_UARTCR_SIREN BSP_BIT32(2)
+#define PL011_UARTCR_UARTEN BSP_BIT32(1)
+  uint32_t uartifls;
+#define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
+#define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)
+#define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+  uint32_t uartimsc;
+  uint32_t uartris;
+  uint32_t uartmis;
+  uint32_t uarticr;
+#define PL011_UARTI_OEI BSP_BIT32(10)
+#define PL011_UARTI_BEI BSP_BIT32(9)
+#define PL011_UARTI_PEI BSP_BIT32(8)
+#define PL011_UARTI_FEI BSP_BIT32(7)
+#define PL011_UARTI_RTI BSP_BIT32(6)
+#define PL011_UARTI_TXI BSP_BIT32(5)
+#define PL011_UARTI_RXI BSP_BIT32(4)
+#define PL011_UARTI_DSRMI BSP_BIT32(3)
+#define PL011_UARTI_DCDMI BSP_BIT32(2)
+#define PL011_UARTI_CTSMI BSP_BIT32(1)
+#define PL011_UARTI_RIMI BSP_BIT32(0)
+  uint32_t uartdmacr;
+#define PL011_UARTDMACR_DMAONERR BSP_BIT32(2)
+#define PL011_UARTDMACR_TXDMAE BSP_BIT32(1)
+#define PL011_UARTDMACR_RXDMAE BSP_BIT32(0)
+  uint32_t reserved_4c[997];
+  uint32_t uartperiphid0;
+  uint32_t uartperiphid1;
+  uint32_t uartperiphid2;
+  uint32_t uartperiphid3;
+  uint32_t uartpcellid0;
+  uint32_t uartpcellid1;
+  uint32_t uartpcellid2;
+  uint32_t uartpcellid3;
+} pl011;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */
Index: bsps/arm/include/bsp/arm-pl011.h
===================================================================
--- bsps/arm/include/bsp/arm-pl011.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-pl011.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,51 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM PL011 Support Package
+ */
+
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL011_H
+#define LIBBSP_ARM_SHARED_ARM_PL011_H
+
+#include <rtems/termiostypes.h>
+
+#include <bsp/arm-pl011-regs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+  rtems_termios_device_context base;
+  volatile pl011 *regs;
+  rtems_vector_number irq;
+  uint32_t initial_baud;
+} arm_pl011_context;
+
+bool arm_pl011_probe(rtems_termios_device_context *base);
+
+void arm_pl011_write_polled(rtems_termios_device_context *base, char c);
+
+extern const rtems_termios_device_handler arm_pl011_fns;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL011_H */
Index: bsps/arm/include/bsp/arm-pl050-regs.h
===================================================================
--- bsps/arm/include/bsp/arm-pl050-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-pl050-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,57 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM PL050 Register Definitions
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL050_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_PL050_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+	uint32_t kmicr;
+#define PL050_KMICR_KMITYPE BSP_BIT32(5)
+#define PL050_KMICR_KMIRXINTREN BSP_BIT32(4)
+#define PL050_KMICR_KMITXINTREN BSP_BIT32(3)
+#define PL050_KMICR_KMIEN BSP_BIT32(2)
+#define PL050_KMICR_FKMID BSP_BIT32(1)
+#define PL050_KMICR_FKMIC BSP_BIT32(0)
+	uint32_t kmistat;
+#define PL050_KMISTAT_TXEMPTY BSP_BIT32(6)
+#define PL050_KMISTAT_TXBUSY BSP_BIT32(5)
+#define PL050_KMISTAT_RXFULL BSP_BIT32(4)
+#define PL050_KMISTAT_RXBUSY BSP_BIT32(3)
+#define PL050_KMISTAT_RXPARITY BSP_BIT32(2)
+#define PL050_KMISTAT_KMIC BSP_BIT32(1)
+#define PL050_KMISTAT_KMID BSP_BIT32(0)
+	uint32_t kmidata;
+#define PL050_KMIDATA_KMIDATA(val) BSP_FLD32(val, 0, 7)
+#define PL050_KMIDATA_KMIDATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define PL050_KMIDATA_KMIDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+	uint32_t kmiclkdiv;
+#define PL050_KMICLKDIV_KMICLKDIV(val) BSP_FLD32(val, 0, 3)
+#define PL050_KMICLKDIV_KMICLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define PL050_KMICLKDIV_KMICLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+	uint32_t kmiir;
+#define PL050_KMIIR_KMITXINTR BSP_BIT32(1)
+#define PL050_KMIIR_KMIRXINTR BSP_BIT32(0)
+} pl050;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL050_REGS_H */
Index: bsps/arm/include/bsp/arm-pl050.h
===================================================================
--- bsps/arm/include/bsp/arm-pl050.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-pl050.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,47 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM PL050 Support
+ */
+
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL050_H
+#define LIBBSP_ARM_SHARED_ARM_PL050_H
+
+#include <rtems/termiostypes.h>
+
+#include <bsp/arm-pl050-regs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+  rtems_termios_device_context base;
+  volatile pl050 *regs;
+  rtems_vector_number irq;
+  uint32_t initial_baud;
+} arm_pl050_context;
+
+extern const rtems_termios_device_handler arm_pl050_fns;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL050_H */
Index: bsps/arm/include/bsp/arm-pl111-fb.h
===================================================================
--- bsps/arm/include/bsp/arm-pl111-fb.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-pl111-fb.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,44 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM PL111 FB Support
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL111_FB_H
+#define LIBBSP_ARM_SHARED_ARM_PL111_FB_H
+
+#include <bsp/arm-pl111-regs.h>
+
+typedef struct pl111_fb_config {
+  volatile pl111 *regs;
+  uint32_t timing0;
+  uint32_t timing1;
+  uint32_t timing2;
+  uint32_t timing3;
+  uint32_t control;
+  uint32_t power_delay_in_us;
+  void (*set_up)(const struct pl111_fb_config *cfg);
+  void (*pins_set_up)(const struct pl111_fb_config *cfg);
+  void (*pins_tear_down)(const struct pl111_fb_config *cfg);
+  void (*tear_down)(const struct pl111_fb_config *cfg);
+} pl111_fb_config;
+
+const pl111_fb_config *arm_pl111_fb_get_config(void);
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL111_FB_H */
Index: bsps/arm/include/bsp/arm-pl111-regs.h
===================================================================
--- bsps/arm/include/bsp/arm-pl111-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-pl111-regs.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,184 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARM PL111 Register definitions
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+	uint32_t timing0;
+#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7)
+#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
+#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7)
+#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15)
+#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23)
+#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31)
+#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+	uint32_t timing1;
+#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9)
+#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15)
+#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
+#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15)
+#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23)
+#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31)
+#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+	uint32_t timing2;
+#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4)
+#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5)
+#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10)
+#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
+#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
+#define PL111_LCD_TIMING2_IVS BSP_BIT32(11)
+#define PL111_LCD_TIMING2_IHS BSP_BIT32(12)
+#define PL111_LCD_TIMING2_IPC BSP_BIT32(13)
+#define PL111_LCD_TIMING2_IOE BSP_BIT32(14)
+#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25)
+#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
+#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
+#define PL111_LCD_TIMING2_BCD BSP_BIT32(26)
+#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31)
+#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
+#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31)
+	uint32_t timing3;
+#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6)
+#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6)
+#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
+#define PL111_LCD_TIMING3_LEE BSP_BIT32(16)
+	uint32_t upbase;
+	uint32_t lpbase;
+	uint32_t control;
+#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0)
+#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3)
+#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
+#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3)
+#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U
+#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U
+#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U
+#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U
+#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U
+#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U
+#define PL111_LCD_CONTROL_LCD_BPP_16 0x06U
+#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U
+#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4)
+#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5)
+#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6)
+#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7)
+#define PL111_LCD_CONTROL_BGR BSP_BIT32(8)
+#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9)
+#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10)
+#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11)
+#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13)
+#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
+#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
+#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16)
+	uint32_t imsc;
+	uint32_t ris;
+	uint32_t mis;
+	uint32_t icr;
+#define PL111_LCD_I_FUF BSP_BIT32(1)
+#define PL111_LCD_I_LNBU BSP_BIT32(2)
+#define PL111_LCD_I_VCOMP BSP_BIT32(3)
+#define PL111_LCD_I_MBERROR BSP_BIT32(4)
+	uint32_t upcurr;
+	uint32_t lpcurr;
+	uint32_t reserved_34[115];
+	uint16_t pal[256];
+#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
+#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4)
+#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4)
+#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
+#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9)
+#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9)
+#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
+#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14)
+#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14)
+#define PL111_LCD_PAL_I BSP_BIT16(15)
+} pl111_lcd;
+
+typedef struct {
+	uint8_t image[1024];
+	uint32_t ctrl;
+#define PL111_CRSR_CTRL_ON BSP_BIT32(0)
+#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5)
+#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5)
+#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
+	uint32_t config;
+#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0)
+#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1)
+	uint32_t palette0;
+	uint32_t palette1;
+#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7)
+#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15)
+#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23)
+#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+	uint32_t xy;
+#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9)
+#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11)
+#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11)
+#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11)
+#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25)
+#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25)
+#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
+#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27)
+#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27)
+#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27)
+	uint32_t clip;
+#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5)
+#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13)
+#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13)
+#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
+	uint32_t imsc;
+	uint32_t icr;
+	uint32_t ris;
+	uint32_t mis;
+#define PL111_CRSR_I_CRSR BSP_BIT32(0)
+} pl111_crsr;
+
+typedef struct {
+	pl111_lcd lcd;
+	uint32_t reserved_400[256];
+	pl111_crsr crsr;
+} pl111;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */
Index: bsps/arm/include/bsp/arm-release-id.h
===================================================================
--- bsps/arm/include/bsp/arm-release-id.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/arm-release-id.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,152 @@
+/**
+ * @file arm-release-id.h
+ *
+ * @ingroup arm_shared
+ *
+ * @brief Create #defines for release IDs
+ */
+
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef ARM_RELEASE_ID_H_
+#define ARM_RELEASE_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* #define the IDs which identify a release. This must be done
+ * prior to #including bsp.h */
+#define ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( release_no, patch_level ) \
+  ( ( ( ( release_no ) & 0xFFFF ) << 16 ) + ( ( patch_level ) & 0xFFFF ) )
+
+typedef enum {
+  ARM_RELEASE_ID_R0_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 0 ),
+  ARM_RELEASE_ID_R0_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 1 ),
+  ARM_RELEASE_ID_R0_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 2 ),
+  ARM_RELEASE_ID_R0_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 3 ),
+  ARM_RELEASE_ID_R0_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 4 ),
+  ARM_RELEASE_ID_R0_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 5 ),
+  ARM_RELEASE_ID_R0_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 6 ),
+  ARM_RELEASE_ID_R0_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 7 ),
+  ARM_RELEASE_ID_R0_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 8 ),
+  ARM_RELEASE_ID_R0_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 9 ),
+  ARM_RELEASE_ID_R0_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 10 ),
+  ARM_RELEASE_ID_R1_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 0 ),
+  ARM_RELEASE_ID_R1_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 1 ),
+  ARM_RELEASE_ID_R1_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 2 ),
+  ARM_RELEASE_ID_R1_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 3 ),
+  ARM_RELEASE_ID_R1_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 4 ),
+  ARM_RELEASE_ID_R1_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 5 ),
+  ARM_RELEASE_ID_R1_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 6 ),
+  ARM_RELEASE_ID_R1_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 7 ),
+  ARM_RELEASE_ID_R1_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 8 ),
+  ARM_RELEASE_ID_R1_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 9 ),
+  ARM_RELEASE_ID_R1_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 10 ),
+  ARM_RELEASE_ID_R2_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 0 ),
+  ARM_RELEASE_ID_R2_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 1 ),
+  ARM_RELEASE_ID_R2_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 2 ),
+  ARM_RELEASE_ID_R2_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 3 ),
+  ARM_RELEASE_ID_R2_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 4 ),
+  ARM_RELEASE_ID_R2_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 5 ),
+  ARM_RELEASE_ID_R2_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 6 ),
+  ARM_RELEASE_ID_R2_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 7 ),
+  ARM_RELEASE_ID_R2_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 8 ),
+  ARM_RELEASE_ID_R2_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 9 ),
+  ARM_RELEASE_ID_R2_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 10 ),
+  ARM_RELEASE_ID_R3_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 0 ),
+  ARM_RELEASE_ID_R3_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 1 ),
+  ARM_RELEASE_ID_R3_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 2 ),
+  ARM_RELEASE_ID_R3_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 3 ),
+  ARM_RELEASE_ID_R3_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 4 ),
+  ARM_RELEASE_ID_R3_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 5 ),
+  ARM_RELEASE_ID_R3_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 6 ),
+  ARM_RELEASE_ID_R3_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 7 ),
+  ARM_RELEASE_ID_R3_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 8 ),
+  ARM_RELEASE_ID_R3_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 9 ),
+  ARM_RELEASE_ID_R3_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 10 ),
+  ARM_RELEASE_ID_R4_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 0 ),
+  ARM_RELEASE_ID_R4_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 1 ),
+  ARM_RELEASE_ID_R4_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 2 ),
+  ARM_RELEASE_ID_R4_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 3 ),
+  ARM_RELEASE_ID_R4_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 4 ),
+  ARM_RELEASE_ID_R4_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 5 ),
+  ARM_RELEASE_ID_R4_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 6 ),
+  ARM_RELEASE_ID_R4_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 7 ),
+  ARM_RELEASE_ID_R4_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 8 ),
+  ARM_RELEASE_ID_R4_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 9 ),
+  ARM_RELEASE_ID_R4_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 10 ),
+  ARM_RELEASE_ID_R5_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 0 ),
+  ARM_RELEASE_ID_R5_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 1 ),
+  ARM_RELEASE_ID_R5_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 2 ),
+  ARM_RELEASE_ID_R5_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 3 ),
+  ARM_RELEASE_ID_R5_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 4 ),
+  ARM_RELEASE_ID_R5_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 5 ),
+  ARM_RELEASE_ID_R5_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 6 ),
+  ARM_RELEASE_ID_R5_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 7 ),
+  ARM_RELEASE_ID_R5_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 8 ),
+  ARM_RELEASE_ID_R5_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 9 ),
+  ARM_RELEASE_ID_R5_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 10 ),
+  ARM_RELEASE_ID_R6_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 0 ),
+  ARM_RELEASE_ID_R6_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 1 ),
+  ARM_RELEASE_ID_R6_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 2 ),
+  ARM_RELEASE_ID_R6_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 3 ),
+  ARM_RELEASE_ID_R6_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 4 ),
+  ARM_RELEASE_ID_R6_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 5 ),
+  ARM_RELEASE_ID_R6_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 6 ),
+  ARM_RELEASE_ID_R6_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 7 ),
+  ARM_RELEASE_ID_R6_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 8 ),
+  ARM_RELEASE_ID_R6_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 9 ),
+  ARM_RELEASE_ID_R6_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 10 ),
+  ARM_RELEASE_ID_R7_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 0 ),
+  ARM_RELEASE_ID_R7_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 1 ),
+  ARM_RELEASE_ID_R7_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 2 ),
+  ARM_RELEASE_ID_R7_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 3 ),
+  ARM_RELEASE_ID_R7_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 4 ),
+  ARM_RELEASE_ID_R7_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 5 ),
+  ARM_RELEASE_ID_R7_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 6 ),
+  ARM_RELEASE_ID_R7_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 7 ),
+  ARM_RELEASE_ID_R7_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 8 ),
+  ARM_RELEASE_ID_R7_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 9 ),
+  ARM_RELEASE_ID_R7_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 10 ),
+  ARM_RELEASE_ID_R8_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 0 ),
+  ARM_RELEASE_ID_R8_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 1 ),
+  ARM_RELEASE_ID_R8_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 2 ),
+  ARM_RELEASE_ID_R8_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 3 ),
+  ARM_RELEASE_ID_R8_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 4 ),
+  ARM_RELEASE_ID_R8_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 5 ),
+  ARM_RELEASE_ID_R8_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 6 ),
+  ARM_RELEASE_ID_R8_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 7 ),
+  ARM_RELEASE_ID_R8_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 8 ),
+  ARM_RELEASE_ID_R8_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 9 ),
+  ARM_RELEASE_ID_R8_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 10 ),
+  ARM_RELEASE_ID_R9_P0  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 0 ),
+  ARM_RELEASE_ID_R9_P1  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 1 ),
+  ARM_RELEASE_ID_R9_P2  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 2 ),
+  ARM_RELEASE_ID_R9_P3  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 3 ),
+  ARM_RELEASE_ID_R9_P4  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 4 ),
+  ARM_RELEASE_ID_R9_P5  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 5 ),
+  ARM_RELEASE_ID_R9_P6  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 6 ),
+  ARM_RELEASE_ID_R9_P7  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 7 ),
+  ARM_RELEASE_ID_R9_P8  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 8 ),
+  ARM_RELEASE_ID_R9_P9  = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 9 ),
+  ARM_RELEASE_ID_R9_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 10 )
+} arm_release_id;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ARM_RELEASE_ID_H_ */
Index: bsps/arm/include/bsp/armv7m-irq.h
===================================================================
--- bsps/arm/include/bsp/armv7m-irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/armv7m-irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,36 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_shared
+ *
+ *  @brief ARMV7M Support
+ */
+
+/*
+ * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARMV7M_IRQ_H
+#define LIBBSP_ARM_SHARED_ARMV7M_IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _ARMV7M_NVIC_Interrupt_dispatch(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_ARMV7M_IRQ_H */
Index: bsps/arm/include/bsp/linker-symbols.h
===================================================================
--- bsps/arm/include/bsp/linker-symbols.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/linker-symbols.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,167 @@
+/**
+ * @file
+ *
+ * @ingroup arm_linker
+ *
+ * @brief Symbols defined in linker command base file.
+ */
+
+/*
+ * Copyright (c) 2008, 2016 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H
+#define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup arm_linker Linker Support
+ *
+ * @ingroup arm_shared
+ *
+ * @brief Linker support.
+ *
+ * @{
+ */
+
+#ifndef ASM
+  #define LINKER_SYMBOL(sym) extern char sym [];
+#else
+  #define LINKER_SYMBOL(sym) .extern sym
+#endif
+
+LINKER_SYMBOL(bsp_stack_irq_begin)
+LINKER_SYMBOL(bsp_stack_irq_end)
+LINKER_SYMBOL(bsp_stack_irq_size)
+
+LINKER_SYMBOL(bsp_stack_fiq_begin)
+LINKER_SYMBOL(bsp_stack_fiq_end)
+LINKER_SYMBOL(bsp_stack_irq_size)
+
+LINKER_SYMBOL(bsp_stack_abt_begin)
+LINKER_SYMBOL(bsp_stack_abt_end)
+LINKER_SYMBOL(bsp_stack_abt_size)
+
+LINKER_SYMBOL(bsp_stack_und_begin)
+LINKER_SYMBOL(bsp_stack_und_end)
+LINKER_SYMBOL(bsp_stack_und_size)
+
+LINKER_SYMBOL(bsp_stack_hyp_begin)
+LINKER_SYMBOL(bsp_stack_hyp_end)
+LINKER_SYMBOL(bsp_stack_hyp_size)
+
+LINKER_SYMBOL(bsp_stack_svc_begin)
+LINKER_SYMBOL(bsp_stack_svc_end)
+LINKER_SYMBOL(bsp_stack_svc_size)
+
+LINKER_SYMBOL(bsp_section_start_begin)
+LINKER_SYMBOL(bsp_section_start_end)
+LINKER_SYMBOL(bsp_section_start_size)
+
+LINKER_SYMBOL(bsp_section_vector_begin)
+LINKER_SYMBOL(bsp_section_vector_end)
+LINKER_SYMBOL(bsp_section_vector_size)
+
+LINKER_SYMBOL(bsp_section_text_begin)
+LINKER_SYMBOL(bsp_section_text_end)
+LINKER_SYMBOL(bsp_section_text_size)
+LINKER_SYMBOL(bsp_section_text_load_begin)
+LINKER_SYMBOL(bsp_section_text_load_end)
+
+LINKER_SYMBOL(bsp_section_rodata_begin)
+LINKER_SYMBOL(bsp_section_rodata_end)
+LINKER_SYMBOL(bsp_section_rodata_size)
+LINKER_SYMBOL(bsp_section_rodata_load_begin)
+LINKER_SYMBOL(bsp_section_rodata_load_end)
+
+LINKER_SYMBOL(bsp_section_data_begin)
+LINKER_SYMBOL(bsp_section_data_end)
+LINKER_SYMBOL(bsp_section_data_size)
+LINKER_SYMBOL(bsp_section_data_load_begin)
+LINKER_SYMBOL(bsp_section_data_load_end)
+
+LINKER_SYMBOL(bsp_section_fast_text_begin)
+LINKER_SYMBOL(bsp_section_fast_text_end)
+LINKER_SYMBOL(bsp_section_fast_text_size)
+LINKER_SYMBOL(bsp_section_fast_text_load_begin)
+LINKER_SYMBOL(bsp_section_fast_text_load_end)
+
+LINKER_SYMBOL(bsp_section_fast_data_begin)
+LINKER_SYMBOL(bsp_section_fast_data_end)
+LINKER_SYMBOL(bsp_section_fast_data_size)
+LINKER_SYMBOL(bsp_section_fast_data_load_begin)
+LINKER_SYMBOL(bsp_section_fast_data_load_end)
+
+LINKER_SYMBOL(bsp_section_bss_begin)
+LINKER_SYMBOL(bsp_section_bss_end)
+LINKER_SYMBOL(bsp_section_bss_size)
+
+LINKER_SYMBOL(bsp_section_work_begin)
+LINKER_SYMBOL(bsp_section_work_end)
+LINKER_SYMBOL(bsp_section_work_size)
+
+LINKER_SYMBOL(bsp_section_stack_begin)
+LINKER_SYMBOL(bsp_section_stack_end)
+LINKER_SYMBOL(bsp_section_stack_size)
+
+LINKER_SYMBOL(bsp_section_nocache_begin)
+LINKER_SYMBOL(bsp_section_nocache_end)
+LINKER_SYMBOL(bsp_section_nocache_size)
+LINKER_SYMBOL(bsp_section_nocache_load_begin)
+LINKER_SYMBOL(bsp_section_nocache_load_end)
+
+LINKER_SYMBOL(bsp_section_nocachenoload_begin)
+LINKER_SYMBOL(bsp_section_nocachenoload_end)
+LINKER_SYMBOL(bsp_section_nocachenoload_size)
+
+LINKER_SYMBOL(bsp_section_nocacheheap_begin)
+LINKER_SYMBOL(bsp_section_nocacheheap_end)
+LINKER_SYMBOL(bsp_section_nocacheheap_size)
+
+LINKER_SYMBOL(bsp_vector_table_begin)
+LINKER_SYMBOL(bsp_vector_table_end)
+LINKER_SYMBOL(bsp_vector_table_size)
+
+LINKER_SYMBOL(bsp_start_vector_table_begin)
+LINKER_SYMBOL(bsp_start_vector_table_end)
+LINKER_SYMBOL(bsp_start_vector_table_size)
+
+LINKER_SYMBOL(bsp_translation_table_base)
+LINKER_SYMBOL(bsp_translation_table_end)
+
+#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text")))
+
+#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data")))
+
+#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache")))
+
+#define BSP_NOCACHE_SUBSECTION(subsection) \
+  __attribute__((section(".bsp_nocache." # subsection)))
+
+#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache")))
+
+#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \
+  __attribute__((section(".bsp_noload_nocache." # subsection)))
+
+LINKER_SYMBOL(bsp_processor_count)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */
Index: bsps/arm/include/bsp/lpc-dma.h
===================================================================
--- bsps/arm/include/bsp/lpc-dma.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/lpc-dma.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,221 @@
+/**
+ * @file
+ *
+ * @ingroup lpc_dma
+ *
+ * @brief DMA support API.
+ */
+
+/*
+ * Copyright (c) 2010-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H
+#define LIBBSP_ARM_SHARED_LPC_DMA_H
+
+#include <bspopts.h>
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lpc_dma DMA Support
+ *
+ * @ingroup arm_lpc24xx
+ * @ingroup arm_lpc32xx
+ *
+ * @brief DMA support.
+ *
+ * @{
+ */
+
+/**
+ * @brief DMA descriptor item.
+ */
+typedef struct {
+  uint32_t src;
+  uint32_t dest;
+  uint32_t lli;
+  uint32_t ctrl;
+} lpc_dma_descriptor;
+
+/**
+ * @brief DMA channel block.
+ */
+typedef struct {
+  lpc_dma_descriptor desc;
+  uint32_t cfg;
+  uint32_t reserved [3];
+} lpc_dma_channel;
+
+/**
+ * @brief DMA control block.
+ */
+typedef struct {
+  uint32_t int_stat;
+  uint32_t int_tc_stat;
+  uint32_t int_tc_clear;
+  uint32_t int_err_stat;
+  uint32_t int_err_clear;
+  uint32_t raw_tc_stat;
+  uint32_t raw_err_stat;
+  uint32_t enabled_channels;
+  uint32_t soft_burst_req;
+  uint32_t soft_single_req;
+  uint32_t soft_last_burst_req;
+  uint32_t soft_last_single_req;
+  uint32_t cfg;
+  uint32_t sync;
+  uint32_t reserved [50];
+  lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT];
+} lpc_dma;
+
+/**
+ * @name DMA Configuration Register
+ *
+ * @{
+ */
+
+#define DMA_CFG_E BSP_BIT32(0)
+#define DMA_CFG_M_0 BSP_BIT32(1)
+#define DMA_CFG_M_1 BSP_BIT32(2)
+
+/** @} */
+
+/**
+ * @name DMA Channel Control Register
+ *
+ * @{
+ */
+
+#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11)
+#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff)
+
+#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14)
+#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0)
+#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1)
+#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2)
+#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3)
+#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4)
+#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5)
+#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6)
+#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7)
+
+#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17)
+#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0)
+#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1)
+#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2)
+#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3)
+#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4)
+#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5)
+#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6)
+#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7)
+
+#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20)
+#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0)
+#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1)
+#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2)
+
+#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23)
+#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0)
+#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1)
+#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2)
+
+#define DMA_CH_CTRL_S BSP_BIT32(24)
+#define DMA_CH_CTRL_D BSP_BIT32(25)
+#define DMA_CH_CTRL_SI BSP_BIT32(26)
+#define DMA_CH_CTRL_DI BSP_BIT32(27)
+#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30)
+#define DMA_CH_CTRL_I BSP_BIT32(31)
+
+/** @} */
+
+/**
+ * @name DMA Channel Configuration Register
+ *
+ * @{
+ */
+
+#define DMA_CH_CFG_E BSP_BIT32(0)
+#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5)
+#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10)
+
+#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13)
+#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0)
+#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1)
+#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2)
+#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3)
+#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4)
+#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5)
+#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6)
+#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7)
+
+#define DMA_CH_CFG_IE BSP_BIT32(14)
+#define DMA_CH_CFG_ITC BSP_BIT32(15)
+#define DMA_CH_CFG_L BSP_BIT32(16)
+#define DMA_CH_CFG_A BSP_BIT32(17)
+#define DMA_CH_CFG_H BSP_BIT32(18)
+
+/** @} */
+
+/**
+ * @name LPC24XX DMA Peripherals
+ *
+ * @{
+ */
+
+#define LPC24XX_DMA_PER_SSP_0_TX 0
+#define LPC24XX_DMA_PER_SSP_0_RX 1
+#define LPC24XX_DMA_PER_SSP_1_TX 2
+#define LPC24XX_DMA_PER_SSP_1_RX 3
+#define LPC24XX_DMA_PER_SD_MMC 4
+#define LPC24XX_DMA_PER_I2S_CH_0 5
+#define LPC24XX_DMA_PER_I2S_CH_1 6
+
+/** @} */
+
+/**
+ * @name LPC32XX DMA Peripherals
+ *
+ * @{
+ */
+
+#define LPC32XX_DMA_PER_I2S_0_CH_0 0
+#define LPC32XX_DMA_PER_I2S_0_CH_1 13
+#define LPC32XX_DMA_PER_I2S_1_CH_0 2
+#define LPC32XX_DMA_PER_I2S_1_CH_1 10
+#define LPC32XX_DMA_PER_NAND_0 1
+#define LPC32XX_DMA_PER_NAND_1 12
+#define LPC32XX_DMA_PER_SD_MMC 4
+#define LPC32XX_DMA_PER_SSP_0_RX 14
+#define LPC32XX_DMA_PER_SSP_0_TX 15
+#define LPC32XX_DMA_PER_SSP_1_RX 3
+#define LPC32XX_DMA_PER_SSP_1_TX 11
+#define LPC32XX_DMA_PER_UART_1_RX 6
+#define LPC32XX_DMA_PER_UART_1_TX 5
+#define LPC32XX_DMA_PER_UART_2_RX 8
+#define LPC32XX_DMA_PER_UART_2_TX 7
+#define LPC32XX_DMA_PER_UART_7_RX 10
+#define LPC32XX_DMA_PER_UART_7_TX 9
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */
Index: bsps/arm/include/bsp/lpc-emc.h
===================================================================
--- bsps/arm/include/bsp/lpc-emc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/lpc-emc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,170 @@
+/**
+ * @file
+ *
+ * @ingroup lpc_emc
+ *
+ * @brief EMC support API.
+ */
+
+/*
+ * Copyright (c) 2010-2011 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H
+#define LIBBSP_ARM_SHARED_LPC_EMC_H
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup lpc_emc EMC Support
+ *
+ * @ingroup arm_lpc24xx
+ * @ingroup arm_lpc32xx
+ *
+ * @brief EMC Support
+ *
+ * @{
+ */
+
+/**
+ * @name EMC Control Register (EMCControl)
+ *
+ * @{
+ */
+
+#define EMC_CTRL_E BSP_BIT32(0)
+#define EMC_CTRL_M BSP_BIT32(0)
+#define EMC_CTRL_L BSP_BIT32(2)
+
+/** @} */
+
+/**
+ * @name EMC Dynamic Memory Control Register (EMCDynamicControl)
+ *
+ * @{
+ */
+
+#define EMC_DYN_CTRL_CE BSP_BIT32(0)
+#define EMC_DYN_CTRL_CS BSP_BIT32(1)
+#define EMC_DYN_CTRL_SR BSP_BIT32(2)
+#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
+#define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
+#define EMC_DYN_CTRL_MCC BSP_BIT32(5)
+#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
+#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
+#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
+#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
+#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
+#define EMC_DYN_CTRL_DP BSP_BIT32(13)
+
+/** @} */
+
+/**
+ * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
+ *
+ * @{
+ */
+
+#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
+#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
+#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
+#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
+
+/** @} */
+
+/**
+ * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN)
+ *
+ * @{
+ */
+
+#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4)
+#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2)
+#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
+#define EMC_DYN_CFG_B BSP_BIT32(19)
+#define EMC_DYN_CFG_P BSP_BIT32(20)
+
+/** @} */
+
+/**
+ * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN)
+ *
+ * @{
+ */
+
+#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3)
+#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10)
+
+/** @} */
+
+#define EMC_DYN_CHIP_COUNT 4
+
+#define EMC_STATIC_CHIP_COUNT 4
+
+typedef struct {
+  uint32_t config;
+  uint32_t rascas;
+  uint32_t reserved_0 [6];
+} lpc_emc_dynamic;
+
+typedef struct {
+  uint32_t config;
+  uint32_t waitwen;
+  uint32_t waitoen;
+  uint32_t waitrd;
+  uint32_t waitpage;
+  uint32_t waitwr;
+  uint32_t waitturn;
+  uint32_t reserved_0 [1];
+} lpc_emc_static;
+
+typedef struct {
+  uint32_t control;
+  uint32_t status;
+  uint32_t config;
+  uint32_t reserved_0 [5];
+  uint32_t dynamiccontrol;
+  uint32_t dynamicrefresh;
+  uint32_t dynamicreadconfig;
+  uint32_t reserved_1;
+  uint32_t dynamictrp;
+  uint32_t dynamictras;
+  uint32_t dynamictsrex;
+  uint32_t dynamictapr;
+  uint32_t dynamictdal;
+  uint32_t dynamictwr;
+  uint32_t dynamictrc;
+  uint32_t dynamictrfc;
+  uint32_t dynamictxsr;
+  uint32_t dynamictrrd;
+  uint32_t dynamictmrd;
+  uint32_t dynamictcdlr;
+  uint32_t reserved_3 [8];
+  uint32_t staticextendedwait;
+  uint32_t reserved_4 [31];
+  lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
+  uint32_t reserved_5 [32];
+  lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
+} lpc_emc;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */
Index: bsps/arm/include/bsp/lpc-i2s.h
===================================================================
--- bsps/arm/include/bsp/lpc-i2s.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/lpc-i2s.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,132 @@
+/**
+ * @file
+ *
+ * @ingroup lpc_i2s
+ *
+ * @brief I2S API.
+ */
+
+/*
+ * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H
+#define LIBBSP_ARM_SHARED_LPC_I2S_H
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lpc_i2s I2S Support
+ *
+ * @ingroup arm_lpc24xx
+ * @ingroup arm_lpc32xx
+ *
+ * @brief I2S support.
+ *
+ * @{
+ */
+
+/**
+ * @brief I2S control block.
+ */
+typedef struct {
+  uint32_t dao;
+  uint32_t dai;
+  uint32_t txfifo;
+  uint32_t rxfifo;
+  uint32_t state;
+  uint32_t dma [2];
+  uint32_t irq;
+  uint32_t txrate;
+  uint32_t rxrate;
+} lpc_i2s;
+
+/**
+ * @name I2S Digital Audio Input and Output
+ *
+ * @{
+ */
+
+#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1)
+#define I2S_DAIO_MONO BSP_BIT32(2)
+#define I2S_DAIO_STOP BSP_BIT32(3)
+#define I2S_DAIO_RESET BSP_BIT32(4)
+#define I2S_DAIO_WS_SEL BSP_BIT32(5)
+#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14)
+#define I2S_DAIO_MUTE BSP_BIT32(15)
+
+/** @} */
+
+/**
+ * @name I2S Status Feedback
+ *
+ * @{
+ */
+
+#define I2S_STATE_IRQ BSP_BIT32(0)
+#define I2S_STATE_DMAREQ_0 BSP_BIT32(1)
+#define I2S_STATE_DMAREQ_1 BSP_BIT32(2)
+#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11)
+#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19)
+
+/** @} */
+
+/**
+ * @name I2S DMA Configuration
+ *
+ * @{
+ */
+
+#define I2S_DMA_RX_ENABLE BSP_BIT32(0)
+#define I2S_DMA_TX_ENABLE BSP_BIT32(1)
+#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
+#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
+
+/** @} */
+
+/**
+ * @name I2S Interrupt Request Control
+ *
+ * @{
+ */
+
+#define I2S_IRQ_RX BSP_BIT32(0)
+#define I2S_IRQ_TX BSP_BIT32(1)
+#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
+#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
+
+/** @} */
+
+/**
+ * @name I2S Transmit and Receive Clock Rate
+ *
+ * @{
+ */
+
+#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9)
+#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7)
+#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15)
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */
Index: bsps/arm/include/bsp/lpc-lcd.h
===================================================================
--- bsps/arm/include/bsp/lpc-lcd.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/lpc-lcd.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,213 @@
+/**
+ * @file
+ *
+ * @ingroup lpc_lcd
+ *
+ * @brief LCD support API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H
+#define LIBBSP_ARM_SHARED_LPC_LCD_H
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lpc_lcd LCD Support
+ *
+ * @ingroup lpc
+ * @ingroup arm_lpc32xx
+ *
+ * @brief LCD support.
+ *
+ * @{
+ */
+
+typedef struct {
+  uint8_t img [1024];
+  uint32_t ctrl;
+  uint32_t cfg;
+  uint32_t pal0;
+  uint32_t pal1;
+  uint32_t xy;
+  uint32_t clip;
+  uint32_t intmsk;
+  uint32_t intclr;
+  uint32_t intraw;
+  uint32_t intstat;
+} lpc_cursor;
+
+typedef struct {
+  uint32_t timh;
+  uint32_t timv;
+  uint32_t pol;
+  uint32_t le;
+  uint32_t upbase;
+  uint32_t lpbase;
+  uint32_t ctrl;
+  uint32_t intmsk;
+  uint32_t intraw;
+  uint32_t intstat;
+  uint32_t intclr;
+  uint32_t upcurr;
+  uint32_t lpcurr;
+  uint8_t reserved_0 [0x200 - 0x034];
+  uint16_t pal [256];
+  uint8_t reserved_1 [0x800 - 0x400];
+  lpc_cursor crsr;
+} lpc_lcd;
+
+/**
+ * @name LCD Configuration Register
+ *
+ * @{
+ */
+
+#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4)
+#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5)
+#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7)
+#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8)
+
+/** @} */
+
+/**
+ * @name LCD Horizontal Timing Register
+ *
+ * @{
+ */
+
+#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7)
+#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
+#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15)
+#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23)
+#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31)
+#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
+
+/** @} */
+
+/**
+ * @name LCD Vertical Timing Register
+ *
+ * @{
+ */
+
+#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9)
+#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15)
+#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
+#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23)
+#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31)
+#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
+
+/** @} */
+
+/**
+ * @name LCD Clock and Signal Polarity Register
+ *
+ * @{
+ */
+
+#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4)
+#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LCD_POL_CLKSEL BSP_BIT32(5)
+#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10)
+#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
+#define LCD_POL_IVS BSP_BIT32(11)
+#define LCD_POL_IHS BSP_BIT32(12)
+#define LCD_POL_IPC BSP_BIT32(13)
+#define LCD_POL_IOE BSP_BIT32(14)
+#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25)
+#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
+#define LCD_POL_BCD BSP_BIT32(26)
+#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31)
+#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
+
+/** @} */
+
+/**
+ * @name LCD Line End Control Register
+ *
+ * @{
+ */
+
+#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6)
+#define LCD_LE_LEE BSP_BIT32(16)
+
+/** @} */
+
+/**
+ * @name LCD Control Register
+ *
+ * @{
+ */
+
+#define LCD_CTRL_LCDEN BSP_BIT32(0)
+#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3)
+#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
+#define LCD_CTRL_LCDBW BSP_BIT32(4)
+#define LCD_CTRL_LCDTFT BSP_BIT32(5)
+#define LCD_CTRL_LCDMONO8 BSP_BIT32(6)
+#define LCD_CTRL_LCDDUAL BSP_BIT32(7)
+#define LCD_CTRL_BGR BSP_BIT32(8)
+#define LCD_CTRL_BEBO BSP_BIT32(9)
+#define LCD_CTRL_BEPO BSP_BIT32(10)
+#define LCD_CTRL_LCDPWR BSP_BIT32(11)
+#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13)
+#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
+#define LCD_CTRL_WATERMARK BSP_BIT32(16)
+
+/** @} */
+
+/**
+ * @name LCD Interrupt Registers
+ *
+ * @{
+ */
+
+#define LCD_INT_FUF BSP_BIT32(1)
+#define LCD_INT_LNBU BSP_BIT32(2)
+#define LCD_INT_VCOMP BSP_BIT32(3)
+#define LCD_INT_BER BSP_BIT32(4)
+
+/** @} */
+
+/**
+ * @name LCD Color Palette Register
+ *
+ * @{
+ */
+
+#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
+#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
+#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
+#define LCD_PAL_I BSP_BIT16(15)
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */
Index: bsps/arm/include/bsp/lpc-timer.h
===================================================================
--- bsps/arm/include/bsp/lpc-timer.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/lpc-timer.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * @ingroup lpc_timer
+ *
+ * @brief Timer API.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
+#define LIBBSP_ARM_SHARED_LPC_TIMER_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lpc_timer Timer Support
+ *
+ * @ingroup arm_lpc24xx
+ * @ingroup arm_lpc32xx
+ *
+ * @brief Timer support.
+ *
+ * @{
+ */
+
+/**
+ * @name Interrupt Register Defines
+ *
+ * @{
+ */
+
+#define LPC_TIMER_IR_MR0 0x1U
+#define LPC_TIMER_IR_MR1 0x2U
+#define LPC_TIMER_IR_MR2 0x4U
+#define LPC_TIMER_IR_MR3 0x8U
+#define LPC_TIMER_IR_CR0 0x10U
+#define LPC_TIMER_IR_CR1 0x20U
+#define LPC_TIMER_IR_CR2 0x40U
+#define LPC_TIMER_IR_CR3 0x80U
+#define LPC_TIMER_IR_ALL 0xffU
+
+/** @} */
+
+/**
+ * @name Timer Control Register Defines
+ *
+ * @{
+ */
+
+#define LPC_TIMER_TCR_EN 0x1U
+#define LPC_TIMER_TCR_RST 0x2U
+
+/** @} */
+
+/**
+ * @name Match Control Register Defines
+ *
+ * @{
+ */
+
+#define LPC_TIMER_MCR_MR0_INTR 0x1U
+#define LPC_TIMER_MCR_MR0_RST 0x2U
+#define LPC_TIMER_MCR_MR0_STOP 0x4U
+#define LPC_TIMER_MCR_MR1_INTR 0x8U
+#define LPC_TIMER_MCR_MR1_RST 0x10U
+#define LPC_TIMER_MCR_MR1_STOP 0x20U
+#define LPC_TIMER_MCR_MR2_INTR 0x40U
+#define LPC_TIMER_MCR_MR2_RST 0x80U
+#define LPC_TIMER_MCR_MR2_STOP 0x100U
+#define LPC_TIMER_MCR_MR3_INTR 0x200U
+#define LPC_TIMER_MCR_MR3_RST 0x400U
+#define LPC_TIMER_MCR_MR3_STOP 0x800U
+
+/** @} */
+
+/**
+ * @name Capture Control Register Defines
+ *
+ * @{
+ */
+
+#define LPC_TIMER_CCR_CAP0_RE 0x1U
+#define LPC_TIMER_CCR_CAP0_FE 0x2U
+#define LPC_TIMER_CCR_CAP0_INTR 0x4U
+#define LPC_TIMER_CCR_CAP1_RE 0x8U
+#define LPC_TIMER_CCR_CAP1_FE 0x10U
+#define LPC_TIMER_CCR_CAP1_INTR 0x20U
+#define LPC_TIMER_CCR_CAP2_RE 0x40U
+#define LPC_TIMER_CCR_CAP2_FE 0x80U
+#define LPC_TIMER_CCR_CAP2_INTR 0x100U
+#define LPC_TIMER_CCR_CAP3_RE 0x200U
+#define LPC_TIMER_CCR_CAP3_FE 0x400U
+#define LPC_TIMER_CCR_CAP3_INTR 0x800U
+
+/** @} */
+
+/**
+ * @name External Match Register Defines
+ *
+ * @{
+ */
+
+#define LPC_TIMER_EMR_EM0_RE 0x1U
+#define LPC_TIMER_EMR_EM1_FE 0x2U
+#define LPC_TIMER_EMR_EM2_INTR 0x4U
+#define LPC_TIMER_EMR_EM3_RE 0x8U
+#define LPC_TIMER_EMR_EMC0_FE 0x10U
+#define LPC_TIMER_EMR_EMC1_INTR 0x20U
+#define LPC_TIMER_EMR_EMC2_RE 0x40U
+#define LPC_TIMER_EMR_EMC3_FE 0x80U
+
+/** @} */
+
+/**
+ * @brief Timer control block.
+ */
+typedef struct {
+  uint32_t ir;
+  uint32_t tcr;
+  uint32_t tc;
+  uint32_t pr;
+  uint32_t pc;
+  uint32_t mcr;
+  uint32_t mr0;
+  uint32_t mr1;
+  uint32_t mr2;
+  uint32_t mr3;
+  uint32_t ccr;
+  uint32_t cr0;
+  uint32_t cr1;
+  uint32_t cr2;
+  uint32_t cr3;
+  uint32_t emr;
+  uint32_t ctcr;
+} lpc_timer;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */
Index: bsps/arm/include/bsp/start.h
===================================================================
--- bsps/arm/include/bsp/start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/bsp/start.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,183 @@
+/**
+ * @file
+ *
+ * @ingroup arm_start
+ *
+ * @brief ARM system low level start.
+ */
+
+/*
+ * Copyright (c) 2008-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_START_H
+#define LIBBSP_ARM_SHARED_START_H
+
+#include <string.h>
+
+#include <bsp/linker-symbols.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup arm_start System Start
+ *
+ * @ingroup arm_shared
+ *
+ * @brief ARM system low level start.
+ *
+ * @{
+ */
+
+#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text")))
+
+#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
+
+/*
+* Many ARM boot loaders pass arguments to loaded OS kernel
+*/
+#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS
+#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int saved_dtb_adr
+#else
+#define BSP_START_HOOKS_LOADER_ARGS void
+#endif
+
+/**
+* @brief System start entry.
+*/
+void _start(void);
+
+/**
+* @brief Start entry hook 0.
+*
+* This hook will be called from the start entry code after all modes and
+* stack pointers are initialized but before the copying of the exception
+* vectors.
+*/
+void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS);
+
+/**
+* @brief Start entry hook 1.
+*
+* This hook will be called from the start entry code after copying of the
+* exception vectors but before the call to boot_card().
+*/
+void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS);
+
+/**
+ * @brief Similar to standard memcpy().
+ *
+ * The memory areas must be word aligned.  Copy code will be executed from the
+ * stack.  If @a dest equals @a src nothing will be copied.
+ */
+void bsp_start_memcpy(int *dest, const int *src, size_t n);
+
+/**
+ * @brief ARM entry point to bsp_start_memcpy().
+ */
+void bsp_start_memcpy_arm(int *dest, const int *src, size_t n);
+
+/**
+ * @brief Copies all standard sections from the load to the runtime area.
+ */
+BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections(void)
+{
+  /* Copy .text section */
+  bsp_start_memcpy(
+    (int *) bsp_section_text_begin,
+    (const int *) bsp_section_text_load_begin,
+    (size_t) bsp_section_text_size
+  );
+
+  /* Copy .rodata section */
+  bsp_start_memcpy(
+    (int *) bsp_section_rodata_begin,
+    (const int *) bsp_section_rodata_load_begin,
+    (size_t) bsp_section_rodata_size
+  );
+
+  /* Copy .data section */
+  bsp_start_memcpy(
+    (int *) bsp_section_data_begin,
+    (const int *) bsp_section_data_load_begin,
+    (size_t) bsp_section_data_size
+  );
+
+  /* Copy .fast_text section */
+  bsp_start_memcpy(
+    (int *) bsp_section_fast_text_begin,
+    (const int *) bsp_section_fast_text_load_begin,
+    (size_t) bsp_section_fast_text_size
+  );
+
+  /* Copy .fast_data section */
+  bsp_start_memcpy(
+    (int *) bsp_section_fast_data_begin,
+    (const int *) bsp_section_fast_data_load_begin,
+    (size_t) bsp_section_fast_data_size
+  );
+}
+
+BSP_START_TEXT_SECTION static inline void
+bsp_start_memcpy_libc(void *dest, const void *src, size_t n)
+{
+  if (dest != src) {
+    memcpy(dest, src, n);
+  }
+}
+
+/**
+ * @brief Copies the .data, .fast_text and .fast_data sections from the load to
+ * the runtime area using the C library memcpy().
+ *
+ * Works only in case the .start, .text and .rodata sections reside in one
+ * memory region.
+ */
+BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections_compact(void)
+{
+  /* Copy .data section */
+  bsp_start_memcpy_libc(
+    bsp_section_data_begin,
+    bsp_section_data_load_begin,
+    (size_t) bsp_section_data_size
+  );
+
+  /* Copy .fast_text section */
+  bsp_start_memcpy_libc(
+    bsp_section_fast_text_begin,
+    bsp_section_fast_text_load_begin,
+    (size_t) bsp_section_fast_text_size
+  );
+
+  /* Copy .fast_data section */
+  bsp_start_memcpy_libc(
+    bsp_section_fast_data_begin,
+    bsp_section_fast_data_load_begin,
+    (size_t) bsp_section_fast_data_size
+  );
+}
+
+BSP_START_TEXT_SECTION static inline void bsp_start_clear_bss(void)
+{
+  memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_START_H */
Index: bsps/arm/include/cmsis_gcc.h
===================================================================
--- bsps/arm/include/cmsis_gcc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/cmsis_gcc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
Index: bsps/arm/include/core_cm7.h
===================================================================
--- bsps/arm/include/core_cm7.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/core_cm7.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,2512 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x07U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in NVIC and returns the active bit.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+  {
+    return 2UL;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+  {
+    return 1UL;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0UL;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += linesize;
+      op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += linesize;
+      op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += linesize;
+      op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
Index: bsps/arm/include/core_cmFunc.h
===================================================================
--- bsps/arm/include/core_cmFunc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/core_cmFunc.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
Index: bsps/arm/include/core_cmInstr.h
===================================================================
--- bsps/arm/include/core_cmInstr.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/core_cmInstr.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
Index: bsps/arm/include/core_cmSimd.h
===================================================================
--- bsps/arm/include/core_cmSimd.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/core_cmSimd.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
Index: bsps/arm/include/libcpu/am335x.h
===================================================================
--- bsps/arm/include/libcpu/am335x.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/libcpu/am335x.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,704 @@
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke@gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng@shrike-systems.com> to add lots
+ * of beagleboard/beaglebone definitions, delete lpc32xx specific
+ * ones, and merge with some other header files.
+ */
+
+#if !defined(_AM335X_H_)
+#define _AM335X_H_
+
+/* Interrupt controller memory map */
+#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller memory map */
+#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+#define AM335X_INT_EMUINT             0
+    /* Emulation interrupt (EMUICINTR) */
+#define AM335X_INT_COMMTX             1
+    /* CortexA8 COMMTX */
+#define AM335X_INT_COMMRX             2
+    /* CortexA8 COMMRX */
+#define AM335X_INT_BENCH              3
+    /* CortexA8 NPMUIRQ */
+#define AM335X_INT_ELM_IRQ            4
+    /* Sinterrupt (Error location process completion) */
+#define AM335X_INT_NMI                7
+    /* nmi_int */
+#define AM335X_INT_L3DEBUG            9
+    /* l3_FlagMux_top_FlagOut1 */
+#define AM335X_INT_L3APPINT           10
+    /* l3_FlagMux_top_FlagOut0  */
+#define AM335X_INT_PRCMINT            11
+    /* irq_mpu */
+#define AM335X_INT_EDMACOMPINT        12
+    /* tpcc_int_pend_po0 */
+#define AM335X_INT_EDMAMPERR          13
+    /* tpcc_mpint_pend_po */
+#define AM335X_INT_EDMAERRINT         14
+    /* tpcc_errint_pend_po */
+#define AM335X_INT_ADC_TSC_GENINT     16
+    /* gen_intr_pend */
+#define AM335X_INT_USBSSINT           17
+    /* usbss_intr_pend */
+#define AM335X_INT_USB0               18
+    /* usb0_intr_pend */
+#define AM335X_INT_USB1               19
+    /* usb1_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT0     20
+    /* pr1_host_intr0_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT1     21
+    /* pr1_host_intr1_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT2     22
+    /* pr1_host_intr2_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT3     23
+    /* pr1_host_intr3_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT4     24
+    /* pr1_host_intr4_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT5     25
+    /* pr1_host_intr5_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT6     26
+    /* pr1_host_intr6_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT7     27
+    /* pr1_host_intr7_intr_pend */
+#define AM335X_INT_MMCSD1INT          28
+    /* MMCSD1  SINTERRUPTN */
+#define AM335X_INT_MMCSD2INT          29
+    /* MMCSD2  SINTERRUPT */
+#define AM335X_INT_I2C2INT            30
+    /* I2C2  POINTRPEND */
+#define AM335X_INT_eCAP0INT           31
+    /* ecap_intr_intr_pend */
+#define AM335X_INT_GPIOINT2A          32
+    /* GPIO 2  POINTRPEND1 */
+#define AM335X_INT_GPIOINT2B          33
+    /* GPIO 2  POINTRPEND2 */
+#define AM335X_INT_USBWAKEUP          34
+    /* USBSS  slv0p_Swakeup */
+#define AM335X_INT_LCDCINT            36
+    /* LCDC  lcd_irq */
+#define AM335X_INT_GFXINT             37
+    /* SGX530  THALIAIRQ */
+#define AM335X_INT_ePWM2INT           39
+    /* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_3PGSWRXTHR0        40
+    /* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
+#define AM335X_INT_3PGSWRXINT0        41
+    /* CPSW (Ethernet)  c0_rx_pend */
+#define AM335X_INT_3PGSWTXINT0        42
+    /* CPSW (Ethernet)  c0_tx_pend */
+#define AM335X_INT_3PGSWMISC0         43
+    /* CPSW (Ethernet)  c0_misc_pend */
+#define AM335X_INT_UART3INT           44
+    /* UART3  niq */
+#define AM335X_INT_UART4INT           45
+    /* UART4  niq */
+#define AM335X_INT_UART5INT           46
+    /* UART5  niq */
+#define AM335X_INT_eCAP1INT           47
+    /* (PWM Subsystem)  ecap_intr_intr_pend */
+#define AM335X_INT_DCAN0_INT0         52
+    /* DCAN0  dcan_intr0_intr_pend */
+#define AM335X_INT_DCAN0_INT1         53
+    /* DCAN0  dcan_intr1_intr_pend */
+#define AM335X_INT_DCAN0_PARITY       54
+    /* DCAN0  dcan_uerr_intr_pend */
+#define AM335X_INT_DCAN1_INT0         55
+    /* DCAN1  dcan_intr0_intr_pend */
+#define AM335X_INT_DCAN1_INT1         56
+    /* DCAN1  dcan_intr1_intr_pend */
+#define AM335X_INT_DCAN1_PARITY       57
+    /* DCAN1  dcan_uerr_intr_pend */
+#define AM335X_INT_ePWM0_TZINT        58
+    /* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_ePWM1_TZINT        59
+    /* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_ePWM2_TZINT        60
+    /* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_eCAP2INT           61
+    /* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
+#define AM335X_INT_GPIOINT3A          62
+    /* GPIO 3  POINTRPEND1 */
+#define AM335X_INT_GPIOINT3B          63
+    /* GPIO 3  POINTRPEND2 */
+#define AM335X_INT_MMCSD0INT          64
+    /* MMCSD0  SINTERRUPTN */
+#define AM335X_INT_SPI0INT            65
+    /* McSPI0  SINTERRUPTN */
+#define AM335X_INT_TINT0              66
+    /* Timer0  POINTR_PEND */
+#define AM335X_INT_TINT1_1MS          67
+    /* DMTIMER_1ms  POINTR_PEND */
+#define AM335X_INT_TINT2              68
+    /* DMTIMER2  POINTR_PEND */
+#define AM335X_INT_TINT3              69
+    /* DMTIMER3  POINTR_PEND */
+#define AM335X_INT_I2C0INT            70
+    /* I2C0  POINTRPEND */
+#define AM335X_INT_I2C1INT            71
+    /* I2C1  POINTRPEND */
+#define AM335X_INT_UART0INT           72
+    /* UART0  niq */
+#define AM335X_INT_UART1INT           73
+    /* UART1  niq */
+#define AM335X_INT_UART2INT           74
+    /* UART2  niq */
+#define AM335X_INT_RTCINT             75
+    /* RTC  timer_intr_pend */
+#define AM335X_INT_RTCALARMINT        76
+    /* RTC  alarm_intr_pend */
+#define AM335X_INT_MBINT0             77
+    /* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
+#define AM335X_INT_M3_TXEV            78
+    /* Wake M3 Subsystem  TXEV */
+#define AM335X_INT_eQEP0INT           79
+    /* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_MCATXINT0          80
+    /* McASP0  mcasp_x_intr_pend */
+#define AM335X_INT_MCARXINT0          81
+    /* McASP0  mcasp_r_intr_pend */
+#define AM335X_INT_MCATXINT1          82
+    /* McASP1  mcasp_x_intr_pend */
+#define AM335X_INT_MCARXINT1          83
+    /* McASP1  mcasp_r_intr_pend */
+#define AM335X_INT_ePWM0INT           86
+    /* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_ePWM1INT           87
+    /* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_eQEP1INT           88
+    /* (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_eQEP2INT           89
+    /* (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_DMA_INTR_PIN2      90
+    /* External DMA/Interrupt Pin2  */
+#define AM335X_INT_WDT1INT            91
+    /* (Public Watchdog) WDTIMER1 PO_INT_PEND */
+#define AM335X_INT_TINT4              92
+    /* DMTIMER4  POINTR_PEN */
+#define AM335X_INT_TINT5              93
+    /* DMTIMER5  POINTR_PEN */
+#define AM335X_INT_TINT6              94
+    /* DMTIMER6  POINTR_PEND */
+#define AM335X_INT_TINT7              95
+    /* DMTIMER7  POINTR_PEND */
+#define AM335X_INT_GPIOINT0A          96
+    /* GPIO 0  POINTRPEND1 */
+#define AM335X_INT_GPIOINT0B          97
+    /* GPIO 0  POINTRPEND2 */
+#define AM335X_INT_GPIOINT1A          98
+    /* GPIO 1  POINTRPEND1 */
+#define AM335X_INT_GPIOINT1B          99
+    /* GPIO 1  POINTRPEND2 */
+#define AM335X_INT_GPMCINT            100
+    /* GPMC  gpmc_sinterrupt */
+#define AM335X_INT_DDRERR0            101
+    /* EMIF  sys_err_intr_pend */
+#define AM335X_INT_TCERRINT0          112
+    /* TPTC0  tptc_erint_pend_po */
+#define AM335X_INT_TCERRINT1          113
+    /* TPTC1  tptc_erint_pend_po */
+#define AM335X_INT_TCERRINT2          114
+    /* TPTC2  tptc_erint_pend_po */
+#define AM335X_INT_ADC_TSC_PENINT     115
+    /* ADC_TSC  pen_intr_pend */
+#define AM335X_INT_SMRFLX_Sabertooth  120
+    /* Smart Reflex 0  intrpen */
+#define AM335X_INT_SMRFLX_Core        121
+    /* Smart Reflex 1  intrpend */
+#define AM335X_INT_DMA_INTR_PIN0      123
+    /* pi_x_dma_event_intr0 (xdma_event_intr0) */
+#define AM335X_INT_DMA_INTR_PIN1      124
+    /* pi_x_dma_event_intr1 (xdma_event_intr1) */
+#define AM335X_INT_SPI1INT            125
+    /* McSPI1  SINTERRUPTN */
+
+#define OMAP3_AM335X_NR_IRQ_VECTORS    125
+
+#define AM335X_DMTIMER0_BASE      0x44E05000
+    /* DMTimer0 Registers */
+#define AM335X_DMTIMER1_1MS_BASE  0x44E31000
+    /* DMTimer1 1ms Registers (Accurate 1ms timer) */
+#define AM335X_DMTIMER2_BASE      0x48040000
+    /*  DMTimer2 Registers */
+#define AM335X_DMTIMER3_BASE      0x48042000
+    /*  DMTimer3 Registers */
+#define AM335X_DMTIMER4_BASE      0x48044000
+    /* DMTimer4 Registers  */
+#define AM335X_DMTIMER5_BASE      0x48046000
+    /* DMTimer5 Registers  */
+#define AM335X_DMTIMER6_BASE      0x48048000
+    /*  DMTimer6 Registers */
+#define AM335X_DMTIMER7_BASE      0x4804A000
+    /*  DMTimer7 Registers */
+
+/* General-purpose timer registers
+   AM335x non 1MS timers have different offsets */
+#define AM335X_TIMER_TIDR             0x000
+    /* IP revision code */
+#define AM335X_TIMER_TIOCP_CFG        0x010
+    /* Controls params for GP timer L4 interface */
+#define AM335X_TIMER_IRQSTATUS_RAW    0x024
+    /* Timer IRQSTATUS Raw Register */
+#define AM335X_TIMER_IRQSTATUS        0x028
+    /* Timer IRQSTATUS Register */
+#define AM335X_TIMER_IRQENABLE_SET    0x02C
+    /* Timer IRQENABLE Set Register */
+#define AM335X_TIMER_IRQENABLE_CLR    0x030
+    /* Timer IRQENABLE Clear Register */
+#define AM335X_TIMER_IRQWAKEEN        0x034
+    /* Timer IRQ Wakeup Enable Register */
+#define AM335X_TIMER_TCLR             0x038
+    /* Controls optional features */
+#define AM335X_TIMER_TCRR             0x03C
+    /* Internal counter value */
+#define AM335X_TIMER_TLDR             0x040
+    /* Timer load value */
+#define AM335X_TIMER_TTGR             0x044
+    /* Triggers counter reload */
+#define AM335X_TIMER_TWPS             0x048
+    /* Indicates if Write-Posted pending */
+#define AM335X_TIMER_TMAR             0x04C
+    /* Value to be compared with counter */
+#define AM335X_TIMER_TCAR1            0x050
+    /* First captured value of counter register */
+#define AM335X_TIMER_TSICR            0x054
+    /* Control posted mode and functional SW reset */
+#define AM335X_TIMER_TCAR2            0x058
+    /* Second captured value of counter register */
+#define AM335X_WDT_BASE                0x44E35000
+    /* Watchdog timer */
+#define AM335X_WDT_WWPS                0x34
+    /* Command posted status */
+#define AM335X_WDT_WSPR                0x48
+    /* Activate/deactivate sequence */
+
+/* RTC registers */
+#define AM335X_RTC_BASE         0x44E3E000
+#define AM335X_RTC_SECS         0x0
+#define AM335X_RTC_MINS         0x4
+#define AM335X_RTC_HOURS        0x8
+#define AM335X_RTC_DAYS         0xc
+#define AM335X_RTC_MONTHS       0x10
+#define AM335X_RTC_YEARS        0x14
+#define AM335X_RTC_WEEKS        0x18
+#define AM335X_RTC_CTRL_REG     0x40
+#define AM335X_RTC_STATUS_REG   0x44
+#define AM335X_RTC_REV_REG      0x74
+#define AM335X_RTC_SYSCONFIG    0x78
+#define AM335X_RTC_KICK0        0x6c
+#define AM335X_RTC_KICK1        0x70
+#define AM335X_RTC_OSC_CLOCK    0x54
+
+#define AM335X_RTC_KICK0_KEY    0x83E70B13
+#define AM335X_RTC_KICK1_KEY    0x95A4F1E0
+
+/* GPIO memory-mapped registers */
+
+#define AM335X_GPIO0_BASE           0x44E07000
+    /* GPIO Bank 0 base Register */
+#define AM335X_GPIO1_BASE           0x4804C000
+    /* GPIO Bank 1 base Register */
+#define AM335X_GPIO2_BASE           0x481AC000
+    /* GPIO Bank 2 base Register */
+#define AM335X_GPIO3_BASE           0x481AE000
+    /* GPIO Bank 3 base Register */
+
+#define AM335X_GPIO_REVISION        0x00
+#define AM335X_GPIO_SYSCONFIG       0x10
+#define AM335X_GPIO_EOI             0x20
+#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24
+#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28
+#define AM335X_GPIO_IRQSTATUS_0     0x2C
+#define AM335X_GPIO_IRQSTATUS_1     0x30
+#define AM335X_GPIO_IRQSTATUS_SET_0 0x34
+#define AM335X_GPIO_IRQSTATUS_SET_1 0x38
+#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C
+#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40
+#define AM335X_GPIO_IRQWAKEN_0      0x44
+#define AM335X_GPIO_IRQWAKEN_1      0x48
+#define AM335X_GPIO_SYSSTATUS       0x114
+#define AM335X_GPIO_CTRL            0x130
+#define AM335X_GPIO_OE              0x134
+#define AM335X_GPIO_DATAIN          0x138
+#define AM335X_GPIO_DATAOUT         0x13C
+#define AM335X_GPIO_LEVELDETECT0    0x140
+#define AM335X_GPIO_LEVELDETECT1    0x144
+#define AM335X_GPIO_RISINGDETECT    0x148
+#define AM335X_GPIO_FALLINGDETECT   0x14C
+#define AM335X_GPIO_DEBOUNCENABLE   0x150
+#define AM335X_GPIO_DEBOUNCINGTIME  0x154
+#define AM335X_GPIO_CLEARDATAOUT    0x190
+#define AM335X_GPIO_SETDATAOUT      0x194
+
+/* AM335X Pad Configuration Register Base */
+#define AM335X_PADCONF_BASE 0x44E10000
+
+/* Memory mapped register offset for Control Module */
+#define AM335X_CONF_GPMC_AD0 0x800
+#define AM335X_CONF_GPMC_AD1 0x804
+#define AM335X_CONF_GPMC_AD2 0x808
+#define AM335X_CONF_GPMC_AD3 0x80C
+#define AM335X_CONF_GPMC_AD4 0x810
+#define AM335X_CONF_GPMC_AD5 0x814
+#define AM335X_CONF_GPMC_AD6 0x818
+#define AM335X_CONF_GPMC_AD7 0x81C
+#define AM335X_CONF_GPMC_AD8 0x820
+#define AM335X_CONF_GPMC_AD9 0x824
+#define AM335X_CONF_GPMC_AD10 0x828
+#define AM335X_CONF_GPMC_AD11 0x82C
+#define AM335X_CONF_GPMC_AD12 0x830
+#define AM335X_CONF_GPMC_AD13 0x834
+#define AM335X_CONF_GPMC_AD14 0x838
+#define AM335X_CONF_GPMC_AD15 0x83C
+#define AM335X_CONF_GPMC_A0 0x840
+#define AM335X_CONF_GPMC_A1 0x844
+#define AM335X_CONF_GPMC_A2 0x848
+#define AM335X_CONF_GPMC_A3 0x84C
+#define AM335X_CONF_GPMC_A4 0x850
+#define AM335X_CONF_GPMC_A5 0x854
+#define AM335X_CONF_GPMC_A6 0x858
+#define AM335X_CONF_GPMC_A7 0x85C
+#define AM335X_CONF_GPMC_A8 0x860
+#define AM335X_CONF_GPMC_A9 0x864
+#define AM335X_CONF_GPMC_A10 0x868
+#define AM335X_CONF_GPMC_A11 0x86C
+#define AM335X_CONF_GPMC_WAIT0 0x870
+#define AM335X_CONF_GPMC_WPN 0x874
+#define AM335X_CONF_GPMC_BEN1 0x878
+#define AM335X_CONF_GPMC_CSN0 0x87C
+#define AM335X_CONF_GPMC_CSN1 0x880
+#define AM335X_CONF_GPMC_CSN2 0x884
+#define AM335X_CONF_GPMC_CSN3 0x888
+#define AM335X_CONF_GPMC_CLK 0x88C
+#define AM335X_CONF_GPMC_ADVN_ALE 0x890
+#define AM335X_CONF_GPMC_OEN_REN 0x894
+#define AM335X_CONF_GPMC_WEN 0x898
+#define AM335X_CONF_GPMC_BEN0_CLE 0x89C
+#define AM335X_CONF_LCD_DATA0 0x8A0
+#define AM335X_CONF_LCD_DATA1 0x8A4
+#define AM335X_CONF_LCD_DATA2 0x8A8
+#define AM335X_CONF_LCD_DATA3 0x8AC
+#define AM335X_CONF_LCD_DATA4 0x8B0
+#define AM335X_CONF_LCD_DATA5 0x8B4
+#define AM335X_CONF_LCD_DATA6 0x8B8
+#define AM335X_CONF_LCD_DATA7 0x8BC
+#define AM335X_CONF_LCD_DATA8 0x8C0
+#define AM335X_CONF_LCD_DATA9 0x8C4
+#define AM335X_CONF_LCD_DATA10 0x8C8
+#define AM335X_CONF_LCD_DATA11 0x8CC
+#define AM335X_CONF_LCD_DATA12 0x8D0
+#define AM335X_CONF_LCD_DATA13 0x8D4
+#define AM335X_CONF_LCD_DATA14 0x8D8
+#define AM335X_CONF_LCD_DATA15 0x8DC
+#define AM335X_CONF_LCD_VSYNC 0x8E0
+#define AM335X_CONF_LCD_HSYNC 0x8E4
+#define AM335X_CONF_LCD_PCLK 0x8E8
+#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC
+#define AM335X_CONF_MMC0_DAT3 0x8F0
+#define AM335X_CONF_MMC0_DAT2 0x8F4
+#define AM335X_CONF_MMC0_DAT1 0x8F8
+#define AM335X_CONF_MMC0_DAT0 0x8FC
+#define AM335X_CONF_MMC0_CLK 0x900
+#define AM335X_CONF_MMC0_CMD 0x904
+#define AM335X_CONF_MII1_COL 0x908
+#define AM335X_CONF_MII1_CRS 0x90C
+#define AM335X_CONF_MII1_RX_ER 0x910
+#define AM335X_CONF_MII1_TX_EN 0x914
+#define AM335X_CONF_MII1_RX_DV 0x918
+#define AM335X_CONF_MII1_TXD3 0x91C
+#define AM335X_CONF_MII1_TXD2 0x920
+#define AM335X_CONF_MII1_TXD1 0x924
+#define AM335X_CONF_MII1_TXD0 0x928
+#define AM335X_CONF_MII1_TX_CLK 0x92C
+#define AM335X_CONF_MII1_RX_CLK 0x930
+#define AM335X_CONF_MII1_RXD3 0x934
+#define AM335X_CONF_MII1_RXD2 0x938
+#define AM335X_CONF_MII1_RXD1 0x93C
+#define AM335X_CONF_MII1_RXD0 0x940
+#define AM335X_CONF_RMII1_REF_CLK 0x944
+#define AM335X_CONF_MDIO 0x948
+#define AM335X_CONF_MDC 0x94C
+#define AM335X_CONF_SPI0_SCLK 0x950
+#define AM335X_CONF_SPI0_D0 0x954
+#define AM335X_CONF_SPI0_D1 0x958
+#define AM335X_CONF_SPI0_CS0 0x95C
+#define AM335X_CONF_SPI0_CS1 0x960
+#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964
+#define AM335X_CONF_UART0_CTSN 0x968
+#define AM335X_CONF_UART0_RTSN 0x96C
+#define AM335X_CONF_UART0_RXD 0x970
+#define AM335X_CONF_UART0_TXD 0x974
+#define AM335X_CONF_UART1_CTSN 0x978
+#define AM335X_CONF_UART1_RTSN 0x97C
+#define AM335X_CONF_UART1_RXD 0x980
+#define AM335X_CONF_UART1_TXD 0x984
+#define AM335X_CONF_I2C0_SDA 0x988
+#define AM335X_CONF_I2C0_SCL 0x98C
+#define AM335X_CONF_MCASP0_ACLKX 0x990
+#define AM335X_CONF_MCASP0_FSX 0x994
+#define AM335X_CONF_MCASP0_AXR0 0x998
+#define AM335X_CONF_MCASP0_AHCLKR 0x99C
+#define AM335X_CONF_MCASP0_ACLKR 0x9A0
+#define AM335X_CONF_MCASP0_FSR 0x9A4
+#define AM335X_CONF_MCASP0_AXR1 0x9A8
+#define AM335X_CONF_MCASP0_AHCLKX 0x9AC
+#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0
+#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4
+#define AM335X_CONF_WARMRSTN 0x9B8
+#define AM335X_CONF_NNMI 0x9C0
+#define AM335X_CONF_TMS 0x9D0
+#define AM335X_CONF_TDI 0x9D4
+#define AM335X_CONF_TDO 0x9D8
+#define AM335X_CONF_TCK 0x9DC
+#define AM335X_CONF_TRSTN 0x9E0
+#define AM335X_CONF_EMU0 0x9E4
+#define AM335X_CONF_EMU1 0x9E8
+#define AM335X_CONF_RTC_PWRONRSTN 0x9F8
+#define AM335X_CONF_PMIC_POWER_EN 0x9FC
+#define AM335X_CONF_EXT_WAKEUP 0xA00
+#define AM335X_CONF_RTC_KALDO_ENN 0xA04
+#define AM335X_CONF_USB0_DRVVBUS 0xA1C
+#define AM335X_CONF_USB1_DRVVBUS 0xA34
+
+/* Registers for PWM Subsystem */
+#define AM335X_PWMSS_CTRL      (0x664)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL    (0xD4)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL    (0xCC)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL    (0xD8)
+#define AM335X_CONTROL_MODULE      (0x44e10000)
+#define AM335X_CM_PER_ADDR     (0x44e00000)
+#define AM335X_PWMSS_CLKSTATUS         (0xC)
+#define AM335X_PWMSS0_MMAP_ADDR        0x48300000
+#define AM335X_PWMSS1_MMAP_ADDR        0x48302000
+#define AM335X_PWMSS2_MMAP_ADDR        0x48304000
+#define AM335X_PWMSS_MMAP_LEN          0x1000
+#define AM335X_PWMSS_IDVER         0x0
+#define AM335X_PWMSS_SYSCONFIG     0x4
+#define AM335X_PWMSS_CLKCONFIG     0x8
+#define AM335X_PWMSS_CLK_EN_ACK        0x100
+#define AM335X_EPWM_TBCTL          0x0
+#define AM335X_EPWM_TBSTS          0x2
+#define AM335X_EPWM_TBPHSHR        0x4
+#define AM335X_EPWM_TBPHS          0x6
+#define AM335X_EPWM_TBCNT          0x8
+#define AM335X_EPWM_TBPRD          0xA
+#define AM335X_EPWM_CMPCTL         0xE
+#define AM335X_EPWM_CMPAHR         0x10
+#define AM335X_EPWM_CMPA           0x12
+#define AM335X_EPWM_CMPB           0x14
+#define AM335X_EPWM_AQCTLA         0x16
+#define AM335X_EPWM_AQCTLB         0x18
+#define AM335X_EPWM_AQSFRC         0x1A
+#define AM335X_EPWM_AQCSFRC        0x1C
+#define AM335X_EPWM_DBCTL          0x1E
+#define AM335X_EPWM_DBRED          0x20
+#define AM335X_EPWM_DBFED          0x22
+#define AM335X_TBCTL_CTRMODE_UP        0x0
+#define AM335X_TBCTL_CTRMODE_DOWN      0x1
+#define AM335X_TBCTL_CTRMODE_UPDOWN    0x2
+#define AM335X_TBCTL_CTRMODE_FREEZE    0x3
+#define AM335X_EPWM_AQCTLA_ZRO_XALOW         (0x0001u)
+#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH        (0x0002u)
+#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE   (0x0003u)
+#define AM335X_EPWM_AQCTLA_CAU_SHIFT          (0x0004u)
+#define AM335X_EPWM_AQCTLA_ZRO_XBLOW         (0x0001u)
+#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH        (0x0002u)
+#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE   (0x0003u)
+#define AM335X_EPWM_AQCTLB_CBU_SHIFT          (0x0008u)
+#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE  (0x0003u)
+#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN      (0x00000001u)
+#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN      (0x00000002u)
+#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN      (0x00000004u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define AM335X_TBCTL_CLKDIV_MASK              (3 << 10)
+#define AM335X_TBCTL_HSPCLKDIV_MASK           (3 << 7)
+#define AM335X_EPWM_TBCTL_CLKDIV              (0x1C00u)
+#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT        (0x000Au)
+#define AM335X_EPWM_TBCTL_HSPCLKDIV           (0x0380u)
+#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT     (0x0007u)
+#define AM335X_EPWM_TBCTL_PRDLD               (0x0008u)
+#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK      AM335X_EPWM_TBCTL_PRDLD
+#define AM335X_EPWM_SHADOW_WRITE_ENABLE       0x0
+#define AM335X_EPWM_SHADOW_WRITE_DISABLE      0x1
+#define AM335X_EPWM_TBCTL_PRDLD_SHIFT         (0x0003u)
+#define AM335X_EPWM_TBCTL_CTRMODE             (0x0003u)
+#define AM335X_EPWM_COUNTER_MODE_MASK         AM335X_EPWM_TBCTL_CTRMODE
+#define AM335X_TBCTL_FREERUN                  (2 << 14)
+#define AM335X_TBCTL_CTRMODE_SHIFT            (0x0000u)
+#define AM335X_EPWM_COUNT_UP                  (AM335X_TBCTL_CTRMODE_UP << \
+                                                     AM335X_TBCTL_CTRMODE_SHIFT)
+
+#define AM335X_EPWM_REGS                       (0x00000200)
+#define AM335X_EPWM_0_REGS                     (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS)
+#define AM335X_EPWM_1_REGS                     (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS)
+#define AM335X_EPWM_2_REGS                     (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS)
+
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC  (0x0u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST       (0x00030000u)
+
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST       (0x00030000u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC  (0x0u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC  (0x0u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST       (0x00030000u)
+
+
+
+/* I2C registers */
+#define AM335X_I2C0_BASE 0x44e0b000
+    /* I2C0 base address */
+#define AM335X_I2C1_BASE 0x4802a000
+    /* I2C1 base address */
+#define AM335X_I2C2_BASE 0x4819c000
+    /* I2C2 base address */
+#define AM335X_I2C_REVNB_LO        0x00
+    /* Module Revision Register (low bytes) */
+#define AM335X_I2C_REVNB_HI        0x04
+    /* Module Revision Register (high bytes) */
+#define AM335X_I2C_SYSC            0x10
+    /* System Configuration Register */
+#define AM335X_I2C_IRQSTATUS_RAW   0x24
+    /* I2C Status Raw Register */
+#define AM335X_I2C_IRQSTATUS       0x28
+    /* I2C Status Register */
+#define AM335X_I2C_IRQENABLE_SET   0x2c
+    /* I2C Interrupt Enable Set Register */
+#define AM335X_I2C_IRQENABLE_CLR   0x30
+    /* I2C Interrupt Enable Clear Register */
+#define AM335X_I2C_WE              0x34
+    /* I2C Wakeup Enable Register */
+#define AM335X_I2C_DMARXENABLE_SET 0x38
+    /* Receive DMA Enable Set Register */
+#define AM335X_I2C_DMATXENABLE_SET 0x3c
+    /* Transmit DMA Enable Set Register */
+#define AM335X_I2C_DMARXENABLE_CLR 0x40
+    /* Receive DMA Enable Clear Register */
+#define AM335X_I2C_DMATXENABLE_CLR 0x44
+    /* Transmit DMA Enable Clear Register */
+#define AM335X_I2C_DMARXWAKE_EN    0x48
+    /* Receive DMA Wakeup Register */
+#define AM335X_I2C_DMATXWAKE_EN    0x4c
+    /* Transmit DMA Wakeup Register */
+#define AM335X_I2C_SYSS            0x90
+    /* System Status Register */
+#define AM335X_I2C_BUF             0x94
+    /* Buffer Configuration Register */
+#define AM335X_I2C_CNT             0x98
+    /* Data Counter Register */
+#define AM335X_I2C_DATA            0x9c
+    /* Data Access Register */
+#define AM335X_I2C_CON             0xa4
+    /* I2C Configuration Register */
+#define AM335X_I2C_OA              0xa8
+    /* I2C Own Address Register */
+#define AM335X_I2C_SA              0xac
+    /* I2C Slave Address Register */
+#define AM335X_I2C_PSC             0xb0
+    /* I2C Clock Prescaler Register */
+#define AM335X_I2C_SCLL            0xb4
+    /* I2C SCL Low Time Register */
+#define AM335X_I2C_SCLH            0xb8
+    /* I2C SCL High Time Register */
+#define AM335X_I2C_SYSTEST         0xbc
+    /* System Test Register */
+#define AM335X_I2C_BUFSTAT         0xc0
+    /* I2C Buffer Status Register */
+#define AM335X_I2C_OA1             0xc4
+    /* I2C Own Address 1 Register */
+#define AM335X_I2C_OA2             0xc8
+    /* I2C Own Address 2 Register */
+#define AM335X_I2C_OA3             0xcc
+    /* I2C Own Address 3 Register */
+#define AM335X_I2C_ACTOA           0xd0
+    /* Active Own Address Register */
+#define AM335X_I2C_SBLOCK          0xd4
+    /* I2C Clock Blocking Enable Register */
+
+#define AM335X_CM_PER_L4LS_CLKSTCTRL  (0x0)
+#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP  (0x2u)
+#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL  (0x00000003u)
+#define AM335X_CM_PER_L4LS_CLKCTRL  (0x60)
+#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
+#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE  (0x00000003u)
+#define AM335X_CM_PER_I2C1_CLKCTRL  (0x48)
+#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
+#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE  (0x00000003u)
+#define AM335X_CM_PER_I2C2_CLKCTRL (0x44)
+#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
+#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE  (0x00000003u)
+#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
+#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
+#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define AM335X_I2C_CON_XSA  (0x00000100u)
+#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR  AM335X_I2C_CON_XSA
+#define AM335X_I2C_CON_XSA_SHIFT  (0x00000008u)
+#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR  (0 << AM335X_I2C_CON_XSA_SHIFT)
+#define AM335X_I2C_CON_I2C_EN   (0x00008000u)
+#define AM335X_I2C_CON_TRX   (0x00000200u)
+#define AM335X_I2C_CON_MST   (0x00000400u)
+#define AM335X_I2C_CON_STB   (0x00000800u)
+#define AM335X_I2C_SYSC_AUTOIDLE   (0x00000001u)
+
+/*I2C0 module clock registers*/
+
+#define AM335X_CM_WKUP_CONTROL_CLKCTRL   (0x4)
+#define AM335X_CM_WKUP_CLKSTCTRL   (0x0)
+#define AM335X_CM_WKUP_I2C0_CLKCTRL   (0xb8)
+#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST   (0x00030000u)
+#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK   (0x00000800u)
+#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST   (0x00030000u)
+#define AM335X_SOC_CM_WKUP_REGS                     (AM335X_CM_PER_ADDR + 0x400)
+
+/* I2C status Register */
+#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
+#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
+#define AM335X_I2C_IRQSTATUS_AL   (1<<0)
+#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
+#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
+#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
+#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
+#define AM335X_I2C_BUF_TXFIFO_CLR   (0x00000040u)
+#define AM335X_I2C_BUF_RXFIFO_CLR   (0x00004000u)
+#define AM335X_I2C_IRQSTATUS_AAS  (1 << 9)
+#define AM335X_I2C_IRQSTATUS_BF  (1 << 8)
+#define AM335X_I2C_IRQSTATUS_STC  (1 << 6)
+#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
+#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
+#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
+
+#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
+#define AM335X_I2C_CON_STOP  (0x00000002u)
+#define AM335X_I2C_CON_START (0x00000001u)
+#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
+#define AM335X_I2C_CFG_MST_TX  (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
+#define AM335X_I2C_IRQSTATUS_RAW_BB   (0x00001000u)
+#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
+#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
+
+#endif
Index: bsps/arm/include/libcpu/mmu.h
===================================================================
--- bsps/arm/include/libcpu/mmu.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/libcpu/mmu.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,32 @@
+/*
+ *  ARM MMU header file
+ */
+
+/*
+ *  Copyright (c) 2004 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ */
+
+#ifndef __LIBCPU_MMU_H__
+#define __LIBCPU_MMU_H__
+
+#include <stdint.h>
+
+#define MMU_SECT_SIZE         0x100000
+
+#define MMU_CACHE_NONE        0x0
+#define MMU_CACHE_BUFFERED    0x1
+#define MMU_CACHE_WTHROUGH    0x2
+#define MMU_CACHE_WBACK       0x3
+
+typedef struct {
+    uint32_t paddr;
+    uint32_t vaddr;
+    uint32_t size;         /* in MB */
+    uint8_t  cache_flags;
+} mmu_sect_map_t;
+
+void mmu_init(mmu_sect_map_t *map);
+void mmu_set_cpu_async_mode(void);
+
+#endif /* __MMU_H__ */
Index: bsps/arm/include/libcpu/omap3.h
===================================================================
--- bsps/arm/include/libcpu/omap3.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/libcpu/omap3.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke@gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng@shrike-systems.com> to add lots
+ * of beagleboard/beaglebone definitions, delete lpc32xx specific
+ * ones, and merge with some other header files.
+ */
+
+/* Interrupt controller memory map */
+#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller memory map */
+#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller registers */
+#define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
+#define OMAP3_INTCPS_SYSCONFIG    0x010 /* Controls params */
+#define OMAP3_INTCPS_SYSSTATUS    0x014 /* Status */
+#define OMAP3_INTCPS_SIR_IRQ      0x040 /* Active IRQ number */
+#define OMAP3_INTCPS_SIR_FIQ      0x044 /* Active FIQ number */
+#define OMAP3_INTCPS_CONTROL      0x048 /* New int agreement bits */
+#define OMAP3_INTCPS_PROTECTION   0x04C /* Protection for other regs */
+#define OMAP3_INTCPS_IDLE         0x050 /* Clock auto-idle/gating */
+#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
+#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
+#define OMAP3_INTCPS_THRESHOLD    0x068 /* Priority threshold */
+#define OMAP3_INTCPS_ITR0         0x080 /* Raw pre-masking interrupt status */
+#define OMAP3_INTCPS_MIR0         0x084 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR1         0x0A4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR2         0x0C4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR3         0x0E4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR_CLEAR0   0x088 /* Clear interrupt mask bits */
+#define OMAP3_INTCPS_MIR_SET0     0x08C /* Set interrupt mask bits */
+#define OMAP3_INTCPS_ISR_SET0     0x090 /* Set software int bits */
+#define OMAP3_INTCPS_ISR_CLEAR0   0x094 /* Clear software int bits */
+#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
+#define OMAP3_INTCPS_ILR0         0x100 /* Priority for interrupts */
+
+/* SYSCONFIG */
+#define OMAP3_SYSCONFIG_AUTOIDLE	0x01	/* SYSCONFIG.AUTOIDLE bit */
+
+#define OMAP3_INTR_ITR(base,n) \
+    (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR(base,n) \
+    (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR_CLEAR(base,n)	\
+    (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR_SET(base,n) \
+    (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
+#define OMAP3_INTR_ISR_SET(base,n) \
+    (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
+#define OMAP3_INTR_ISR_CLEAR(base,n) \
+    (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
+#define OMAP3_INTR_PENDING_IRQ(base,n) \
+    (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
+#define OMAP3_INTR_PENDING_FIQ(base,n) \
+    (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
+#define OMAP3_INTR_ILR(base,m) \
+    (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
+
+#define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */
+#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */
+#define OMAP3_INTR_NEWIRQAGR      0x1  /* New IRQ Generation */
+
+#define OMAP3_DM337X_NR_IRQ_VECTORS    96
+
+/* Interrupt mappings */
+#define OMAP3_MCBSP2_ST_IRQ  4  /* Sidestone McBSP2 overflow */
+#define OMAP3_MCBSP3_ST_IRQ  5  /* Sidestone McBSP3 overflow */
+#define OMAP3_SYS_NIRQ       7  /* External source (active low) */
+#define OMAP3_SMX_DBG_IRQ    9  /* L3 interconnect error for debug */
+#define OMAP3_SMX_APP_IRQ   10  /* L3 interconnect error for application */
+#define OMAP3_PRCM_IRQ      11  /* PRCM module */
+#define OMAP3_SDMA0_IRQ     12  /* System DMA request 0 */
+#define OMAP3_SDMA1_IRQ     13  /* System DMA request 1 */
+#define OMAP3_SDMA2_IRQ     14  /* System DMA request 2 */
+#define OMAP3_SDMA3_IRQ     15  /* System DMA request 3 */
+#define OMAP3_MCBSP1_IRQ    16  /* McBSP module 1 */
+#define OMAP3_MCBSP2_IRQ    17  /* McBSP module 2 */
+#define OMAP3_GPMC_IRQ      20  /* General-purpose memory controller */
+#define OMAP3_SGX_IRQ       21  /* 2D/3D graphics module */
+#define OMAP3_MCBSP3_IRQ    22  /* McBSP module 3 */
+#define OMAP3_MCBSP4_IRQ    23  /* McBSP module 4 */
+#define OMAP3_CAM0_IRQ      24  /* Camera interface request 0 */
+#define OMAP3_DSS_IRQ       25  /* Display subsystem module */
+#define OMAP3_MAIL_U0_IRQ   26  /* Mailbox user 0 request */
+#define OMAP3_MCBSP5_IRQ    27  /* McBSP module 5 */
+#define OMAP3_IVA2_MMU_IRQ  28  /* IVA2 MMU */
+#define OMAP3_GPIO1_IRQ     29  /* GPIO module 1 */
+#define OMAP3_GPIO2_IRQ     30  /* GPIO module 2 */
+#define OMAP3_GPIO3_IRQ     31  /* GPIO module 3 */
+#define OMAP3_GPIO4_IRQ     32  /* GPIO module 4 */
+#define OMAP3_GPIO5_IRQ     33  /* GPIO module 5 */
+#define OMAP3_GPIO6_IRQ     34  /* GPIO module 6 */
+#define OMAP3_WDT3_IRQ      36  /* Watchdog timer module 3 overflow */
+#define OMAP3_GPT1_IRQ      37  /* General-purpose timer module 1 */
+#define OMAP3_GPT2_IRQ      38  /* General-purpose timer module 2 */
+#define OMAP3_GPT3_IRQ      39  /* General-purpose timer module 3 */
+#define OMAP3_GPT4_IRQ      40  /* General-purpose timer module 4 */
+#define OMAP3_GPT5_IRQ      41  /* General-purpose timer module 5 */
+#define OMAP3_GPT6_IRQ      42  /* General-purpose timer module 6 */
+#define OMAP3_GPT7_IRQ      43  /* General-purpose timer module 7 */
+#define OMAP3_GPT8_IRQ      44  /* General-purpose timer module 8 */
+#define OMAP3_GPT9_IRQ      45  /* General-purpose timer module 9 */
+#define OMAP3_GPT10_IRQ     46  /* General-purpose timer module 10 */
+#define OMAP3_GPT11_IRQ     47  /* General-purpose timer module 11 */
+#define OMAP3_SPI4_IRQ      48  /* McSPI module 4 */
+#define OMAP3_MCBSP4_TX_IRQ 54  /* McBSP module 4 transmit */
+#define OMAP3_MCBSP4_RX_IRQ 55  /* McBSP module 4 receive */
+#define OMAP3_I2C1_IRQ      56  /* I2C module 1 */
+#define OMAP3_I2C2_IRQ      57  /* I2C module 2 */
+#define OMAP3_HDQ_IRQ       58  /* HDQ/1-Wire */
+#define OMAP3_MCBSP1_TX_IRQ 59  /* McBSP module 1 transmit */
+#define OMAP3_MCBSP1_RX_IRQ 60  /* McBSP module 1 receive */
+#define OMAP3_I2C3_IRQ      61  /* I2C module 3 */
+#define OMAP3_MCBSP2_TX_IRQ 62  /* McBSP module 2 transmit */
+#define OMAP3_MCBSP2_RX_IRQ 63  /* McBSP module 2 receive */
+#define OMAP3_SPI1_IRQ      65  /* McSPI module 1 */
+#define OMAP3_SPI2_IRQ      66  /* McSPI module 2 */
+#define OMAP3_UART1_IRQ     72  /* UART module 1 */
+#define OMAP3_UART2_IRQ     73  /* UART module 2 */
+#define OMAP3_UART3_IRQ     74  /* UART module 3 */
+#define OMAP3_PBIAS_IRQ     75  /* Merged interrupt for PBIASlite 1/2 */
+#define OMAP3_OHCI_IRQ      76  /* OHCI HSUSB MP Host Interrupt */
+#define OMAP3_EHCI_IRQ      77  /* EHCI HSUSB MP Host Interrupt */
+#define OMAP3_TLL_IRQ       78  /* HSUSB MP TLL Interrupt */
+#define OMAP3_MCBSP5_TX_IRQ 81  /* McBSP module 5 transmit */
+#define OMAP3_MCBSP5_RX_IRQ 82  /* McBSP module 5 receive */
+#define OMAP3_MMC1_IRQ      83  /* MMC/SD module 1 */
+#define OMAP3_MMC2_IRQ      86  /* MMC/SD module 2 */
+#define OMAP3_ICR_IRQ       87  /* MPU ICR */
+#define OMAP3_D2DFRINT_IRQ  88  /* 3G coproc (in stacked modem config) */
+#define OMAP3_MCBSP3_TX_IRQ 89  /* McBSP module 3 transmit */
+#define OMAP3_MCBSP3_RX_IRQ 90  /* McBSP module 3 receive */
+#define OMAP3_SPI3_IRQ      91  /* McSPI module 3 */
+#define OMAP3_HSUSB_MC_IRQ  92  /* High-speed USB OTG */
+#define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
+#define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
+
+/* General-purpose timer register map */
+#define OMAP3_GPTIMER1_BASE  0x48318000
+    /* GPTIMER1 physical address */
+#define OMAP3_GPTIMER2_BASE  0x49032000
+    /* GPTIMER2 physical address */
+#define OMAP3_GPTIMER3_BASE  0x49034000
+    /* GPTIMER3 physical address */
+#define OMAP3_GPTIMER4_BASE  0x49036000
+    /* GPTIMER4 physical address */
+#define OMAP3_GPTIMER5_BASE  0x49038000
+    /* GPTIMER5 physical address */
+#define OMAP3_GPTIMER6_BASE  0x4903A000
+    /* GPTIMER6 physical address */
+#define OMAP3_GPTIMER7_BASE  0x4903C000
+    /* GPTIMER7 physical address */
+#define OMAP3_GPTIMER8_BASE  0x4903E000
+    /* GPTIMER8 physical address */
+#define OMAP3_GPTIMER9_BASE  0x49040000
+    /* GPTIMER9 physical address */
+#define OMAP3_GPTIMER10_BASE 0x48086000
+    /* GPTIMER10 physical address */
+#define OMAP3_GPTIMER11_BASE 0x48088000
+    /* GPTIMER11 physical address */
+
+
+/* General-purpose timer registers */
+#define OMAP3_TIMER_TIDR      0x000
+    /* IP revision code */
+#define OMAP3_TIMER_TIOCP_CFG 0x010
+    /* Controls params for GP timer L4 iface */
+#define OMAP3_TIMER_TISTAT    0x014
+    /* Status (excl. interrupt status) */
+#define OMAP3_TIMER_TISR      0x018
+    /* Pending interrupt status */
+#define OMAP3_TIMER_TIER      0x01C
+    /* Interrupt enable */
+#define OMAP3_TIMER_TWER      0x020
+    /* Wakeup enable */
+#define OMAP3_TIMER_TCLR      0x024
+    /* Controls optional features */
+#define OMAP3_TIMER_TCRR      0x028
+    /* Internal counter value */
+#define OMAP3_TIMER_TLDR      0x02C
+    /* Timer load value */
+#define OMAP3_TIMER_TTGR      0x030
+    /* Triggers counter reload */
+#define OMAP3_TIMER_TWPS      0x034
+    /* Indicates if Write-Posted pending */
+#define OMAP3_TIMER_TMAR      0x038
+    /* Value to be compared with counter */
+#define OMAP3_TIMER_TCAR1     0x03C
+    /* First captured value of counter reg */
+#define OMAP3_TIMER_TSICR     0x040
+    /* Control posted mode and functional SW rst */
+#define OMAP3_TIMER_TCAR2     0x044
+    /* Second captured value of counter register */
+#define OMAP3_TIMER_TPIR      0x048
+    /* Positive increment (1 ms tick) */
+#define OMAP3_TIMER_TNIR      0x04C
+    /* Negative increment (1 ms tick) */
+#define OMAP3_TIMER_TCVR      0x050
+    /* Defines TCRR is sub/over-period (1 ms tick) */
+#define OMAP3_TIMER_TOCR      0x054
+    /* Masks tick interrupt */
+#define OMAP3_TIMER_TOWR      0x058
+    /* Number of masked overflow interrupts */
+
+/* Interrupt status register fields */
+#define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */
+#define OMAP3_TISR_OVF_IT_FLAG  (1 << 1) /* Pending overflow interrupt status */
+#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
+
+/* Interrupt enable register fields */
+#define OMAP3_TIER_MAT_IT_ENA  (1 << 0) /* Enable match interrupt */
+#define OMAP3_TIER_OVF_IT_ENA  (1 << 1) /* Enable overflow interrupt */
+#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
+
+/* Timer control fields */
+#define OMAP3_TCLR_ST       (1 << 0)  /* Start/stop timer */
+#define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot mode */
+#define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
+#define OMAP3_TCLR_PTV      (1 << 1)  /* looks like "bleed" from Minix */
+#define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
+
+
+#define OMAP3_CM_CLKSEL_GFX		0x48004b40
+#define OMAP3_CM_CLKEN_PLL		0x48004d00
+#define OMAP3_CM_FCLKEN1_CORE	0x48004A00
+#define OMAP3_CM_CLKSEL_CORE	0x48004A40 /* GPT10 src clock sel. */
+#define OMAP3_CM_FCLKEN_PER		0x48005000
+#define OMAP3_CM_CLKSEL_PER		0x48005040
+#define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
+
+
+#define CM_MODULEMODE_MASK        (0x3 << 0)
+#define CM_MODULEMODE_ENABLE      (0x2 << 0)
+#define CM_MODULEMODE_DISABLED    (0x0 << 0)
+
+#define CM_CLKCTRL_IDLEST         (0x3 << 16)
+#define CM_CLKCTRL_IDLEST_FUNC    (0x0 << 16)
+#define CM_CLKCTRL_IDLEST_TRANS   (0x1 << 16)
+#define CM_CLKCTRL_IDLEST_IDLE    (0x2 << 16)
+#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
+
+#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
+
+#define CM_WKUP_TIMER1_CLKCTRL	(CM_WKUP_BASE + 0xC4)
+    /* This register manages the TIMER1 clocks. [Memory Mapped] */
+
+#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
+#define CM_PER_TIMER7_CLKCTRL	(CM_PER_BASE + 0x7C)
+    /* This register manages the TIMER7 clocks. [Memory Mapped] */
+
+/* CM_DPLL registers */
+
+#define CM_DPLL_BASE 	0x44E00500 /* Clock Module PLL Registers */
+
+#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
+
+#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0)
+    /* Select CLK_M_OSC clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0)
+    /* Select CLK_32KHZ clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0)
+    /* Select TCLKIN clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0)
+    /* Select CLK_RC32K clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0)
+    /* Selects the CLK_32768 from 32KHz Crystal Osc */
+
+#define CLKSEL_TIMER7_CLK   (CM_DPLL_BASE + 0x04)
+#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
+#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
+
+/*RTC CLOCK BASE & Registers*/
+#define CM_RTC_BASE            0x44E00800
+#define CM_RTC_RTC_CLKCTRL     0x0
+#define CM_RTC_CLKSTCTRL       0x4
+
+
+#define OMAP3_CLKSEL_GPT1    (1 << 0)
+#define OMAP3_CLKSEL_GPT10   (1 << 6)
+#define OMAP3_CLKSEL_GPT11   (1 << 7)
+
+#define OMAP34XX_CORE_L4_IO_BASE  0x48000000
+
+#define ARM_TTBR_ADDR_MASK (0xffffc000)
+#define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
+#define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back */
+#define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through */
+#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
+#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
+
+/* cpu control flags */
+/* CPU control register (CP15 register 1) */
+#define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
+#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
+#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
+#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
+#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
+#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
+#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
+#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
+#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
+#define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
+#define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
+#define CPU_CONTROL_SWP_ENABLE  0x00000400 /* SW: SWP{B} perform normally. */
+#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
+#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
+#define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
+#define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
+#define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
+#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
+#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
+#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
+#define CPU_CONTROL_V_ENABLE    0x01000000 /* VE: Interrupt vectors enable */
+#define CPU_CONTROL_EX_BEND     0x02000000 /* EE: exception endianness */
+#define CPU_CONTROL_NMFI        0x08000000 /* NMFI: Non maskable FIQ */
+#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
+#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
+#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
+
+#define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
+
+/* VM bits */
+
+/* Big page (1MB section) specific flags. */
+#define ARM_VM_SECTION                  (1 << 1)
+    /* 1MB section */
+#define ARM_VM_SECTION_PRESENT          (1 << 1)
+    /* Section is present */
+#define ARM_VM_SECTION_B                (1 << 2)
+    /* B Bit */
+#define ARM_VM_SECTION_C                (1 << 3)
+    /* C Bit */
+#define ARM_VM_SECTION_DOMAIN           (0xF << 5)
+    /* Domain Number */
+#define ARM_VM_SECTION_SUPER            (0x1 << 10)
+    /* Super access only AP[1:0] */
+#define ARM_VM_SECTION_USER             (0x3 << 10)
+    /* Super/User access AP[1:0] */
+#define ARM_VM_SECTION_TEX0             (1 << 12)
+    /* TEX[0] */
+#define ARM_VM_SECTION_TEX1             (1 << 13)
+    /* TEX[1] */
+#define ARM_VM_SECTION_TEX2             (1 << 14)
+    /* TEX[2] */
+#define ARM_VM_SECTION_RO               (1 << 15)
+    /* Read only access AP[2] */
+#define ARM_VM_SECTION_SHAREABLE        (1 << 16)
+    /* Shareable */
+#define ARM_VM_SECTION_NOTGLOBAL        (1 << 17)
+    /* Not Global */
+
+#define ARM_VM_SECTION_WB \
+    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
+/* inner and outer write-back, write-allocate */
+#define ARM_VM_SECTION_WT \
+    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
+/* inner and outer write-through, no write-allocate */
+#define ARM_VM_SECTION_WTWB \
+    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
+/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
+
+/* shareable device */
+#define ARM_VM_SECTION_CACHED   ARM_VM_SECTION_WTWB
+#define ARM_VM_SECTION_DEVICE   (ARM_VM_SECTION_B)
Index: bsps/arm/include/libcpu/omap_timer.h
===================================================================
--- bsps/arm/include/libcpu/omap_timer.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/libcpu/omap_timer.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,39 @@
+/**
+ * @file
+ *
+ * @brief Clock driver configuration.
+ */
+
+#include <stdint.h>
+
+typedef struct omap_timer_registers
+{
+  uint32_t TIDR;
+  uint32_t TIOCP_CFG;
+  uint32_t TISTAT;
+  uint32_t TISR;
+  uint32_t TIER;
+  uint32_t TWER;
+  uint32_t TCLR;
+  uint32_t TCRR;
+  uint32_t TLDR;
+  uint32_t TTGR;
+  uint32_t TWPS;
+  uint32_t TMAR;
+  uint32_t TCAR1;
+  uint32_t TSICR;
+  uint32_t TCAR2;
+  uint32_t TPIR;
+  uint32_t TNIR;
+  uint32_t TCVR;
+  uint32_t TOCR;
+  uint32_t TOWR;
+
+} omap_timer_registers_t;
+
+typedef struct omap_timer
+{
+  uint32_t base;
+  int irq_nr;
+  struct omap_timer_registers *regs;
+} omap_timer_t;
Index: bsps/arm/include/uart.h
===================================================================
--- bsps/arm/include/uart.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/include/uart.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,163 @@
+/**
+ *  @file
+ *
+ *  @ingroup arm_comm
+ *
+ *  @brief UART Support
+ */
+
+/*
+ * This software is Copyright (C) 1998 by T.sqware - all rights limited
+ * It is provided in to the public domain "as is", can be freely modified
+ * as far as this copyight notice is kept unchanged, but does not imply
+ * an endorsement by T.sqware of the product in which it is included.
+ *
+ * Copyright (c) Canon Research France SA.]
+ * Emmanuel Raguet, mailto:raguet@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _BSPUART_H
+#define _BSPUART_H
+
+#include <rtems/bspIo.h>
+
+void BSP_uart_init(int uart, int baud, int hwFlow);
+void BSP_uart_set_baud(int aurt, int baud);
+void BSP_uart_intr_ctrl(int uart, int cmd);
+void BSP_uart_throttle(int uart);
+void BSP_uart_unthrottle(int uart);
+int  BSP_uart_polled_status(int uart);
+void BSP_uart_polled_write(int uart, int val);
+int  BSP_uart_polled_read(int uart);
+void BSP_uart_termios_set(int uart, void *ttyp);
+int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
+int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
+void BSP_uart_termios_isr_com1();
+void BSP_uart_termios_isr_com2();
+void BSP_uart_dbgisr_com1(void);
+void BSP_uart_dbgisr_com2(void);
+extern unsigned BSP_poll_char_via_serial(void);
+extern void BSP_output_char_via_serial(int val);
+extern int BSPConsolePort;
+extern int BSPBaseBaud;
+/*
+ * Command values for BSP_uart_intr_ctrl(),
+ * values are strange in order to catch errors
+ * with assert
+ */
+#define BSP_UART_INTR_CTRL_DISABLE  (0)
+#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
+#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
+#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
+
+/* Return values for uart_polled_status() */
+#define BSP_UART_STATUS_ERROR    (-1) /* No character */
+#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
+#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
+#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
+
+/* PC UART definitions */
+#define BSP_UART_COM1            (0)
+#define BSP_UART_COM2            (1)
+
+/*
+ * Base IO for UART
+ */
+
+#define COM1_BASE_IO	0x3F8
+#define COM2_BASE_IO	0x2F8
+
+/*
+ * Offsets from base
+ */
+
+/* DLAB 0 */
+#define RBR  RSRBR   /* Rx Buffer Register (read) */
+#define THR  RSTHR   /* Tx Buffer Register (write) */
+#define IER  RSIER   /* Interrupt Enable Register */
+
+/* DLAB X */
+#define IIR  RSIIR   /* Interrupt Ident Register (read) */
+#define FCR  RSFCR   /* FIFO Control Register (write) */
+#define LCR  RSLCR   /* Line Control Register */
+#define LSR  RSLSR   /* Line Status Register */
+
+/* DLAB 1 */
+#define DLL  RSDLL   /* Divisor Latch, LSB */
+#define DLM  RSDLH   /* Divisor Latch, MSB */
+
+/* Uart control */
+#define CNT  RSCNT   /* General Control register */
+
+/*
+ * define bit for CNT
+ */
+#define UART_ENABLE 	1
+#define PAD_ENABLE	2
+
+/*
+ * Interrupt source definition via IIR
+ */
+#define NO_MORE_INTR				1
+#define TRANSMITTER_HODING_REGISTER_EMPTY	2
+#define RECEIVER_DATA_AVAIL			4
+#define RECEIVER_ERROR  			6
+#define CHARACTER_TIMEOUT_INDICATION		12
+
+/*
+ * Bits definition of IER
+ */
+#define	RECEIVE_ENABLE		0x1
+#define	TRANSMIT_ENABLE		0x2
+#define RECEIVER_LINE_ST_ENABLE	0x4
+#define INTERRUPT_DISABLE	0x0
+
+/*
+ * Bits definition of the Line Status Register (LSR)
+ */
+#define DR	0x01	/* Data Ready */
+#define OE	0x02	/* Overrun Error */
+#define PE	0x04	/* Parity Error */
+#define FE	0x08	/* Framing Error */
+#define BI	0x10	/* Break Interrupt */
+#define THRE	0x20	/* Transmitter Holding Register Empty */
+#define TEMT	0x40	/* Transmitter Empty */
+#define ERFIFO	0x80	/* Error receive Fifo */
+
+/*
+ * Bits definition of the Line Control Register (LCR)
+ */
+#define CHR_5_BITS 0
+#define CHR_6_BITS 1
+#define CHR_7_BITS 2
+#define CHR_8_BITS 3
+
+#define WL	0x03	/* Word length mask */
+#define STB	0x04	/* 1 Stop Bit, otherwise 2 Stop Bits */
+#define PEN	0x08	/* Parity Enabled */
+#define EPS	0x10	/* Even Parity Select, otherwise Odd */
+#define SP	0x20	/* Stick Parity */
+#define BCB	0x40	/* Break Control Bit */
+#define DLAB	0x80	/* Enable Divisor Latch Access */
+
+/*
+ * Bits definition of the FIFO Control Register : WD16C552 or NS16550
+ */
+
+#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
+#define FIFO_EN	    0x01    /* Enable the FIFO */
+#define XMIT_RESET  0x04    /* Transmit FIFO Reset */
+#define RCV_RESET   0x02    /* Receive FIFO Reset */
+#define FCR3	    0x08    /* do not understand manual! */
+
+#define RECEIVE_FIFO_TRIGGER1	0x0  /* trigger recieve interrupt after 1 byte  */
+#define RECEIVE_FIFO_TRIGGER4	0x40 /* trigger recieve interrupt after 4 byte  */
+#define RECEIVE_FIFO_TRIGGER8	0x80 /* trigger recieve interrupt after 8 byte  */
+#define RECEIVE_FIFO_TRIGGER12	0xc0 /* trigger recieve interrupt after 14 byte */
+#define TRIG_LEVEL  		0xc0 /* Mask for the trigger level 		*/
+
+#endif /* _BSPUART_H */
