Index: bsps/arm/beagle/headers.am
===================================================================
--- bsps/arm/beagle/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/headers.am	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,14 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/arm/beagle/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/bbb-gpio.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/bbb-pwm.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/beagleboneblack.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/i2c.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/beagle/include/bsp/irq.h
Index: bsps/arm/beagle/include/bsp.h
===================================================================
--- bsps/arm/beagle/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/bsp.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,364 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Global BSP definitions.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke@gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng@shrike-systems.com> to add lots
+ * of beagleboard/beaglebone definitions, delete lpc32xx specific
+ * ones, and merge with some other header files.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BSP_H
+#define LIBBSP_ARM_BEAGLE_BSP_H
+
+#include <bspopts.h>
+#include <stdint.h>
+#include <bsp/start.h>
+#include <bsp/default-initial-extension.h>
+#include <bsp/beagleboneblack.h>
+
+#include <rtems.h>
+#include <rtems/irq-extension.h>
+
+#include <libcpu/omap3.h>
+#include <libcpu/am335x.h>
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+/* UART base clock frequency */
+#define UART_CLOCK     48000000
+
+/* Access memory-mapped I/O devices */
+#define mmio_read(a)    (*(volatile uint32_t *)(a))
+#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
+#define mmio_set(a,v)   mmio_write((a), mmio_read((a)) | (v))
+#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
+
+#define REG16(x)(*((volatile uint16_t *)(x)))
+#define REG(x)(*((volatile uint32_t *)(x)))
+#define BIT(x)(0x1 << x)
+
+#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
+
+/* Write a uint32_t value to a memory address. */
+static inline void
+write32(uint32_t address, uint32_t value)
+{
+    REG(address) = value;
+}
+
+/* Read an uint32_t from a memory address */
+static inline uint32_t
+read32(uint32_t address)
+{
+    return REG(address);
+}
+
+/* Set a 32 bits value depending on a mask */
+static inline void
+set32(uint32_t address, uint32_t mask, uint32_t value)
+{
+    uint32_t val;
+    val = read32(address);
+    /* clear the bits */
+    val &= ~(mask);
+    /* apply the value using the mask */
+    val |= (value & mask);
+    write32(address, val);
+}
+
+/* Write a uint16_t value to a memory address. */
+static inline void
+write16(uint32_t address, uint16_t value)
+{
+    REG16(address) = value;
+}
+
+/* Read an uint16_t from a memory address */
+static inline uint16_t
+read16(uint32_t address)
+{
+    return REG16(address);
+}
+
+/* Data synchronization barrier */
+static inline void dsb(void)
+{
+    asm volatile("dsb" : : : "memory");
+}
+
+/* Instruction synchronization barrier */
+static inline void isb(void)
+{
+    asm volatile("isb" : : : "memory");
+}
+
+/* flush data cache */
+static inline void flush_data_cache(void)
+{
+    asm volatile(
+        "mov r0, #0\n"
+        "mcr p15, #0, r0, c7, c10, #4\n"
+        : /* No outputs */
+        : /* No inputs */
+        : "r0","memory"
+    );
+}
+
+#define __arch_getb(a)      (*(volatile unsigned char *)(a))
+#define __arch_getw(a)      (*(volatile unsigned short *)(a))
+#define __arch_getl(a)      (*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a)    (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)    (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)    (*(volatile unsigned int *)(a) = (v))
+
+#define writeb(v,c) ({ unsigned char  __v = v; __arch_putb(__v,c); __v; })
+#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
+#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
+
+#define readb(c)  ({ unsigned char  __v = __arch_getb(c); __v; })
+#define readw(c)  ({ unsigned short __v = __arch_getw(c); __v; })
+#define readl(c)  ({ unsigned int __v = __arch_getl(c); __v; })
+
+#define SYSTEM_CLOCK_12       12000000
+#define SYSTEM_CLOCK_13       13000000
+#define SYSTEM_CLOCK_192      19200000
+#define SYSTEM_CLOCK_96       96000000
+
+#if !defined(IS_DM3730) && !defined(IS_AM335X)
+#error Unrecognized BSP configured.
+#endif
+
+#if IS_DM3730
+#define BSP_DEVICEMEM_START 0x48000000
+#define BSP_DEVICEMEM_END   0x5F000000
+#endif
+
+#if IS_AM335X
+#define BSP_DEVICEMEM_START 0x44000000
+#define BSP_DEVICEMEM_END   0x57000000
+#endif
+
+/* per-target uart config */
+#if IS_AM335X
+#define BSP_CONSOLE_UART        1
+#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_1
+#define BSP_CONSOLE_UART_IRQ    OMAP3_UART1_IRQ
+#define BEAGLE_BASE_UART_1      0x44E09000
+#define BEAGLE_BASE_UART_2      0x48022000
+#define BEAGLE_BASE_UART_3      0x48024000
+#endif
+
+/* per-target uart config */
+#if IS_DM3730
+#define BSP_CONSOLE_UART        3
+#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_3
+#define BSP_CONSOLE_UART_IRQ    OMAP3_UART3_IRQ
+#define BEAGLE_BASE_UART_1      0x4806A000
+#define BEAGLE_BASE_UART_2      0x4806C000
+#define BEAGLE_BASE_UART_3      0x49020000
+#endif
+
+/* GPIO pin config */
+#if IS_AM335X
+#define BSP_GPIO_PIN_COUNT 128
+#define BSP_GPIO_PINS_PER_BANK 32
+#endif
+
+#if IS_DM3730
+#define BSP_GPIO_PIN_COUNT 192
+#define BSP_GPIO_PINS_PER_BANK 32
+#endif
+
+#if BSP_START_COPY_FDT_FROM_U_BOOT
+#define BSP_FDT_IS_SUPPORTED
+#endif
+
+/* i2c stuff */
+typedef struct {
+    uint32_t rx_or_tx;
+    uint32_t stat;
+    uint32_t ctrl;
+    uint32_t clk_hi;
+    uint32_t clk_lo;
+    uint32_t adr;
+    uint32_t rxfl;
+    uint32_t txfl;
+    uint32_t rxb;
+    uint32_t txb;
+    uint32_t s_tx;
+    uint32_t s_txfl;
+} beagle_i2c;
+
+/* sctlr */
+/* Read System Control Register */
+static inline uint32_t read_sctlr()
+{
+    uint32_t ctl;
+
+    asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
+        : [ctl] "=r" (ctl));
+    return ctl;
+}
+
+/* Write System Control Register */
+static inline void write_sctlr(uint32_t ctl)
+{
+    asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
+        : : [ctl] "r" (ctl));
+    isb();
+}
+
+/* Read Auxiliary Control Register */
+static inline uint32_t read_actlr()
+{
+    uint32_t ctl;
+
+    asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
+            : [ctl] "=r" (ctl));
+    return ctl;
+}
+
+/* Write Auxiliary Control Register */
+static inline void write_actlr(uint32_t ctl)
+{
+    asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
+        : : [ctl] "r" (ctl));
+    isb();
+}
+
+/* Write Translation Table Base Control Register */
+static inline void write_ttbcr(uint32_t bcr)
+{
+        asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
+                        : : [bcr] "r" (bcr));
+
+        isb();
+}
+
+/* Read Domain Access Control Register */
+static inline uint32_t read_dacr()
+{
+        uint32_t dacr;
+
+        asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
+                        : [dacr] "=r" (dacr));
+
+        return dacr;
+}
+
+
+/* Write Domain Access Control Register */
+static inline void write_dacr(uint32_t dacr)
+{
+        asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
+                        : : [dacr] "r" (dacr));
+
+        isb();
+}
+
+static inline void refresh_tlb(void)
+{
+    dsb();
+
+    /* Invalidate entire unified TLB */
+    asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
+        : : [zero] "r" (0));
+
+    /* Invalidate all instruction caches to PoU.
+     * Also flushes branch target cache. */
+    asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
+        : : [zero] "r" (0));
+
+    /* Invalidate entire branch predictor array */
+    asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
+        : : [zero] "r" (0)); /* flush BTB */
+
+    dsb();
+    isb();
+}
+
+/* Read Translation Table Base Register 0 */
+static inline uint32_t read_ttbr0()
+{
+    uint32_t bar;
+
+    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+        : [bar] "=r" (bar));
+
+    return bar & ARM_TTBR_ADDR_MASK;
+}
+
+
+/* Read Translation Table Base Register 0 */
+static inline uint32_t read_ttbr0_unmasked()
+{
+    uint32_t bar;
+
+    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+        : [bar] "=r" (bar));
+
+    return bar;
+}
+
+/* Write Translation Table Base Register 0 */
+static inline void write_ttbr0(uint32_t bar)
+{
+    dsb();
+    isb();
+    /* In our setup TTBR contains the base address *and* the flags
+       but other pieces of the kernel code expect ttbr to be the
+       base address of the l1 page table. We therefore add the
+       flags here and remove them in the read_ttbr0 */
+    uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
+    asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
+        : : [bar] "r" (v));
+
+    refresh_tlb();
+}
+
+/* Behaviour on fatal error; default: test-friendly.
+ * set breakpoint to bsp_fatal_extension.
+ */
+/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
+/*#define  BSP_PRESS_KEY_FOR_RESET     1 */
+#define    BSP_PRINT_EXCEPTION_CONTEXT 1
+    /* human-readable exception info */
+#define    BSP_RESET_BOARD_AT_EXIT 1
+    /* causes qemu to exit, signaling end of test */
+
+
+/**
+ * @defgroup arm_beagle Beaglebone, Beagleboard Support
+ *
+ * @ingroup bsp_arm
+ *
+ * @brief Beaglebones and beagleboards support package
+ *
+ */
+
+/**
+ * @brief Beagleboard specific set up of the MMU.
+ *
+ * Provide in the application to override.
+ */
+BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
+
+#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
Index: bsps/arm/beagle/include/bsp/bbb-gpio.h
===================================================================
--- bsps/arm/beagle/include/bsp/bbb-gpio.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/bsp/bbb-gpio.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BBB_GPIO_H
+#define LIBBSP_ARM_BEAGLE_BBB_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief  BeagleBone Black GPIO functions.
+ */
+#define BBB_DIGITAL_IN  2
+#define BBB_DIGITAL_OUT 1
+
+/**
+ * @brief  BeagleBone Black GPIO pad configuration.
+ */
+#define BBB_PUDEN (1 << 3)
+#define BBB_PUDDIS ~BBB_PUDEN
+#define BBB_PU_EN (1 << 4)
+#define BBB_PD_EN ~BBB_PU_EN
+#define BBB_MUXMODE(X) (X & 0x7)
+#define BBB_RXACTIVE (1 << 5)
+#define BBB_SLEWCTRL (1 << 6)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */
Index: bsps/arm/beagle/include/bsp/bbb-pwm.h
===================================================================
--- bsps/arm/beagle/include/bsp/bbb-pwm.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/bsp/bbb-pwm.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,178 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black PWM support definitions.
+ */
+
+/**
+ * Copyright (c) 2016 Punit Vara <punitvara@gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/** Some constants are taken from 
+ * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H
+#define LIBBSP_ARM_BEAGLE_BBB_PWM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief  BeagleBone Black PWM Macros.
+ */
+#define BBB_CONTROL_CONF_GPMC_AD(n)   (0x800 + (n * 4))
+#define BBB_CONTROL_CONF_LCD_DATA(n)   (0x8a0 + (n * 4))
+
+/**
+ * @brief The set of possible PWM subsystem module
+ *
+ * Enumerated type to define various instance of pwm module.
+ */
+typedef enum{
+  BBB_PWMSS0 = 0,
+  BBB_PWMSS1,
+  BBB_PWMSS2,
+  BBB_PWMSS_COUNT
+}BBB_PWMSS;
+
+typedef enum{
+  BBB_P8_13_2B = 3,
+  BBB_P8_19_2A,
+  BBB_P8_45_2A,
+  BBB_P8_46_2B,
+  BBB_P8_34_1B,
+  BBB_P8_36_1A,
+  BBB_P9_14_1A,
+  BBB_P9_16_1B,
+  BBB_P9_21_0B,
+  BBB_P9_22_0A,
+  BBB_P9_29_0B,
+  BBB_P9_31_0A
+}bbb_pwm_pin_t;
+
+#define BBB_P8_13_MUX_PWM 4 
+#define BBB_P8_19_MUX_PWM 4
+#define BBB_P8_45_MUX_PWM 3
+#define BBB_P8_46_MUX_PWM 3
+#define BBB_P8_34_MUX_PWM 2
+#define BBB_P8_36_MUX_PWM 2
+#define BBB_P9_14_MUX_PWM 6
+#define BBB_P9_16_MUX_PWM 6
+#define BBB_P9_21_MUX_PWM 3
+#define BBB_P9_22_MUX_PWM 3
+#define BBB_P9_29_MUX_PWM 1
+#define BBB_P9_31_MUX_PWM 1
+#define BBB_PWM_FREQ_THRESHOLD 0.5f
+
+/**
+ * @brief  BeagleBone Black PWM API.
+ */
+
+/**
+ * @brief This function intilizes clock for pwm sub system.
+ *
+ * @param PWMSS_ID It is the instance number of EPWM of pwm sub system.
+ * 
+ * @return true if successful 
+ * @return false if not successful
+ *
+ **/
+bool beagle_pwm_init(BBB_PWMSS pwmss_id);
+
+/* PWMSS setting
+ *      set pulse argument of epwm module
+ *
+ *      @param pwm_id    : EPWMSS number , 0~2
+ *      @param pwm_freq : frequency to be generated
+ *      @param dutyA    : Duty Cycle(in percentage) in PWM channel A
+ *      @param dutyB    : Duty Cycle(in percentage) in PWM channel B
+ *
+ *      @return         : 1 for success
+ *      @return         : 0 for failed
+ *
+ *      @example        :  beagle_pwm_configure(0 , 50.0f , 50.0f , 25.0f);      // Generate 50HZ pwm in PWM0 ,
+ *                                                                              // duty cycle is 50% for ePWM0A , 25% for ePWM0B
+ *
+ *      @Note :
+ *              find an number nearst 65535 for TBPRD , to improve duty precision,
+ *
+ *              Using big TBPRD can increase the range of CMPA and CMPB ,
+ *              and it means we can get better precision on duty cycle.
+ *
+ *              EX : 20.25% duty cycle
+ *                  on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
+ *                  on TBPRD = 6250  , CMPA = 1265.625 ( .625 rejection), real duty : 20.24%   (1265 6250)
+ *                  on TBPRD = 500   , CMPA = 101.25   ( .25 rejection) , real duty : 20.2%    (101/500)
+ *
+ *              Divisor = CLKDIV * HSPCLKDIV
+ *                      1 TBPRD : 10 ns (default)
+ *                      65535 TBPRD : 655350 ns
+ *                      65535 TBPRD : 655350 * Divisor ns  = X TBPRD : Cycle
+ *
+ *              accrooding to that , we must find a Divisor value , let X nearest 65535 .
+ *              so , Divisor must  Nearest Cycle/655350
+ */
+int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b);
+
+/**
+ * @brief   This API enables the particular PWM module.
+ *
+ * @param   pwmid  It is the instance number of EPWM of pwm sub system.
+ *
+ * @return  true if successful
+ * @return  false if fail
+ *
+ **/
+bool beagle_pwm_enable(BBB_PWMSS pwmid);
+
+/**
+ * @brief   This API disables the particular PWM module.
+ *
+ * @param   pwmid  It is the instance number of EPWM of pwm sub system.
+ *
+ * @return  true if successful
+ * @return  false if fail
+ *
+ **/
+bool beagle_pwm_disable(BBB_PWMSS pwmid);
+
+/**
+ * @brief   This function enables pinmuxing for PWM module.
+ *
+ * @param   pin_no  It is individual pin at which freuqency need to be generated.
+ *                  It should be according to pwm sub system.
+ *
+ * @param   pwm_id  It is the instance number of EPWM of pwmsubsystem.
+ *
+ * @return  true if successful
+ * @return  false if fail
+ *
+ **/
+bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id);
+
+/**
+ * @brief   This function determines whether PWMSS-wide clocks enabled or not.
+ *
+ * @param   pwmss_id  It is the instance number of PWMSS which clocks need to be
+ *                    checked.
+ * 
+ * @return  true if successful
+ * @return  false if fail
+ *
+ **/
+bool beagle_pwmss_is_running(unsigned int pwmss_id);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_BBB_PWM_H */
Index: bsps/arm/beagle/include/bsp/beagleboneblack.h
===================================================================
--- bsps/arm/beagle/include/bsp/beagleboneblack.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/bsp/beagleboneblack.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
+#define LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
+
+/* In general GPIOs of BeagleBone Black/White can be addressed
+ * using two 46-pin dual-row expansion connectors P9 and P8,
+ * which are also known as Expansion A and Expansion B Connectors,
+ * respectively.
+ *
+ * Each Expansion Connector consists of 23 pins. So 2x23 pins would
+ * be available. It has 4 GPIO Banks each consists of 32 pins each.
+ * Toatal number of pins are 128 (32x4).
+ *
+ * So for mapping between generalized pin name and the unique pin
+ * numbers in this header file Macros are declared.
+ */
+
+/* USER LEDs of BeagleBone Black */
+#define BBB_LED_USR0  53 /* USR LED0 */
+#define BBB_LED_USR1  54 /* USR LED1 */
+#define BBB_LED_USR2  55 /* USR LED2 */
+#define BBB_LED_USR3  56 /* USR LED3 */
+
+/* Header P8 of BeagleBone Black */
+#define BBB_P8_7      66 /* GPIO2_2 */
+#define BBB_P8_8      67 /* GPIO2_3 */
+#define BBB_P8_9      69 /* GPIO2_5 */
+#define BBB_P8_10     68 /* GPIO2_4 */
+#define BBB_P8_11     45 /* GPIO1_13 */
+#define BBB_P8_12     44 /* GPIO1_12 */
+#define BBB_P8_13     23 /* GPIO0_23 */
+#define BBB_P8_14     26 /* GPIO0_26 */
+#define BBB_P8_15     47 /* GPIO1_15 */
+#define BBB_P8_16     46 /* GPIO1_14 */
+#define BBB_P8_17     27 /* GPIO0_27 */
+#define BBB_P8_18     65 /* GPIO2_1 */
+#define BBB_P8_19     22 /* GPIO0_22 */
+#define BBB_P8_26     61 /* GPIO1_29 */
+	
+/* Header P9 of BeagleBone Black */
+#define BBB_P9_11     30 /* GPIO0_30 */
+#define BBB_P9_12     60 /* GPIO1_28 */
+#define BBB_P9_13     31 /* GPIO0_31 */
+#define BBB_P9_14     50 /* GPIO1_18 */
+#define BBB_P9_15     48 /* GPIO1_16 */
+#define BBB_P9_16     51 /* GPIO1_19 */
+#define BBB_P9_17      5 /* GPIO0_5 */
+#define BBB_P9_18      4 /* GPIO0_4 */
+#define BBB_P9_23     49 /* GPIO1_17 */
+#define BBB_P9_24     15 /* GPIO0_15 */
+#define BBB_P9_26     14 /* GPIO1_14 */
+#define BBB_P9_27     115/* GPIO3_19 */
+#define BBB_P9_30     112/* GPIO3_16 */
+#define BBB_P9_41     20 /* GPIO0_20 */
+#define BBB_P9_42      7 /* GPIO0_7 */
+
+#endif /* LIBBSP_ARM_BEAGLE_GPIO_H */
Index: bsps/arm/beagle/include/bsp/i2c.h
===================================================================
--- bsps/arm/beagle/include/bsp/i2c.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/bsp/i2c.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,211 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief I2C support API.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke@gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_I2C_H
+#define LIBBSP_ARM_BEAGLE_I2C_H
+
+#include <rtems.h>
+#include <dev/i2c/i2c.h>
+#include <bsp.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define BBB_I2C_CON_EN  (1 << 15)  /* I2C module enable */
+#define BBB_I2C_CON_BE  (1 << 14)  /* Big endian mode */
+#define BBB_I2C_CON_STB (1 << 11)  /* Start byte mode (master mode only) */
+#define BBB_I2C_CON_MST (1 << 10)  /* Master/slave mode */
+#define BBB_I2C_CON_TRX (1 << 9)   /* Transmitter/receiver mode */
+           /* (master mode only) */
+#define BBB_I2C_CON_XA  (1 << 8)   /* Expand address */
+#define BBB_I2C_CON_STP (1 << 1)   /* Stop condition (master mode only) */
+#define BBB_I2C_CON_STT (1 << 0)   /* Start condition (master mode only) */
+#define BBB_I2C_CON_CLR 0x0  /* Clear configuration register */
+/* I2C Status Register (I2C_STAT): */
+
+#define BBB_I2C_STAT_SBD  (1 << 15) /* Single byte data */
+#define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */
+#define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define BBB_I2C_STAT_AAS  (1 << 9)  /* Address as slave */
+#define BBB_I2C_STAT_GC (1 << 5)
+#define BBB_I2C_STAT_XRDY (1 << 4)  /* Transmit data ready */
+#define BBB_I2C_STAT_RRDY (1 << 3)  /* Receive data ready */
+#define BBB_I2C_STAT_ARDY (1 << 2)  /* Register access ready */
+#define BBB_I2C_STAT_NACK (1 << 1)  /* No acknowledgment interrupt enable */
+#define BBB_I2C_STAT_AL (1 << 0)  /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define BBB_I2C_IE_GC_IE  (1 << 5)
+#define BBB_I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
+#define BBB_I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
+#define BBB_I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
+#define BBB_I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
+#define BBB_I2C_IE_AL_IE  (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C SYSC Register (I2C_SYSC): */
+#define BBB_I2C_SYSC_SRST (1 << 1)
+
+#define BBB_I2C_TIMEOUT 1000
+
+#define BBB_I2C_SYSS_RDONE            (1 << 0)  /* Internel reset monitoring */
+
+#define BBB_CONFIG_SYS_I2C_SPEED    100000
+#define BBB_CONFIG_SYS_I2C_SLAVE    1
+#define BBB_I2C_ALL_FLAGS 0x7FFF
+#define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF
+
+#define BBB_I2C_SYSCLK 48000000
+#define BBB_I2C_INTERNAL_CLK 12000000
+#define BBB_I2C_SPEED_CLK 100000
+
+#define BBB_I2C_IRQ_ERROR \
+  ( AM335X_I2C_IRQSTATUS_NACK \
+    | AM335X_I2C_IRQSTATUS_ROVR \
+    | AM335X_I2C_IRQSTATUS_AL \
+    | AM335X_I2C_IRQSTATUS_ARDY \
+    | AM335X_I2C_IRQSTATUS_RRDY \
+    | AM335X_I2C_IRQSTATUS_XRDY \
+    | AM335X_I2C_IRQSTATUS_XUDF )
+
+#define BBB_I2C_IRQ_USED \
+  ( AM335X_I2C_IRQSTATUS_ARDY \
+    | AM335X_I2C_IRQSTATUS_XRDY )
+
+#define BBB_I2C_0_BUS_PATH "/dev/i2c-0"
+#define BBB_I2C_1_BUS_PATH "/dev/i2c-1"
+#define BBB_I2C_2_BUS_PATH "/dev/i2c-2"
+
+#define BBB_I2C0_IRQ 70
+#define BBB_I2C1_IRQ 71
+#define BBB_I2C2_IRQ 30
+
+#define BBB_MODE2 2
+#define BBB_MODE3 3
+
+typedef enum {
+  I2C0,
+  I2C1,
+  I2C2,
+  I2C_COUNT
+} bbb_i2c_id_t;
+
+typedef struct i2c_regs {
+  uint32_t BBB_I2C_REVNB_LO;
+  uint32_t BBB_I2C_REVNB_HI;
+  uint32_t dummy1[ 2 ];
+  uint32_t BBB_I2C_SYSC;
+  uint32_t dummy2[ 4 ];
+  uint32_t BBB_I2C_IRQSTATUS_RAW;
+  uint32_t BBB_I2C_IRQSTATUS;
+  uint32_t BBB_I2C_IRQENABLE_SET;
+  uint32_t BBB_I2C_IRQENABLE_CLR;
+  uint32_t BBB_I2C_WE;
+  uint32_t BBB_I2C_DMARXENABLE_SET;
+  uint32_t BBB_I2C_DMATXENABLE_SET;
+  uint32_t BBB_I2C_DMARXENABLE_CLR;
+  uint32_t BBB_I2C_DMATXENABLE_CLR;
+  uint32_t BBB_I2C_DMARXWAKE_EN;
+  uint32_t BBB_I2C_DMATXWAKE_EN;
+  uint32_t dummy3[ 16 ];
+  uint32_t BBB_I2C_SYSS;
+  uint32_t BBB_I2C_BUF;
+  uint32_t BBB_I2C_CNT;
+  uint32_t BBB_I2C_DATA;
+  uint32_t dummy4;
+  uint32_t BBB_I2C_CON;
+  uint32_t BBB_I2C_OA;
+  uint32_t BBB_I2C_SA;
+  uint32_t BBB_I2C_PSC;
+  uint32_t BBB_I2C_SCLL;
+  uint32_t BBB_I2C_SCLH;
+  uint32_t BBB_I2C_SYSTEST;
+  uint32_t BBB_I2C_BUFSTAT;
+  uint32_t BBB_I2C_OA1;
+  uint32_t BBB_I2C_OA2;
+  uint32_t BBB_I2C_OA3;
+  uint32_t BBB_I2C_ACTOA;
+  uint32_t BBB_I2C_SBLOCK;
+} bbb_i2c_regs;
+
+typedef struct bbb_i2c_bus {
+  i2c_bus base;
+  volatile bbb_i2c_regs *regs;
+  i2c_msg *msgs;
+  uint32_t msg_todo;
+  uint32_t current_msg_todo;
+  uint8_t *current_msg_byte;
+  uint32_t current_todo;
+  bool read;
+  bool hold;
+  rtems_id task_id;
+  rtems_vector_number irq;
+  uint32_t input_clock;
+  uint32_t already_transferred;
+} bbb_i2c_bus;
+
+int am335x_i2c_bus_register(
+  const char         *bus_path,
+  uintptr_t           register_base,
+  uint32_t            input_clock,
+  rtems_vector_number irq
+);
+
+static inline int bbb_register_i2c_0( void )
+{
+  return am335x_i2c_bus_register(
+    BBB_I2C_0_BUS_PATH,
+    AM335X_I2C0_BASE,
+    I2C_BUS_CLOCK_DEFAULT,
+    BBB_I2C0_IRQ
+  );
+}
+
+static inline int bbb_register_i2c_1( void )
+{
+  return am335x_i2c_bus_register(
+    BBB_I2C_1_BUS_PATH,
+    AM335X_I2C1_BASE,
+    I2C_BUS_CLOCK_DEFAULT,
+    BBB_I2C1_IRQ
+  );
+}
+
+static inline int bbb_register_i2c_2( void )
+{
+  return am335x_i2c_bus_register(
+    BBB_I2C_2_BUS_PATH,
+    AM335X_I2C2_BASE,
+    I2C_BUS_CLOCK_DEFAULT,
+    BBB_I2C2_IRQ
+  );
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_I2C_H */
Index: bsps/arm/beagle/include/bsp/irq.h
===================================================================
--- bsps/arm/beagle/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/bsp/irq.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,23 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Basic BSP IRQ info.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_IRQ_H
+#define LIBBSP_ARM_BEAGLE_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 127
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_BEAGLE_IRQ_H */
Index: bsps/arm/beagle/include/tm27.h
===================================================================
--- bsps/arm/beagle/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
+++ bsps/arm/beagle/include/tm27.h	(revision 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9)
@@ -0,0 +1,1 @@
+#include <rtems/tm27-default.h>
