Changeset 2adc507f in rtems


Ignore:
Timestamp:
Feb 28, 2013, 7:08:21 PM (7 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.11, master
Children:
e2b4891
Parents:
aa314cf
git-author:
Joel Sherrill <joel.sherrill@…> (02/28/13 19:08:21)
git-committer:
Joel Sherrill <joel.sherrill@…> (02/28/13 19:08:51)
Message:

cpukit moxie: Style corrections

Location:
cpukit/score/cpu/moxie
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/moxie/cpu.c

    raa314cf r2adc507f  
    2828 *  INPUT PARAMETERS: NONE
    2929 */
    30 
    31 
    3230void _CPU_Initialize(void)
    3331{
     
    4240}
    4341
    44 /*PAGE
    45  *
     42/*
    4643 *  _CPU_ISR_Get_level
    4744 *
    4845 *  This routine returns the current interrupt level.
    4946 */
    50 
    5147uint32_t   _CPU_ISR_Get_level( void )
    5248{
     
    5450}
    5551
    56 /*PAGE
    57  *
     52/*
    5853 *  _CPU_ISR_install_raw_handler
    5954 */
    60 
    6155void _CPU_ISR_install_raw_handler(
    6256  uint32_t    vector,
     
    7367}
    7468
    75 /*PAGE
    76  *
     69/*
    7770 *  _CPU_ISR_install_vector
    7871 *
     
    8881 *
    8982 */
    90 
    9183void _CPU_ISR_install_vector(
    9284  uint32_t    vector,
     
    113105}
    114106
    115 /*PAGE
    116  *
     107/*
    117108 *  _CPU_Install_interrupt_stack
    118109 */
    119 
    120110void _CPU_Install_interrupt_stack( void )
    121111{
    122112}
    123113
    124 /*PAGE
    125  *
     114/*
    126115 *  _CPU_Thread_Idle_body
    127116 *
     
    138127 *     hook with caution.
    139128 */
    140 
    141129#if 0
    142130void *_CPU_Thread_Idle_body( uintptr_t ignored )
  • cpukit/score/cpu/moxie/rtems/score/cpu.h

    raa314cf r2adc507f  
    5252 *  XXX
    5353 */
    54 
    5554#define CPU_INLINE_ENABLE_DISPATCH       FALSE
    5655
     
    7675 *  XXX
    7776 */
    78 
    7977#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
    8078
     
    112110 *  XXX
    113111 */
    114 
    115112#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    116113
     
    146143 *  XXX
    147144 */
    148 
    149145#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    150146
     
    161157 *  XXX
    162158 */
    163 
    164159#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    165160
     
    183178 *  XXX
    184179 */
    185 
    186180#define CPU_HARDWARE_FP     FALSE
    187181
     
    198192 *  XXX
    199193 */
    200 
    201194#define CPU_ALL_TASKS_ARE_FP     FALSE
    202195
     
    216209 *  XXX
    217210 */
    218 
    219211#define CPU_IDLE_TASK_IS_FP      FALSE
    220212
     
    248240 *  XXX
    249241 */
    250 
    251242#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
    252243
     
    278269 *  the BSP in newer versions of RTEMS.
    279270 */
    280 
    281271#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    282272
     
    292282 *  XXX
    293283 */
    294 
    295284#define CPU_STACK_GROWS_UP               FALSE
    296285
     
    318307 *  XXX
    319308 */
    320 
    321309#define CPU_STRUCTURE_ALIGNMENT
    322310
     
    329317 *  routines are handled.
    330318 */
    331 
    332319#define CPU_BIG_ENDIAN                           TRUE
    333320#define CPU_LITTLE_ENDIAN                        FALSE
     
    342329 *  XXX
    343330 */
    344 
    345331#define CPU_MODES_INTERRUPT_MASK   0x00000001
    346332
     
    393379 *  XXX
    394380 */
    395 
    396 
    397381
    398382#define nogap __attribute__ ((packed))
     
    438422 *  XXX
    439423 */
    440 
    441424SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    442425
     
    448431 *  XXX
    449432 */
    450 
    451 /* XXX: if needed, put more variables here */
    452433
    453434/*
     
    461442 *  XXX
    462443 */
    463 
    464444#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
    465445
     
    473453 *  It is highly unlikely the MOXIE will get used in a multiprocessor system.
    474454 */
    475 
    476455#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
    477456
     
    484463 *  XXX
    485464 */
    486 
    487465#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
    488 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
     466#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
     467    (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
    489468
    490469/*
     
    492471 *  level.  Most ports maintain the variable _ISR_Nest_level.
    493472 */
    494 
    495473#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    496474
     
    503481 *  XXX
    504482 */
    505 
    506483#define CPU_STACK_MINIMUM_SIZE          (1536)
    507484
     
    523500 *  XXX
    524501 */
    525 
    526502#define CPU_ALIGNMENT              8
    527503
     
    541517 *  XXX
    542518 */
    543 
    544519#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
    545520
     
    559534 *  XXX
    560535 */
    561 
    562536#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
    563537
     
    574548 *  XXX
    575549 */
    576 
    577550#define CPU_STACK_ALIGNMENT        0
    578551
     
    584557 *  Support routine to initialize the RTEMS vector table after it is allocated.
    585558 */
    586 
    587559#define _CPU_Initialize_vectors()
    588560
     
    595567 *  XXX
    596568 */
    597 
    598569#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
    599570
     
    607578 *  XXX
    608579 */
    609 
    610580#define _CPU_ISR_Enable( _isr_cookie )
    611581
     
    620590 *  XXX
    621591 */
    622 
    623592#define _CPU_ISR_Flash( _isr_cookie )
    624593
     
    637606 *  XXX
    638607 */
    639 
    640608#define _CPU_ISR_Set_level( _new_level )        \
    641609  {                                                     \
     
    674642 *  XXX
    675643 */
    676 
    677 
    678644#define CPU_CCR_INTERRUPTS_ON  0x80
    679645#define CPU_CCR_INTERRUPTS_OFF 0x00
     
    706672 *  XXX
    707673 */
    708 
    709674#define _CPU_Context_Restart_self( _the_context ) \
    710675   _CPU_Context_restore( (_the_context) );
     
    727692 *  XXX
    728693 */
    729 
    730694#define _CPU_Context_Fp_start( _base, _offset ) \
    731695   ( (void *) (_base) + (_offset) )
     
    746710 *  XXX
    747711 */
    748 
    749712#define _CPU_Context_Initialize_fp( _destination ) \
    750713  { \
     
    765728 *  XXX
    766729 */
    767 
    768730#define _CPU_Fatal_halt( _error ) \
    769731        printk("Fatal Error %d Halted\n",_error); \
    770732        for(;;)
    771 
    772733
    773734/* end of Fatal Error manager macros */
     
    833794 *  XXX
    834795 */
    835 
    836796#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
    837797#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
     
    857817 *  XXX
    858818 */
    859 
    860819#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    861820
     
    875834 *  XXX
    876835 */
    877 
    878836#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    879837
     
    896854 *  XXX
    897855 */
    898 
    899856void _CPU_Initialize(void);
    900857
     
    909866 *  XXX
    910867 */
    911 
    912868void _CPU_ISR_install_raw_handler(
    913869  uint32_t    vector,
     
    925881 *  XXX
    926882 */
    927 
    928883void _CPU_ISR_install_vector(
    929884  uint32_t    vector,
     
    944899 *  XXX
    945900 */
    946 
    947901void _CPU_Install_interrupt_stack( void );
    948902
     
    959913 *  XXX
    960914 */
    961 
    962915void *_CPU_Thread_Idle_body( uint32_t );
    963916
     
    971924 *  XXX
    972925 */
    973 
    974926void _CPU_Context_switch(
    975927  Context_Control  *run,
     
    989941 *  XXX
    990942 */
    991 
    992943void _CPU_Context_restore(
    993944  Context_Control *new_context
     
    1003954 *  XXX
    1004955 */
    1005 
    1006956void _CPU_Context_save_fp(
    1007957  Context_Control_fp **fp_context_ptr
     
    1017967 *  XXX
    1018968 */
    1019 
    1020969void _CPU_Context_restore_fp(
    1021970  Context_Control_fp **fp_context_ptr
     
    10651014 *  This is the generic implementation.
    10661015 */
    1067 
    10681016static inline uint32_t   CPU_swap_u32(
    10691017  uint32_t   value
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