Changeset 2a7f710f in rtems


Ignore:
Timestamp:
Mar 31, 2004, 4:14:40 AM (16 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
d89f13a
Parents:
654c115c
Message:

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

  • console/uart.c, include/ep7312.h, startup/bspstart.c, timer/timer.c: Convert to using c99 fixed size types.
Location:
c/src/lib/libbsp/arm/edb7312
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/edb7312/ChangeLog

    r654c115c r2a7f710f  
     12004-03-31      Ralf Corsepius <ralf_corsepius@rtems.org>
     2
     3        * console/uart.c, include/ep7312.h, startup/bspstart.c,
     4        timer/timer.c: Convert to using c99 fixed size types.
     5
    162004-02-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    27
  • c/src/lib/libbsp/arm/edb7312/console/uart.c

    r654c115c r2a7f710f  
    5757        8,                                /* ulHysteresis */
    5858        NULL,                             /* pDeviceParams */
    59         (unsigned32)EP7312_UARTCR1,       /* ulCtrlPort1 */
    60         (unsigned32)EP7312_SYSFLG1,       /* ulCtrlPort2 */
    61         (unsigned32)EP7312_UARTDR1,       /* ulDataPort */
     59        (uint32_t)EP7312_UARTCR1,       /* ulCtrlPort1 */
     60        (uint32_t)EP7312_SYSFLG1,       /* ulCtrlPort2 */
     61        (uint32_t)EP7312_UARTDR1,       /* ulDataPort */
    6262        0,                                /* getRegister */
    6363        0,                                /* setRegister */
     
    8787int uart_poll_read(int minor)
    8888{
    89     volatile unsigned32 *data_reg;
    90     volatile unsigned32 *ctrl_reg1;
    91     volatile unsigned32 *ctrl_reg2;
     89    volatile uint32_t  *data_reg;
     90    volatile uint32_t  *ctrl_reg1;
     91    volatile uint32_t  *ctrl_reg2;
    9292    char        c;
    9393    int         err;
    9494
    95     data_reg = (unsigned32*)Console_Port_Tbl[minor].ulDataPort;
    96     ctrl_reg1 = (unsigned32*)Console_Port_Tbl[minor].ulCtrlPort1;
    97     ctrl_reg2 = (unsigned32*)Console_Port_Tbl[minor].ulCtrlPort2;
     95    data_reg = (uint32_t*)Console_Port_Tbl[minor].ulDataPort;
     96    ctrl_reg1 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort1;
     97    ctrl_reg2 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort2;
    9898
    9999    if ((*ctrl_reg2 & EP7312_UART_URXFE1) != 0) {
     
    115115static int uart_write(int minor, const char *buf, int len)
    116116{
    117     volatile unsigned32 *data_reg;
    118     volatile unsigned32 *ctrl_reg1;
    119     volatile unsigned32 *ctrl_reg2;
     117    volatile uint32_t  *data_reg;
     118    volatile uint32_t  *ctrl_reg1;
     119    volatile uint32_t  *ctrl_reg2;
    120120    int i;
    121121    char c;
    122122
    123     data_reg = (unsigned32*)Console_Port_Tbl[minor].ulDataPort;
    124     ctrl_reg1 = (unsigned32*)Console_Port_Tbl[minor].ulCtrlPort1;
    125     ctrl_reg2 = (unsigned32*)Console_Port_Tbl[minor].ulCtrlPort2;
     123    data_reg = (uint32_t*)Console_Port_Tbl[minor].ulDataPort;
     124    ctrl_reg1 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort1;
     125    ctrl_reg2 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort2;
    126126
    127127    for (i = 0; i < len; i++) {
     
    140140static void uart_init(int minor)
    141141{
    142     volatile unsigned32 *data_reg;
    143     volatile unsigned32 *ctrl_reg1;
    144     volatile unsigned32 *ctrl_reg2;
     142    volatile uint32_t  *data_reg;
     143    volatile uint32_t  *ctrl_reg1;
     144    volatile uint32_t  *ctrl_reg2;
    145145   
    146     data_reg = (unsigned32*)Console_Port_Tbl[minor].ulDataPort;
    147     ctrl_reg1 = (unsigned32*)Console_Port_Tbl[minor].ulCtrlPort1;
    148     ctrl_reg2 = (unsigned32*)Console_Port_Tbl[minor].ulCtrlPort2;
     146    data_reg = (uint32_t*)Console_Port_Tbl[minor].ulDataPort;
     147    ctrl_reg1 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort1;
     148    ctrl_reg2 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort2;
    149149
    150150    /*   *ctrl_reg = (BSP_UART_DATA8       |
  • c/src/lib/libbsp/arm/edb7312/include/ep7312.h

    r654c115c r2a7f710f  
    2424#define EP7312_REG_BASE 0x80000000
    2525
    26 #define EP7312_PADR    ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0000))
    27 #define EP7312_PBDR    ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0001))
    28 #define EP7312_PDDR    ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0003))
    29 #define EP7312_PADDR   ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0040))
    30 #define EP7312_PBDDR   ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0041))
    31 #define EP7312_PDDDR   ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0043))
    32 #define EP7312_PEDR    ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0080))
    33 #define EP7312_PEDDR   ((volatile unsigned8  *)(EP7312_REG_BASE + 0x00C0))
    34 #define EP7312_SYSCON1 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0100))
    35 #define EP7312_SYSFLG1 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0140))
    36 #define EP7312_MEMCFG1 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0180))
    37 #define EP7312_MEMCFG2 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x01C0))
    38 #define EP7312_INTSR1  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0240))
    39 #define EP7312_INTMR1  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0280))
    40 #define EP7312_LCDCON  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x02C0))
    41 #define EP7312_TC1D    ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0300))
    42 #define EP7312_TC2D    ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0340))
    43 #define EP7312_RTCDR   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0380))
    44 #define EP7312_RTCMR   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x03C0))
    45 #define EP7312_PMPCON  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0400))
    46 #define EP7312_CODR    ((volatile unsigned8  *)(EP7312_REG_BASE + 0x0440))
    47 #define EP7312_UARTDR1 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0480))
    48 #define EP7312_UARTCR1 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x04C0))
    49 #define EP7312_SYNCIO  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0500))
    50 #define EP7312_PALLSW  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0540))
    51 #define EP7312_PALMSW  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0580))
    52 #define EP7312_STFCLR  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x05C0))
    53 #define EP7312_BLEOI   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0600))
    54 #define EP7312_MCEOI   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0640))
    55 #define EP7312_TEOI    ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0680))
    56 #define EP7312_TC1EOI  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x06C0))
    57 #define EP7312_TC2EOI  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0700))
    58 #define EP7312_RTCEOI  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0740))
    59 #define EP7312_UMSEOI  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0780))
    60 #define EP7312_COEOI   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x07C0))
    61 #define EP7312_HALT    ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0800))
    62 #define EP7312_STDBY   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x0840))
    63 #define EP7312_FBADDR  ((volatile unsigned8  *)(EP7312_REG_BASE + 0x1000))
    64 #define EP7312_SYSCON2 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1100))
    65 #define EP7312_SYSFLG2 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1140))
    66 #define EP7312_INTSR2  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1240))
    67 #define EP7312_INTMR2  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1280))
    68 #define EP7312_UARTDR2 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1480))
    69 #define EP7312_UARTCR2 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x14C0))
    70 #define EP7312_SS2DR   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1500))
    71 #define EP7312_SRXEOF  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1600))
    72 #define EP7312_SS2POP  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x16C0))
    73 #define EP7312_KBDEOI  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x1700))
    74 #define EP7312_DAIR    ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2000))
    75 #define EP7312_DAIDR0  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2040))
    76 #define EP7312_DAIDR1  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2080))
    77 #define EP7312_DAIDR2  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x20C0))
    78 #define EP7312_DAISR   ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2100))
    79 #define EP7312_SYSCON3 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2200))
    80 #define EP7312_INTSR3  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2240))
    81 #define EP7312_INTMR3  ((volatile unsigned8  *)(EP7312_REG_BASE + 0x2280))
    82 #define EP7312_LEDFLSH ((volatile unsigned8  *)(EP7312_REG_BASE + 0x22C0))
    83 #define EP7312_SDCONF  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2300))
    84 #define EP7312_SDRFPR  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2340))
    85 #define EP7312_UNIQID  ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2440))
    86 #define EP7312_DAI64Fs ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2600))
    87 #define EP7312_PLLW    ((volatile unsigned8  *)(EP7312_REG_BASE + 0x2610))
    88 #define EP7312_PLLR    ((volatile unsigned8  *)(EP7312_REG_BASE + 0xA5A8))
    89 #define EP7312_RANDID0 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2700))
    90 #define EP7312_RANDID1 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2704))
    91 #define EP7312_RANDID2 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x2708))
    92 #define EP7312_RANDID3 ((volatile unsigned32 *)(EP7312_REG_BASE + 0x270C))
     26#define EP7312_PADR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
     27#define EP7312_PBDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001))
     28#define EP7312_PDDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003))
     29#define EP7312_PADDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040))
     30#define EP7312_PBDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041))
     31#define EP7312_PDDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043))
     32#define EP7312_PEDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080))
     33#define EP7312_PEDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0))
     34#define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100))
     35#define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140))
     36#define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180))
     37#define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0))
     38#define EP7312_INTSR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240))
     39#define EP7312_INTMR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280))
     40#define EP7312_LCDCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0))
     41#define EP7312_TC1D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300))
     42#define EP7312_TC2D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340))
     43#define EP7312_RTCDR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380))
     44#define EP7312_RTCMR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0))
     45#define EP7312_PMPCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400))
     46#define EP7312_CODR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440))
     47#define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480))
     48#define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0))
     49#define EP7312_SYNCIO  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500))
     50#define EP7312_PALLSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540))
     51#define EP7312_PALMSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580))
     52#define EP7312_STFCLR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0))
     53#define EP7312_BLEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600))
     54#define EP7312_MCEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640))
     55#define EP7312_TEOI    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680))
     56#define EP7312_TC1EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0))
     57#define EP7312_TC2EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700))
     58#define EP7312_RTCEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740))
     59#define EP7312_UMSEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780))
     60#define EP7312_COEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0))
     61#define EP7312_HALT    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800))
     62#define EP7312_STDBY   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840))
     63#define EP7312_FBADDR  ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000))
     64#define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100))
     65#define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140))
     66#define EP7312_INTSR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240))
     67#define EP7312_INTMR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280))
     68#define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480))
     69#define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0))
     70#define EP7312_SS2DR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500))
     71#define EP7312_SRXEOF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600))
     72#define EP7312_SS2POP  ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0))
     73#define EP7312_KBDEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700))
     74#define EP7312_DAIR    ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000))
     75#define EP7312_DAIDR0  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040))
     76#define EP7312_DAIDR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080))
     77#define EP7312_DAIDR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0))
     78#define EP7312_DAISR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100))
     79#define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200))
     80#define EP7312_INTSR3  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240))
     81#define EP7312_INTMR3  ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280))
     82#define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0))
     83#define EP7312_SDCONF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300))
     84#define EP7312_SDRFPR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340))
     85#define EP7312_UNIQID  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440))
     86#define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600))
     87#define EP7312_PLLW    ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610))
     88#define EP7312_PLLR    ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8))
     89#define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700))
     90#define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704))
     91#define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708))
     92#define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C))
    9393
    9494/* serial port bits */
  • c/src/lib/libbsp/arm/edb7312/startup/bspstart.c

    r654c115c r2a7f710f  
    5252/*************************************************************/
    5353extern void rtems_irq_mngt_init(void);
    54 void bsp_libc_init( void *, unsigned32, int );
     54void bsp_libc_init( void *, uint32_t, int );
    5555void bsp_postdriver_hook(void);
    5656
     
    7676void bsp_pretasking_hook(void)
    7777{
    78     unsigned32 heap_start;
    79     unsigned32 heap_size;
     78    uint32_t  heap_start;
     79    uint32_t  heap_size;
    8080
    8181
     
    138138    BSP_Configuration.work_space_start = (void *)&_bss_free_start;
    139139   
    140     free_mem_start = ((unsigned32)&_bss_free_start +
     140    free_mem_start = ((uint32_t)&_bss_free_start +
    141141                      BSP_Configuration.work_space_size);
    142142   
    143     free_mem_end = ((unsigned32)&_sdram_base + (unsigned32)&_sdram_size);
     143    free_mem_end = ((uint32_t)&_sdram_base + (uint32_t)&_sdram_size);
    144144   
    145145    /*
  • c/src/lib/libbsp/arm/edb7312/timer/timer.c

    r654c115c r2a7f710f  
    2525#include <ep7312.h>
    2626
    27 rtems_unsigned16 tstart;
     27uint16_t        tstart;
    2828rtems_boolean Timer_driver_Find_average_overhead;
    2929
     
    5151int Read_timer( void )
    5252{
    53   rtems_unsigned16 t;
    54   rtems_unsigned32 total;
     53  uint16_t        t;
     54  uint32_t        total;
    5555  t = *EP7312_TC2D;
    5656
     
    6161   */
    6262
    63   total = (unsigned32)0x0000ffff - t;  /* result is 1/512000 = ~2 uS */
     63  total = (uint32_t)0x0000ffff - t;  /* result is 1/512000 = ~2 uS */
    6464  total = (total * 1953) / 1000;   /* convert to uS */
    6565  if ( Timer_driver_Find_average_overhead == 1 )
Note: See TracChangeset for help on using the changeset viewer.