Changeset 2a7f710f in rtems
- Timestamp:
- 03/31/04 04:14:40 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d89f13a
- Parents:
- 654c115c
- Location:
- c/src/lib/libbsp/arm/edb7312
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/edb7312/ChangeLog
r654c115c r2a7f710f 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * console/uart.c, include/ep7312.h, startup/bspstart.c, 4 timer/timer.c: Convert to using c99 fixed size types. 5 1 6 2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 7 -
c/src/lib/libbsp/arm/edb7312/console/uart.c
r654c115c r2a7f710f 57 57 8, /* ulHysteresis */ 58 58 NULL, /* pDeviceParams */ 59 (u nsigned32)EP7312_UARTCR1, /* ulCtrlPort1 */60 (u nsigned32)EP7312_SYSFLG1, /* ulCtrlPort2 */61 (u nsigned32)EP7312_UARTDR1, /* ulDataPort */59 (uint32_t)EP7312_UARTCR1, /* ulCtrlPort1 */ 60 (uint32_t)EP7312_SYSFLG1, /* ulCtrlPort2 */ 61 (uint32_t)EP7312_UARTDR1, /* ulDataPort */ 62 62 0, /* getRegister */ 63 63 0, /* setRegister */ … … 87 87 int uart_poll_read(int minor) 88 88 { 89 volatile u nsigned32*data_reg;90 volatile u nsigned32*ctrl_reg1;91 volatile u nsigned32*ctrl_reg2;89 volatile uint32_t *data_reg; 90 volatile uint32_t *ctrl_reg1; 91 volatile uint32_t *ctrl_reg2; 92 92 char c; 93 93 int err; 94 94 95 data_reg = (u nsigned32*)Console_Port_Tbl[minor].ulDataPort;96 ctrl_reg1 = (u nsigned32*)Console_Port_Tbl[minor].ulCtrlPort1;97 ctrl_reg2 = (u nsigned32*)Console_Port_Tbl[minor].ulCtrlPort2;95 data_reg = (uint32_t*)Console_Port_Tbl[minor].ulDataPort; 96 ctrl_reg1 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort1; 97 ctrl_reg2 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort2; 98 98 99 99 if ((*ctrl_reg2 & EP7312_UART_URXFE1) != 0) { … … 115 115 static int uart_write(int minor, const char *buf, int len) 116 116 { 117 volatile u nsigned32*data_reg;118 volatile u nsigned32*ctrl_reg1;119 volatile u nsigned32*ctrl_reg2;117 volatile uint32_t *data_reg; 118 volatile uint32_t *ctrl_reg1; 119 volatile uint32_t *ctrl_reg2; 120 120 int i; 121 121 char c; 122 122 123 data_reg = (u nsigned32*)Console_Port_Tbl[minor].ulDataPort;124 ctrl_reg1 = (u nsigned32*)Console_Port_Tbl[minor].ulCtrlPort1;125 ctrl_reg2 = (u nsigned32*)Console_Port_Tbl[minor].ulCtrlPort2;123 data_reg = (uint32_t*)Console_Port_Tbl[minor].ulDataPort; 124 ctrl_reg1 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort1; 125 ctrl_reg2 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort2; 126 126 127 127 for (i = 0; i < len; i++) { … … 140 140 static void uart_init(int minor) 141 141 { 142 volatile u nsigned32*data_reg;143 volatile u nsigned32*ctrl_reg1;144 volatile u nsigned32*ctrl_reg2;142 volatile uint32_t *data_reg; 143 volatile uint32_t *ctrl_reg1; 144 volatile uint32_t *ctrl_reg2; 145 145 146 data_reg = (u nsigned32*)Console_Port_Tbl[minor].ulDataPort;147 ctrl_reg1 = (u nsigned32*)Console_Port_Tbl[minor].ulCtrlPort1;148 ctrl_reg2 = (u nsigned32*)Console_Port_Tbl[minor].ulCtrlPort2;146 data_reg = (uint32_t*)Console_Port_Tbl[minor].ulDataPort; 147 ctrl_reg1 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort1; 148 ctrl_reg2 = (uint32_t*)Console_Port_Tbl[minor].ulCtrlPort2; 149 149 150 150 /* *ctrl_reg = (BSP_UART_DATA8 | -
c/src/lib/libbsp/arm/edb7312/include/ep7312.h
r654c115c r2a7f710f 24 24 #define EP7312_REG_BASE 0x80000000 25 25 26 #define EP7312_PADR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0000))27 #define EP7312_PBDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0001))28 #define EP7312_PDDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0003))29 #define EP7312_PADDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0040))30 #define EP7312_PBDDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0041))31 #define EP7312_PDDDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0043))32 #define EP7312_PEDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0080))33 #define EP7312_PEDDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x00C0))34 #define EP7312_SYSCON1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0100))35 #define EP7312_SYSFLG1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0140))36 #define EP7312_MEMCFG1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0180))37 #define EP7312_MEMCFG2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x01C0))38 #define EP7312_INTSR1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0240))39 #define EP7312_INTMR1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0280))40 #define EP7312_LCDCON ((volatile u nsigned32*)(EP7312_REG_BASE + 0x02C0))41 #define EP7312_TC1D ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0300))42 #define EP7312_TC2D ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0340))43 #define EP7312_RTCDR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0380))44 #define EP7312_RTCMR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x03C0))45 #define EP7312_PMPCON ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0400))46 #define EP7312_CODR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x0440))47 #define EP7312_UARTDR1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0480))48 #define EP7312_UARTCR1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x04C0))49 #define EP7312_SYNCIO ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0500))50 #define EP7312_PALLSW ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0540))51 #define EP7312_PALMSW ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0580))52 #define EP7312_STFCLR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x05C0))53 #define EP7312_BLEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0600))54 #define EP7312_MCEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0640))55 #define EP7312_TEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0680))56 #define EP7312_TC1EOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x06C0))57 #define EP7312_TC2EOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0700))58 #define EP7312_RTCEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0740))59 #define EP7312_UMSEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0780))60 #define EP7312_COEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x07C0))61 #define EP7312_HALT ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0800))62 #define EP7312_STDBY ((volatile u nsigned32*)(EP7312_REG_BASE + 0x0840))63 #define EP7312_FBADDR ((volatile u nsigned8*)(EP7312_REG_BASE + 0x1000))64 #define EP7312_SYSCON2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1100))65 #define EP7312_SYSFLG2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1140))66 #define EP7312_INTSR2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1240))67 #define EP7312_INTMR2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1280))68 #define EP7312_UARTDR2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1480))69 #define EP7312_UARTCR2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x14C0))70 #define EP7312_SS2DR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1500))71 #define EP7312_SRXEOF ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1600))72 #define EP7312_SS2POP ((volatile u nsigned32*)(EP7312_REG_BASE + 0x16C0))73 #define EP7312_KBDEOI ((volatile u nsigned32*)(EP7312_REG_BASE + 0x1700))74 #define EP7312_DAIR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2000))75 #define EP7312_DAIDR0 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2040))76 #define EP7312_DAIDR1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2080))77 #define EP7312_DAIDR2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x20C0))78 #define EP7312_DAISR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2100))79 #define EP7312_SYSCON3 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2200))80 #define EP7312_INTSR3 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2240))81 #define EP7312_INTMR3 ((volatile u nsigned8*)(EP7312_REG_BASE + 0x2280))82 #define EP7312_LEDFLSH ((volatile u nsigned8*)(EP7312_REG_BASE + 0x22C0))83 #define EP7312_SDCONF ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2300))84 #define EP7312_SDRFPR ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2340))85 #define EP7312_UNIQID ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2440))86 #define EP7312_DAI64Fs ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2600))87 #define EP7312_PLLW ((volatile u nsigned8*)(EP7312_REG_BASE + 0x2610))88 #define EP7312_PLLR ((volatile u nsigned8*)(EP7312_REG_BASE + 0xA5A8))89 #define EP7312_RANDID0 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2700))90 #define EP7312_RANDID1 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2704))91 #define EP7312_RANDID2 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x2708))92 #define EP7312_RANDID3 ((volatile u nsigned32*)(EP7312_REG_BASE + 0x270C))26 #define EP7312_PADR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000)) 27 #define EP7312_PBDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001)) 28 #define EP7312_PDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003)) 29 #define EP7312_PADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040)) 30 #define EP7312_PBDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041)) 31 #define EP7312_PDDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043)) 32 #define EP7312_PEDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080)) 33 #define EP7312_PEDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0)) 34 #define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100)) 35 #define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140)) 36 #define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180)) 37 #define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0)) 38 #define EP7312_INTSR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240)) 39 #define EP7312_INTMR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280)) 40 #define EP7312_LCDCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0)) 41 #define EP7312_TC1D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300)) 42 #define EP7312_TC2D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340)) 43 #define EP7312_RTCDR ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380)) 44 #define EP7312_RTCMR ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0)) 45 #define EP7312_PMPCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400)) 46 #define EP7312_CODR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440)) 47 #define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480)) 48 #define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0)) 49 #define EP7312_SYNCIO ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500)) 50 #define EP7312_PALLSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540)) 51 #define EP7312_PALMSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580)) 52 #define EP7312_STFCLR ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0)) 53 #define EP7312_BLEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600)) 54 #define EP7312_MCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640)) 55 #define EP7312_TEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680)) 56 #define EP7312_TC1EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0)) 57 #define EP7312_TC2EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700)) 58 #define EP7312_RTCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740)) 59 #define EP7312_UMSEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780)) 60 #define EP7312_COEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0)) 61 #define EP7312_HALT ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800)) 62 #define EP7312_STDBY ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840)) 63 #define EP7312_FBADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000)) 64 #define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100)) 65 #define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140)) 66 #define EP7312_INTSR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240)) 67 #define EP7312_INTMR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280)) 68 #define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480)) 69 #define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0)) 70 #define EP7312_SS2DR ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500)) 71 #define EP7312_SRXEOF ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600)) 72 #define EP7312_SS2POP ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0)) 73 #define EP7312_KBDEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700)) 74 #define EP7312_DAIR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000)) 75 #define EP7312_DAIDR0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040)) 76 #define EP7312_DAIDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080)) 77 #define EP7312_DAIDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0)) 78 #define EP7312_DAISR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100)) 79 #define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200)) 80 #define EP7312_INTSR3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240)) 81 #define EP7312_INTMR3 ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280)) 82 #define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0)) 83 #define EP7312_SDCONF ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300)) 84 #define EP7312_SDRFPR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340)) 85 #define EP7312_UNIQID ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440)) 86 #define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600)) 87 #define EP7312_PLLW ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610)) 88 #define EP7312_PLLR ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8)) 89 #define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700)) 90 #define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704)) 91 #define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708)) 92 #define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C)) 93 93 94 94 /* serial port bits */ -
c/src/lib/libbsp/arm/edb7312/startup/bspstart.c
r654c115c r2a7f710f 52 52 /*************************************************************/ 53 53 extern void rtems_irq_mngt_init(void); 54 void bsp_libc_init( void *, u nsigned32, int );54 void bsp_libc_init( void *, uint32_t, int ); 55 55 void bsp_postdriver_hook(void); 56 56 … … 76 76 void bsp_pretasking_hook(void) 77 77 { 78 u nsigned32heap_start;79 u nsigned32heap_size;78 uint32_t heap_start; 79 uint32_t heap_size; 80 80 81 81 … … 138 138 BSP_Configuration.work_space_start = (void *)&_bss_free_start; 139 139 140 free_mem_start = ((u nsigned32)&_bss_free_start +140 free_mem_start = ((uint32_t)&_bss_free_start + 141 141 BSP_Configuration.work_space_size); 142 142 143 free_mem_end = ((u nsigned32)&_sdram_base + (unsigned32)&_sdram_size);143 free_mem_end = ((uint32_t)&_sdram_base + (uint32_t)&_sdram_size); 144 144 145 145 /* -
c/src/lib/libbsp/arm/edb7312/timer/timer.c
r654c115c r2a7f710f 25 25 #include <ep7312.h> 26 26 27 rtems_unsigned16tstart;27 uint16_t tstart; 28 28 rtems_boolean Timer_driver_Find_average_overhead; 29 29 … … 51 51 int Read_timer( void ) 52 52 { 53 rtems_unsigned16t;54 rtems_unsigned32total;53 uint16_t t; 54 uint32_t total; 55 55 t = *EP7312_TC2D; 56 56 … … 61 61 */ 62 62 63 total = (u nsigned32)0x0000ffff - t; /* result is 1/512000 = ~2 uS */63 total = (uint32_t)0x0000ffff - t; /* result is 1/512000 = ~2 uS */ 64 64 total = (total * 1953) / 1000; /* convert to uS */ 65 65 if ( Timer_driver_Find_average_overhead == 1 )
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