Changeset 2a6ec317 in rtems


Ignore:
Timestamp:
Oct 1, 2012, 1:22:52 PM (7 years ago)
Author:
Peter Dufault <dufault@…>
Branches:
4.11, master
Children:
6527d87
Parents:
967481a0
git-author:
Peter Dufault <dufault@…> (10/01/12 13:22:52)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/02/12 13:27:34)
Message:

bsp/mpc55xx: PR2077: Mapping for external flash

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c

    r967481a0 r2a6ec317  
    3131  MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
    3232#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
    33     /* XXX I'm not using TLB1 entry 2 the same way as
    34          * in the BAM.
    35      */
    36     /*  Set up MMU TLB1 entry 2 for external ram. */
    37     /*  Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */
    38     /*       Real Base address = 0x2100_0000 XXX NOT LIKE BAM */
    39     /*  Page Size            6 =  4MB XXX Not like BAM */
    40     /*  Not Guarded, Cache Enable, All Access (0, 3F) */
    41     {
    42         { .R = 0x10020000},     /* MAS0 */
    43         { .R = 0xC0000600},     /* MAS1 */
    44         { .R = 0x21000000},     /* MAS2 */
    45         { .R = 0x2100003F}      /* MAS3 */
    46     },
    47 
    48     /*  Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */
    49     /*  Effective Base address = 0x2140_0000 */
    50     /*       Real Base address = 0x2140_0000 */
    51     /*  Page Size            6 = 4MB */
    52     /*  Not Guarded, Cache Enable, All Access (0, 3F) */
    53     {
    54         { .R =  0x10050000 },   /* MAS0 */
    55         { .R =  0xC0000600 },   /* MAS1 */
    56         { .R =  0x21400000 },   /* MAS2 */
    57         { .R =  0x2140003F }    /* MAS3 */
    58     },
    59     /*  Set up MMU TLB1 entry 6 for External LAN91C111 */
    60     /*  Effective Base address = 0x2200_0000 */
    61     /*       Real Base address = 0x2200_0000 */
    62     /*  Page Size            7 = 16MB */
    63     /*  Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
    64     {
    65         { .R = 0x10060000},     /* MAS0 */
    66         { .R = 0xC0000700},     /* MAS1 */
    67         { .R = 0x2200000E},     /* MAS2 */
    68         { .R = 0x2200003F}      /* MAS3 */
    69     },
    70 
    71     /*  Set up MMU TLB1 entry 7 for External FPGA */
    72     /*  Effective Base address = 0x2300_0000 */
    73     /*       Real Base address = 0x2300_0000 */
    74     /*  Page Size            7 = 16MB */
    75     /*  Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
    76     {
    77         { .R = 0x10070000},     /* MAS0 */
    78         { .R = 0xC0000700},     /* MAS1 */
    79         { .R = 0x2300000E},     /* MAS2 */
    80         { .R = 0x2300003F},     /* MAS3 */
    81     },
    82 
    83         /* Should also set up maps for the debug RAM and the
    84          * external flash.
    85          */
     33  /* Arguments macro:       idx,  addr,      size,              x, w, r, io */
     34  MPC55XX_MMU_TAG_INITIALIZER(8, 0x20000000, MPC55XX_MMU_8M,    1, 0, 1, 0), /* External FLASH 8M */
     35  MPC55XX_MMU_TAG_INITIALIZER(2, 0x21000000, MPC55XX_MMU_4M,    0, 1, 1, 0), /* Lower half SRAM */
     36  MPC55XX_MMU_TAG_INITIALIZER(5, 0x21400000, MPC55XX_MMU_4M,    1, 1, 1, 0), /* Upper half SRAM ("debug") */
     37  MPC55XX_MMU_TAG_INITIALIZER(6, 0x22000000, MPC55XX_MMU_16M,   0, 1, 1, 1), /* LAN91C111 */
     38  MPC55XX_MMU_TAG_INITIALIZER(7, 0x23000000, MPC55XX_MMU_16M,   0, 1, 1, 1), /* FPGA */
    8639#elif defined(MPC55XX_BOARD_MPC5566EVB)
    8740  /* Internal flash 3M */
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