Changeset 2a5880f1 in rtems


Ignore:
Timestamp:
08/10/11 15:00:53 (11 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
3848df4d
Parents:
45dabfd
Message:

2011-08-10 Sebastian Huber <sebastian.huber@…>

  • rtems/score/cpu.h: Removed superfluous comments. Format. Include by assembler support. Removed superfluous floating-point support. Stack alignment is now 4.
Location:
cpukit/score/cpu/nios2
Files:
2 edited

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  • cpukit/score/cpu/nios2/ChangeLog

    r45dabfd r2a5880f1  
     12011-08-10      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/score/cpu.h: Removed superfluous comments.  Format.  Include
     4        by assembler support. Removed superfluous floating-point support.
     5        Stack alignment is now 4.
     6
    172011-08-10      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    r45dabfd r2a5880f1  
    1 /**
    2  * @file rtems/score/cpu.h
    3  */
    4 
    5 /*
    6  *  This include file contains information pertaining to the XXX
    7  *  processor.
    8  *
    9  *  @note This file is part of a porting template that is intended
    10  *  to be used as the starting point when porting RTEMS to a new
    11  *  CPU family.  The following needs to be done when using this as
    12  *  the starting point for a new port:
    13  *
    14  *  + Anywhere there is an XXX, it should be replaced
    15  *    with information about the CPU family being ported to.
    16  *
    17  *  + At the end of each comment section, there is a heading which
    18  *    says "Port Specific Information:".  When porting to RTEMS,
    19  *    add CPU family specific information in this section
    20  */
    21 
    22 /*  COPYRIGHT (c) 1989-2004.
     1/*
     2 *  Copyright (c) 2011 embedded brains GmbH
     3 *
     4 *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
     5 *
     6 *  COPYRIGHT (c) 1989-2004.
    237 *  On-Line Applications Research Corporation (OAR).
    248 *
     
    4024#include <rtems/score/nios2.h>
    4125
    42 /* conditional compilation parameters */
    43 
    44 /**
    45  *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
    46  *
    47  *  If TRUE, then they are inlined.
    48  *  If FALSE, then a subroutine call is made.
    49  *
    50  *  This conditional is an example of the classic trade-off of size
    51  *  versus speed.  Inlining the call (TRUE) typically increases the
    52  *  size of RTEMS while speeding up the enabling of dispatching.
    53  *
    54  *  @note In general, the @ref _Thread_Dispatch_disable_level will
    55  *  only be 0 or 1 unless you are in an interrupt handler and that
    56  *  interrupt handler invokes the executive.]  When not inlined
    57  *  something calls @ref _Thread_Enable_dispatch which in turns calls
    58  *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
    59  *  one subroutine call is avoided entirely.
    60  *
    61  *  Port Specific Information:
    62  *
    63  *  XXX document implementation including references if appropriate
    64  */
    65 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
    66 
    67 /**
    68  *  Should the body of the search loops in _Thread_queue_Enqueue_priority
    69  *  be unrolled one time?  In unrolled each iteration of the loop examines
    70  *  two "nodes" on the chain being searched.  Otherwise, only one node
    71  *  is examined per iteration.
    72  *
    73  *  If TRUE, then the loops are unrolled.
    74  *  If FALSE, then the loops are not unrolled.
    75  *
    76  *  The primary factor in making this decision is the cost of disabling
    77  *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
    78  *  body of the loop.  On some CPUs, the flash is more expensive than
    79  *  one iteration of the loop body.  In this case, it might be desirable
    80  *  to unroll the loop.  It is important to note that on some CPUs, this
    81  *  code is the longest interrupt disable period in RTEMS.  So it is
    82  *  necessary to strike a balance when setting this parameter.
    83  *
    84  *  Port Specific Information:
    85  *
    86  *  XXX document implementation including references if appropriate
    87  */
    88 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
    89 
    90 /**
    91  *  Does RTEMS manage a dedicated interrupt stack in software?
    92  *
    93  *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
    94  *  If FALSE, nothing is done.
    95  *
    96  *  If the CPU supports a dedicated interrupt stack in hardware,
    97  *  then it is generally the responsibility of the BSP to allocate it
    98  *  and set it up.
    99  *
    100  *  If the CPU does not support a dedicated interrupt stack, then
    101  *  the porter has two options: (1) execute interrupts on the
    102  *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
    103  *  interrupt stack.
    104  *
    105  *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    106  *
    107  *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    108  *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    109  *  possible that both are FALSE for a particular CPU.  Although it
    110  *  is unclear what that would imply about the interrupt processing
    111  *  procedure on that CPU.
    112  *
    113  *  Port Specific Information:
    114  *
    115  *  XXX document implementation including references if appropriate
    116  */
     26/*
     27 * TODO: Run the timing tests and figure out what is better.
     28 */
     29#define CPU_INLINE_ENABLE_DISPATCH FALSE
     30
     31/*
     32 * TODO: Run the timing tests and figure out what is better.
     33 */
     34#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
     35
    11736#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    11837
    119 /**
    120  *  Does the CPU follow the simple vectored interrupt model?
    121  *
    122  *  If TRUE, then RTEMS allocates the vector table it internally manages.
    123  *  If FALSE, then the BSP is assumed to allocate and manage the vector
    124  *  table
    125  *
    126  *  Port Specific Information:
    127  *
    128  *  XXX document implementation including references if appropriate
    129  */
    13038#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
    13139
    132 /**
    133  *  Does this CPU have hardware support for a dedicated interrupt stack?
    134  *
    135  *  If TRUE, then it must be installed during initialization.
    136  *  If FALSE, then no installation is performed.
    137  *
    138  *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
    139  *
    140  *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
    141  *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
    142  *  possible that both are FALSE for a particular CPU.  Although it
    143  *  is unclear what that would imply about the interrupt processing
    144  *  procedure on that CPU.
    145  *
    146  *  Port Specific Information:
    147  *
    148  *  XXX document implementation including references if appropriate
    149  */
     40#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
     41
     42#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
     43
     44#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
     45
    15046#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    15147
    152 /**
    153  *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
    154  *
    155  *  If TRUE, then the memory is allocated during initialization.
    156  *  If FALSE, then the memory is allocated during initialization.
    157  *
    158  *  This should be TRUE is @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
    159  *  or @ref CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
    160  *
    161  *  Port Specific Information:
    162  *
    163  *  XXX document implementation including references if appropriate
    164  */
    16548#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
    16649
    167 /**
    168  *  Does the RTEMS invoke the user's ISR with the vector number and
    169  *  a pointer to the saved interrupt frame (1) or just the vector
    170  *  number (0)?
    171  *
    172  *  Port Specific Information:
    173  *
    174  *  XXX document implementation including references if appropriate
    175  */
    17650#define CPU_ISR_PASSES_FRAME_POINTER 1
    17751
    178 /**
    179  *  @def CPU_HARDWARE_FP
    180  *
    181  *  Does the CPU have hardware floating point?
    182  *
    183  *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is supported.
    184  *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is ignored.
    185  *
    186  *  If there is a FP coprocessor such as the i387 or mc68881, then
    187  *  the answer is TRUE.
    188  *
    189  *  It indicates whether or not this CPU model has FP support.  For
    190  *  example, it would be possible to have an i386_nofp CPU model
    191  *  which set this to false to indicate that you have an i386 without
    192  *  an i387 and wish to leave floating point support out of RTEMS.
    193  */
    194 
    195 /**
    196  *  @def CPU_SOFTWARE_FP
    197  *
    198  *  Does the CPU have no hardware floating point and GCC provides a
    199  *  software floating point implementation which must be context
    200  *  switched?
    201  *
    202  *  This feature conditional is used to indicate whether or not there
    203  *  is software implemented floating point that must be context
    204  *  switched.  The determination of whether or not this applies
    205  *  is very tool specific and the state saved/restored is also
    206  *  compiler specific.
    207  *
    208  *  Port Specific Information:
    209  *
    210  *  XXX document implementation including references if appropriate
    211  */
    212 #define CPU_HARDWARE_FP     FALSE
    213 #define CPU_SOFTWARE_FP     FALSE
    214 
    215 /**
    216  *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
    217  *
    218  *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is assumed.
    219  *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is followed.
    220  *
    221  *  So far, the only CPUs in which this option has been used are the
    222  *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
    223  *  gcc both implicitly used the floating point registers to perform
    224  *  integer multiplies.  Similarly, the PowerPC port of gcc has been
    225  *  seen to allocate floating point local variables and touch the FPU
    226  *  even when the flow through a subroutine (like vfprintf()) might
    227  *  not use floating point formats.
    228  *
    229  *  If a function which you would not think utilize the FP unit DOES,
    230  *  then one can not easily predict which tasks will use the FP hardware.
    231  *  In this case, this option should be TRUE.
    232  *
    233  *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
    234  *
    235  *  Port Specific Information:
    236  *
    237  *  XXX document implementation including references if appropriate
    238  */
    239 #define CPU_ALL_TASKS_ARE_FP     FALSE
    240 
    241 /**
    242  *  Should the IDLE task have a floating point context?
    243  *
    244  *  If TRUE, then the IDLE task is created as a @ref RTEMS_FLOATING_POINT task
    245  *  and it has a floating point context which is switched in and out.
    246  *  If FALSE, then the IDLE task does not have a floating point context.
    247  *
    248  *  Setting this to TRUE negatively impacts the time required to preempt
    249  *  the IDLE task from an interrupt because the floating point context
    250  *  must be saved as part of the preemption.
    251  *
    252  *  Port Specific Information:
    253  *
    254  *  XXX document implementation including references if appropriate
    255  */
    256 #define CPU_IDLE_TASK_IS_FP      FALSE
    257 
    258 /**
    259  *  Should the saving of the floating point registers be deferred
    260  *  until a context switch is made to another different floating point
    261  *  task?
    262  *
    263  *  If TRUE, then the floating point context will not be stored until
    264  *  necessary.  It will remain in the floating point registers and not
    265  *  disturned until another floating point task is switched to.
    266  *
    267  *  If FALSE, then the floating point context is saved when a floating
    268  *  point task is switched out and restored when the next floating point
    269  *  task is restored.  The state of the floating point registers between
    270  *  those two operations is not specified.
    271  *
    272  *  If the floating point context does NOT have to be saved as part of
    273  *  interrupt dispatching, then it should be safe to set this to TRUE.
    274  *
    275  *  Setting this flag to TRUE results in using a different algorithm
    276  *  for deciding when to save and restore the floating point context.
    277  *  The deferred FP switch algorithm minimizes the number of times
    278  *  the FP context is saved and restored.  The FP context is not saved
    279  *  until a context switch is made to another, different FP task.
    280  *  Thus in a system with only one FP task, the FP context will never
    281  *  be saved or restored.
    282  *
    283  *  Port Specific Information:
    284  *
    285  *  XXX document implementation including references if appropriate
    286  */
    287 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
    288 
    289 /**
    290  *  Does this port provide a CPU dependent IDLE task implementation?
    291  *
    292  *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
    293  *  must be provided and is the default IDLE thread body instead of
    294  *  @ref _CPU_Thread_Idle_body.
    295  *
    296  *  If FALSE, then use the generic IDLE thread body if the BSP does
    297  *  not provide one.
    298  *
    299  *  This is intended to allow for supporting processors which have
    300  *  a low power or idle mode.  When the IDLE thread is executed, then
    301  *  the CPU can be powered down.
    302  *
    303  *  The order of precedence for selecting the IDLE thread body is:
    304  *
    305  *    -#  BSP provided
    306  *    -#  CPU dependent (if provided)
    307  *    -#  generic (if no BSP and no CPU dependent)
    308  *
    309  *  Port Specific Information:
    310  *
    311  *  XXX document implementation including references if appropriate
    312  */
    313 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    314 
    315 /**
    316  *  Does the stack grow up (toward higher addresses) or down
    317  *  (toward lower addresses)?
    318  *
    319  *  If TRUE, then the grows upward.
    320  *  If FALSE, then the grows toward smaller addresses.
    321  *
    322  *  Port Specific Information:
    323  *
    324  *  XXX document implementation including references if appropriate
    325  */
    326 #define CPU_STACK_GROWS_UP               FALSE
    327 
    328 /**
    329  *  The following is the variable attribute used to force alignment
    330  *  of critical RTEMS structures.  On some processors it may make
    331  *  sense to have these aligned on tighter boundaries than
    332  *  the minimum requirements of the compiler in order to have as
    333  *  much of the critical data area as possible in a cache line.
    334  *
    335  *  The placement of this macro in the declaration of the variables
    336  *  is based on the syntactically requirements of the GNU C
    337  *  "__attribute__" extension.  For example with GNU C, use
    338  *  the following to force a structures to a 32 byte boundary.
    339  *
    340  *      __attribute__ ((aligned (32)))
    341  *
    342  *  @note Currently only the Priority Bit Map table uses this feature.
    343  *        To benefit from using this, the data must be heavily
    344  *        used so it will stay in the cache and used frequently enough
    345  *        in the executive to justify turning this on.
    346  *
    347  *  Port Specific Information:
    348  *
    349  *  XXX document implementation including references if appropriate
     52#define CPU_HARDWARE_FP FALSE
     53
     54#define CPU_SOFTWARE_FP FALSE
     55
     56#define CPU_CONTEXT_FP_SIZE 0
     57
     58#define CPU_ALL_TASKS_ARE_FP FALSE
     59
     60#define CPU_IDLE_TASK_IS_FP FALSE
     61
     62#define CPU_USE_DEFERRED_FP_SWITCH FALSE
     63
     64#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
     65
     66#define CPU_STACK_GROWS_UP FALSE
     67
     68/*
     69 * TODO: Run the timing tests and figure out if we profit from cache alignment.
    35070 */
    35171#define CPU_STRUCTURE_ALIGNMENT
    35272
    353 /**
    354  *  @defgroup CPUEndian Processor Dependent Endianness Support
    355  *
    356  *  This group assists in issues related to processor endianness.
    357  */
    358 
    359 /**
    360  *  @ingroup CPUEndian
    361  *  Define what is required to specify how the network to host conversion
    362  *  routines are handled.
    363  *
    364  *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
    365  *  same values.
    366  *
    367  *  @see CPU_LITTLE_ENDIAN
    368  *
    369  *  Port Specific Information:
    370  *
    371  *  XXX document implementation including references if appropriate
    372  */
    373 #define CPU_BIG_ENDIAN                           FALSE
    374 
    375 /**
    376  *  @ingroup CPUEndian
    377  *  Define what is required to specify how the network to host conversion
    378  *  routines are handled.
    379  *
    380  *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
    381  *  same values.
    382  *
    383  *  @see CPU_BIG_ENDIAN
    384  *
    385  *  Port Specific Information:
    386  *
    387  *  XXX document implementation including references if appropriate
    388  */
    389 #define CPU_LITTLE_ENDIAN                        TRUE
    390 
    391 /**
    392  *  @ingroup CPUInterrupt
    393  *  The following defines the number of bits actually used in the
    394  *  interrupt field of the task mode.  How those bits map to the
    395  *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
    396  *
    397  *  Port Specific Information:
    398  *
    399  *  XXX document implementation including references if appropriate
    400  */
    401 #define CPU_MODES_INTERRUPT_MASK   0x00000001
    402 
    403 /*
    404  *  Processor defined structures required for cpukit/score.
    405  *
    406  *  Port Specific Information:
    407  *
    408  *  XXX document implementation including references if appropriate
    409  */
    410 
    411 /* may need to put some structures here.  */
    412 
    413 /**
    414  * @defgroup CPUContext Processor Dependent Context Management
    415  *
    416  *  From the highest level viewpoint, there are 2 types of context to save.
    417  *
    418  *     -# Interrupt registers to save
    419  *     -# Task level registers to save
    420  *
    421  *  Since RTEMS handles integer and floating point contexts separately, this
    422  *  means we have the following 3 context items:
    423  *
    424  *     -# task level context stuff::  Context_Control
    425  *     -# floating point task stuff:: Context_Control_fp
    426  *     -# special interrupt level context :: CPU_Interrupt_frame
    427  *
    428  *  On some processors, it is cost-effective to save only the callee
    429  *  preserved registers during a task context switch.  This means
    430  *  that the ISR code needs to save those registers which do not
    431  *  persist across function calls.  It is not mandatory to make this
    432  *  distinctions between the caller/callee saves registers for the
    433  *  purpose of minimizing context saved during task switch and on interrupts.
    434  *  If the cost of saving extra registers is minimal, simplicity is the
    435  *  choice.  Save the same context on interrupt entry as for tasks in
    436  *  this case.
    437  *
    438  *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
    439  *  care should be used in designing the context area.
    440  *
    441  *  On some CPUs with hardware floating point support, the Context_Control_fp
    442  *  structure will not be used or it simply consist of an array of a
    443  *  fixed number of bytes.   This is done when the floating point context
    444  *  is dumped by a "FP save context" type instruction and the format
    445  *  is not really defined by the CPU.  In this case, there is no need
    446  *  to figure out the exact format -- only the size.  Of course, although
    447  *  this is enough information for RTEMS, it is probably not enough for
    448  *  a debugger such as gdb.  But that is another problem.
    449  *
    450  *  Port Specific Information:
    451  *
    452  *  XXX document implementation including references if appropriate
    453  */
     73#define CPU_BIG_ENDIAN FALSE
     74
     75#define CPU_LITTLE_ENDIAN TRUE
     76
     77#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
     78
     79/*
     80 * Alignment value according to "Nios II Processor Reference" chapter 7
     81 * "Application Binary Interface" section "Memory Alignment".
     82 */
     83#define CPU_ALIGNMENT 4
     84
     85#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
     86
     87#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
     88
     89#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
     90
     91#define CPU_MODES_INTERRUPT_MASK 0x1
     92
     93#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
     94
     95#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
     96
     97#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
     98
     99#ifndef ASM
    454100
    455101/**
     
    480126  (_context)->sp
    481127
    482 /**
    483  *  @ingroup CPUContext Management
    484  *  This defines the complete set of floating point registers that must
    485  *  be saved during any context switch from one thread to another.
    486  */
    487128typedef struct {
    488 } Context_Control_fp;
    489 
    490 /**
    491  *  @ingroup CPUContext Management
    492  *  This defines the set of integer and processor state registers that must
    493  *  be saved during an interrupt.  This set does not include any which are
    494  *  in @ref Context_Control.
    495  */
     129  uint32_t r1;
     130  uint32_t r2;
     131  uint32_t r3;
     132  uint32_t r4;
     133  uint32_t r5;
     134  uint32_t r6;
     135  uint32_t r7;
     136  uint32_t r8;
     137  uint32_t r9;
     138  uint32_t r10;
     139  uint32_t r11;
     140  uint32_t r12;
     141  uint32_t r13;
     142  uint32_t r14;
     143  uint32_t r15;
     144  uint32_t ra;
     145  uint32_t gp;
     146  uint32_t et;
     147  uint32_t ea;
     148} CPU_Interrupt_frame;
     149
    496150typedef struct {
    497     uint32_t r1;
    498     uint32_t r2;
    499     uint32_t r3;
    500     uint32_t r4;
    501     uint32_t r5;
    502     uint32_t r6;
    503     uint32_t r7;
    504     uint32_t r8;
    505     uint32_t r9;
    506     uint32_t r10;
    507     uint32_t r11;
    508     uint32_t r12;
    509     uint32_t r13;
    510     uint32_t r14;
    511     uint32_t r15;
    512     uint32_t ra;
    513     uint32_t gp;
    514     uint32_t et;
    515     uint32_t ea;
    516 } CPU_Interrupt_frame;
    517 
    518 /**
    519  *  @ingroup CPUContext Management
    520  *  This defines the set of integer and processor state registers that are
    521  *  saved during a software exception.
    522  */
    523 typedef struct {
    524     uint32_t r1;
    525     uint32_t r2;
    526     uint32_t r3;
    527     uint32_t r4;
    528     uint32_t r5;
    529     uint32_t r6;
    530     uint32_t r7;
    531     uint32_t r8;
    532     uint32_t r9;
    533     uint32_t r10;
    534     uint32_t r11;
    535     uint32_t r12;
    536     uint32_t r13;
    537     uint32_t r14;
    538     uint32_t r15;
    539     uint32_t r16;
    540     uint32_t r17;
    541     uint32_t r18;
    542     uint32_t r19;
    543     uint32_t r20;
    544     uint32_t r21;
    545     uint32_t r22;
    546     uint32_t r23;
    547     uint32_t gp;
    548     uint32_t fp;
    549     uint32_t sp;
    550     uint32_t ra;
    551     uint32_t et;
    552     uint32_t ea;
    553     uint32_t status;
    554     uint32_t ienable;
    555     uint32_t ipending;
     151  uint32_t r1;
     152  uint32_t r2;
     153  uint32_t r3;
     154  uint32_t r4;
     155  uint32_t r5;
     156  uint32_t r6;
     157  uint32_t r7;
     158  uint32_t r8;
     159  uint32_t r9;
     160  uint32_t r10;
     161  uint32_t r11;
     162  uint32_t r12;
     163  uint32_t r13;
     164  uint32_t r14;
     165  uint32_t r15;
     166  uint32_t r16;
     167  uint32_t r17;
     168  uint32_t r18;
     169  uint32_t r19;
     170  uint32_t r20;
     171  uint32_t r21;
     172  uint32_t r22;
     173  uint32_t r23;
     174  uint32_t gp;
     175  uint32_t fp;
     176  uint32_t sp;
     177  uint32_t ra;
     178  uint32_t et;
     179  uint32_t ea;
     180  uint32_t status;
     181  uint32_t ienable;
     182  uint32_t ipending;
    556183} CPU_Exception_frame;
    557184
    558 /**
    559  *  This variable is optional.  It is used on CPUs on which it is difficult
    560  *  to generate an "uninitialized" FP context.  It is filled in by
    561  *  @ref _CPU_Initialize and copied into the task's FP context area during
    562  *  @ref _CPU_Context_Initialize.
    563  *
    564  *  Port Specific Information:
    565  *
    566  *  XXX document implementation including references if appropriate
    567  */
    568 #if 0
    569 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    570 #endif
    571 
    572 /**
    573  *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
    574  *
    575  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    576  *  This stack is allocated by the Interrupt Manager and the switch
    577  *  is performed in @ref _ISR_Handler.  These variables contain pointers
    578  *  to the lowest and highest addresses in the chunk of memory allocated
    579  *  for the interrupt stack.  Since it is unknown whether the stack
    580  *  grows up or down (in general), this give the CPU dependent
    581  *  code the option of picking the version it wants to use.
    582  *
    583  *  @note These two variables are required if the macro
    584  *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    585  *
    586  *  Port Specific Information:
    587  *
    588  *  XXX document implementation including references if appropriate
    589  */
    590 
    591 /*
    592  *  Nothing prevents the porter from declaring more CPU specific variables.
    593  *
    594  *  Port Specific Information:
    595  *
    596  *  XXX document implementation including references if appropriate
    597  */
    598 
    599 /* XXX: if needed, put more variables here */
    600 
    601 /**
    602  *  @ingroup CPUContext
    603  *  The size of the floating point context area.  On some CPUs this
    604  *  will not be a "sizeof" because the format of the floating point
    605  *  area is not defined -- only the size is.  This is usually on
    606  *  CPUs with a "floating point save context" instruction.
    607  *
    608  *  Port Specific Information:
    609  *
    610  *  XXX document implementation including references if appropriate
    611  */
    612 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
    613 
    614 /**
    615  *  Amount of extra stack (above minimum stack size) required by
    616  *  MPCI receive server thread.  Remember that in a multiprocessor
    617  *  system this thread must exist and be able to process all directives.
    618  *
    619  *  Port Specific Information:
    620  *
    621  *  XXX document implementation including references if appropriate
    622  */
    623 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
    624 
    625 /**
    626  *  @ingroup CPUInterrupt
    627  *  This defines the number of entries in the @ref _ISR_Vector_table managed
    628  *  by RTEMS.
    629  *
    630  *  Port Specific Information:
    631  *
    632  *  XXX document implementation including references if appropriate
    633  */
    634 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
    635 
    636 /**
    637  *  @ingroup CPUInterrupt
    638  *  This defines the highest interrupt vector number for this port.
    639  */
    640 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
    641 
    642 /**
    643  *  @ingroup CPUInterrupt
    644  *  This is defined if the port has a special way to report the ISR nesting
    645  *  level.  Most ports maintain the variable @a _ISR_Nest_level.
    646  */
    647 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    648 
    649 /**
    650  *  @ingroup CPUContext
    651  *  Should be large enough to run all RTEMS tests.  This ensures
    652  *  that a "reasonable" small application should not have any problems.
    653  *
    654  *  Port Specific Information:
    655  *
    656  *  XXX document implementation including references if appropriate
    657  */
    658 #define CPU_STACK_MINIMUM_SIZE          (1024*4)
    659 /* kawk: was *4 */
    660 
    661 /**
    662  *  CPU's worst alignment requirement for data types on a byte boundary.  This
    663  *  alignment does not take into account the requirements for the stack.
    664  *
    665  *  Port Specific Information:
    666  *
    667  *  XXX document implementation including references if appropriate
    668  */
    669 #define CPU_ALIGNMENT              4
    670 
    671 /**
    672  *  This number corresponds to the byte alignment requirement for the
    673  *  heap handler.  This alignment requirement may be stricter than that
    674  *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
    675  *  common for the heap to follow the same alignment requirement as
    676  *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
    677  *  the heap, then this should be set to @ref CPU_ALIGNMENT.
    678  *
    679  *  @note  This does not have to be a power of 2 although it should be
    680  *         a multiple of 2 greater than or equal to 2.  The requirement
    681  *         to be a multiple of 2 is because the heap uses the least
    682  *         significant field of the front and back flags to indicate
    683  *         that a block is in use or free.  So you do not want any odd
    684  *         length blocks really putting length data in that bit.
    685  *
    686  *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
    687  *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
    688  *         elements allocated from the heap meet all restrictions.
    689  *
    690  *  Port Specific Information:
    691  *
    692  *  XXX document implementation including references if appropriate
    693  */
    694 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
    695 
    696 /**
    697  *  This number corresponds to the byte alignment requirement for memory
    698  *  buffers allocated by the partition manager.  This alignment requirement
    699  *  may be stricter than that for the data types alignment specified by
    700  *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
    701  *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
    702  *  strict enough for the partition, then this should be set to
    703  *  @ref CPU_ALIGNMENT.
    704  *
    705  *  @note  This does not have to be a power of 2.  It does have to
    706  *         be greater or equal to than @ref CPU_ALIGNMENT.
    707  *
    708  *  Port Specific Information:
    709  *
    710  *  XXX document implementation including references if appropriate
    711  */
    712 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
    713 
    714 /**
    715  *  This number corresponds to the byte alignment requirement for the
    716  *  stack.  This alignment requirement may be stricter than that for the
    717  *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
    718  *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
    719  *  set to 0.
    720  *
    721  *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
    722  *
    723  *  Port Specific Information:
    724  *
    725  *  XXX document implementation including references if appropriate
    726  */
    727 #define CPU_STACK_ALIGNMENT        0
    728 
    729 /*
    730  *  ISR handler macros
    731  */
    732 
    733 /**
    734  *  @ingroup CPUInterrupt
    735  *  Support routine to initialize the RTEMS vector table after it is allocated.
    736  *
    737  *  Port Specific Information:
    738  *
    739  *  XXX document implementation including references if appropriate
    740  */
    741185#define _CPU_Initialize_vectors()
    742186
    743 /**
    744  *  @ingroup CPUInterrupt
    745  *  Disable all interrupts for an RTEMS critical section.  The previous
    746  *  level is returned in @a _isr_cookie.
    747  *
    748  *  @param _isr_cookie (out) will contain the previous level cookie
    749  *
    750  *  Port Specific Information:
    751  *
    752  *  XXX document implementation including references if appropriate
    753  */
    754187#define _CPU_ISR_Disable( _isr_cookie ) \
    755   { \
    756     _isr_cookie = __builtin_rdctl(0); /* read status register */ \
    757     __builtin_wrctl(0, 0); /* write 0 to status register */ \
    758   }
    759 
    760 /**
    761  *  @ingroup CPUInterrupt
    762  *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
    763  *  This indicates the end of an RTEMS critical section.  The parameter
    764  *  @a _isr_cookie is not modified.
    765  *
    766  *  @param _isr_cookie (in) contain the previous level cookie
    767  *
    768  *  Port Specific Information:
    769  *
    770  *  XXX document implementation including references if appropriate
    771  */
    772 #define _CPU_ISR_Enable( _isr_cookie )  \
    773   { \
    774     __builtin_wrctl( 0, _isr_cookie ); \
    775   }
    776 
    777 /**
    778  *  @ingroup CPUInterrupt
    779  *  This temporarily restores the interrupt to @a _isr_cookie before immediately
    780  *  disabling them again.  This is used to divide long RTEMS critical
    781  *  sections into two or more parts.  The parameter @a _isr_cookie is not
    782  *  modified.
    783  *
    784  *  @param _isr_cookie (in) contain the previous level cookie
    785  *
    786  *  Port Specific Information:
    787  *
    788  *  XXX document implementation including references if appropriate
    789  */
     188  do { \
     189    _isr_cookie = __builtin_rdctl( 0 ); \
     190    __builtin_wrctl( 0, 0 ); \
     191  } while ( 0 )
     192
     193#define _CPU_ISR_Enable( _isr_cookie ) \
     194  do { \
     195    __builtin_wrctl( 0, (int) _isr_cookie ); \
     196  } while ( 0 )
     197
    790198#define _CPU_ISR_Flash( _isr_cookie ) \
    791   { \
    792     __builtin_wrctl( 0, _isr_cookie ); \
    793     /* TODO: Does NIOS2 get a chance to \
    794     process IRQ between these statements? */ \
     199  do { \
     200    __builtin_wrctl( 0, (int) _isr_cookie ); \
    795201    __builtin_wrctl( 0, 0 ); \
    796   }
    797 
    798 /**
    799  *  @ingroup CPUInterrupt
    800  *
    801  *  This routine and @ref _CPU_ISR_Get_level
    802  *  Map the interrupt level in task mode onto the hardware that the CPU
    803  *  actually provides.  Currently, interrupt levels which do not
    804  *  map onto the CPU in a generic fashion are undefined.  Someday,
    805  *  it would be nice if these were "mapped" by the application
    806  *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
    807  *  8 - 255 would be available for bsp/application specific meaning.
    808  *  This could be used to manage a programmable interrupt controller
    809  *  via the rtems_task_mode directive.
    810  *
    811  *  Port Specific Information:
    812  *
    813  *  XXX document implementation including references if appropriate
    814  */
     202  } while ( 0 )
     203
    815204#define _CPU_ISR_Set_level( new_level ) \
    816         _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 );
    817 
    818 /**
    819  *  @ingroup CPUInterrupt
    820  *  Return the current interrupt disable level for this task in
    821  *  the format used by the interrupt level portion of the task mode.
    822  *
    823  *  @note This routine usually must be implemented as a subroutine.
    824  *
    825  *  Port Specific Information:
    826  *
    827  *  XXX document implementation including references if appropriate
    828  */
    829 uint32_t   _CPU_ISR_Get_level( void );
    830 
    831 /* end of ISR handler macros */
    832 
    833 /* Context handler macros */
    834 
    835 /**
    836  *  @ingroup CPUContext
    837  *  Initialize the context to a state suitable for starting a
    838  *  task after a context restore operation.  Generally, this
    839  *  involves:
    840  *
    841  *     - setting a starting address
    842  *     - preparing the stack
    843  *     - preparing the stack and frame pointers
    844  *     - setting the proper interrupt level in the context
    845  *     - initializing the floating point context
    846  *
    847  *  This routine generally does not set any unnecessary register
    848  *  in the context.  The state of the "general data" registers is
    849  *  undefined at task start time.
    850  *
    851  *  @param _the_context (in) is the context structure to be initialized
    852  *  @param _stack_base (in) is the lowest physical address of this task's stack
    853  *  @param _size (in) is the size of this task's stack
    854  *  @param _isr (in) is the interrupt disable level
    855  *  @param _entry_point (in) is the thread's entry point.  This is
    856  *         always @a _Thread_Handler
    857  *  @param _is_fp (in) is TRUE if the thread is to be a floating
    858  *        point thread.  This is typically only used on CPUs where the
    859  *        FPU may be easily disabled by software such as on the SPARC
    860  *        where the PSR contains an enable FPU bit.
    861  *
    862  *  Port Specific Information:
    863  *
    864  *  XXX document implementation including references if appropriate
     205  _CPU_ISR_Enable( new_level == 0 ? 1 : 0 );
     206
     207uint32_t _CPU_ISR_Get_level( void );
     208
     209/*
     210 * FIXME: Evaluate interrupt level.
    865211 */
    866212#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    867213                                 _isr, _entry_point, _is_fp ) \
    868    do { \
    869      uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
    870      (_the_context)->fp = (void *)_stack; \
    871      (_the_context)->sp = (void *)_stack; \
    872      (_the_context)->ra = (void *)(_entry_point); \
    873      (_the_context)->status  = 0x1; /* IRQs enabled */ \
    874    } while ( 0 )
    875 
    876 /*
    877  *  This routine is responsible for somehow restarting the currently
    878  *  executing task.  If you are lucky, then all that is necessary
    879  *  is restoring the context.  Otherwise, there will need to be
    880  *  a special assembly routine which does something special in this
    881  *  case.  @ref _CPU_Context_Restore should work most of the time.  It will
    882  *  not work if restarting self conflicts with the stack frame
    883  *  assumptions of restoring a context.
    884  *
    885  *  Port Specific Information:
    886  *
    887  *  XXX document implementation including references if appropriate
    888  */
     214  do { \
     215    uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
     216    (_the_context)->fp = (void *)_stack; \
     217    (_the_context)->sp = (void *)_stack; \
     218    (_the_context)->ra = (void *)(_entry_point); \
     219    (_the_context)->status  = 0x1; /* IRQs enabled */ \
     220  } while ( 0 )
     221
    889222#define _CPU_Context_Restart_self( _the_context ) \
    890    _CPU_Context_restore( (_the_context) );
    891 
    892 /**
    893  *  @ingroup CPUContext
    894  *  The purpose of this macro is to allow the initial pointer into
    895  *  a floating point context area (used to save the floating point
    896  *  context) to be at an arbitrary place in the floating point
    897  *  context area.
    898  *
    899  *  This is necessary because some FP units are designed to have
    900  *  their context saved as a stack which grows into lower addresses.
    901  *  Other FP units can be saved by simply moving registers into offsets
    902  *  from the base of the context area.  Finally some FP units provide
    903  *  a "dump context" instruction which could fill in from high to low
    904  *  or low to high based on the whim of the CPU designers.
    905  *
    906  *  @param _base (in) is the lowest physical address of the floating point
    907  *         context area
    908  *  @param _offset (in) is the offset into the floating point area
    909  *
    910  *  Port Specific Information:
    911  *
    912  *  XXX document implementation including references if appropriate
    913  */
    914 #if 1
    915 #define _CPU_Context_Fp_start( _base, _offset )
    916 #else
    917 #define _CPU_Context_Fp_start( _base, _offset ) \
    918    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
    919 #endif
    920 
    921 /**
    922  *  This routine initializes the FP context area passed to it to.
    923  *  There are a few standard ways in which to initialize the
    924  *  floating point context.  The code included for this macro assumes
    925  *  that this is a CPU in which a "initial" FP context was saved into
    926  *  @a _CPU_Null_fp_context and it simply copies it to the destination
    927  *  context passed to it.
    928  *
    929  *  Other floating point context save/restore models include:
    930  *    -# not doing anything, and
    931  *    -# putting a "null FP status word" in the correct place in the FP context.
    932  *
    933  *  @param _destination (in) is the floating point context area
    934  *
    935  *  Port Specific Information:
    936  *
    937  *  XXX document implementation including references if appropriate
    938  */
    939 #if 1
    940 #define _CPU_Context_Initialize_fp( _destination )
    941 #else
    942 #define _CPU_Context_Initialize_fp( _destination ) \
    943   { \
    944    *(*(_destination)) = _CPU_Null_fp_context; \
    945   }
    946 #endif
    947 
    948 /* end of Context handler macros */
    949 
    950 /* Fatal Error manager macros */
    951 
    952 /**
    953  *  This routine copies _error into a known place -- typically a stack
    954  *  location or a register, optionally disables interrupts, and
    955  *  halts/stops the CPU.
    956  *
    957  *  Port Specific Information:
    958  *
    959  *  XXX document implementation including references if appropriate
    960  */
     223  _CPU_Context_restore( (_the_context) );
     224
    961225#define _CPU_Fatal_halt( _error ) \
    962   { \
     226  do { \
    963227    __builtin_wrctl(0, 0); /* write 0 to status register (disable interrupts) */ \
    964228    __asm volatile ("mov et, %z0" : : "rM" (_error)); /* write error code to ET register */ \
    965     for(;;); \
    966   }
    967 
    968 /* end of Fatal Error manager macros */
    969 
    970 /* Bitfield handler macros */
    971 
    972 /**
    973  *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
    974  *
    975  *  This set of routines are used to implement fast searches for
    976  *  the most important ready task.
    977  */
    978 
    979 /**
    980  *  @ingroup CPUBitfield
    981  *  This definition is set to TRUE if the port uses the generic bitfield
    982  *  manipulation implementation.
    983  */
    984 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
    985 
    986 /**
    987  *  @ingroup CPUBitfield
    988  *  This definition is set to TRUE if the port uses the data tables provided
    989  *  by the generic bitfield manipulation implementation.
    990  *  This can occur when actually using the generic bitfield manipulation
    991  *  implementation or when implementing the same algorithm in assembly
    992  *  language for improved performance.  It is unlikely that a port will use
    993  *  the data if it has a bitfield scan instruction.
    994  */
    995 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
    996 
    997 /**
    998  *  @ingroup CPUBitfield
    999  *  This routine sets @a _output to the bit number of the first bit
    1000  *  set in @a _value.  @a _value is of CPU dependent type
    1001  *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
    1002  *  wide although only the 16 least significant bits will be used.
    1003  *
    1004  *  There are a number of variables in using a "find first bit" type
    1005  *  instruction.
    1006  *
    1007  *    -# What happens when run on a value of zero?
    1008  *    -# Bits may be numbered from MSB to LSB or vice-versa.
    1009  *    -# The numbering may be zero or one based.
    1010  *    -# The "find first bit" instruction may search from MSB or LSB.
    1011  *
    1012  *  RTEMS guarantees that (1) will never happen so it is not a concern.
    1013  *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
    1014  *  @ref _CPU_Priority_bits_index.  These three form a set of routines
    1015  *  which must logically operate together.  Bits in the _value are
    1016  *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
    1017  *  The basic major and minor values calculated by @ref _Priority_Major
    1018  *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
    1019  *  to properly range between the values returned by the "find first bit"
    1020  *  instruction.  This makes it possible for @ref _Priority_Get_highest to
    1021  *  calculate the major and directly index into the minor table.
    1022  *  This mapping is necessary to ensure that 0 (a high priority major/minor)
    1023  *  is the first bit found.
    1024  *
    1025  *  This entire "find first bit" and mapping process depends heavily
    1026  *  on the manner in which a priority is broken into a major and minor
    1027  *  components with the major being the 4 MSB of a priority and minor
    1028  *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
    1029  *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
    1030  *  to the lowest priority.
    1031  *
    1032  *  If your CPU does not have a "find first bit" instruction, then
    1033  *  there are ways to make do without it.  Here are a handful of ways
    1034  *  to implement this in software:
    1035  *
    1036 @verbatim
    1037       - a series of 16 bit test instructions
    1038       - a "binary search using if's"
    1039       - _number = 0
    1040         if _value > 0x00ff
    1041           _value >>=8
    1042           _number = 8;
    1043 
    1044         if _value > 0x0000f
    1045           _value >=8
    1046           _number += 4
    1047 
    1048         _number += bit_set_table[ _value ]
    1049 @endverbatim
    1050 
    1051  *    where bit_set_table[ 16 ] has values which indicate the first
    1052  *      bit set
    1053  *
    1054  *  @param _value (in) is the value to be scanned
    1055  *  @param _output (in) is the first bit set
    1056  *
    1057  *  Port Specific Information:
    1058  *
    1059  *  XXX document implementation including references if appropriate
    1060  */
    1061 
    1062 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    1063 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
    1064   { \
    1065     (_output) = 0;   /* do something to prevent warnings */ \
    1066   }
    1067 #endif
    1068 
    1069 /* end of Bitfield handler macros */
    1070 
    1071 /**
    1072  *  This routine builds the mask which corresponds to the bit fields
    1073  *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
    1074  *  for that routine.
    1075  *
    1076  *  Port Specific Information:
    1077  *
    1078  *  XXX document implementation including references if appropriate
    1079  */
    1080 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    1081 
    1082 #define _CPU_Priority_Mask( _bit_number ) \
    1083   ( 1 << (_bit_number) )
    1084 
    1085 #endif
    1086 
    1087 /**
    1088  *  @ingroup CPUBitfield
    1089  *  This routine translates the bit numbers returned by
    1090  *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
    1091  *  a major or minor component of a priority.  See the discussion
    1092  *  for that routine.
    1093  *
    1094  *  @param _priority (in) is the major or minor number to translate
    1095  *
    1096  *  Port Specific Information:
    1097  *
    1098  *  XXX document implementation including references if appropriate
    1099  */
    1100 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
    1101 
    1102 #define _CPU_Priority_bits_index( _priority ) \
    1103   (_priority)
    1104 
    1105 #endif
    1106 
    1107 /* end of Priority handler macros */
    1108 
    1109 /* functions */
    1110 
    1111 /**
    1112  *  This routine performs CPU dependent initialization.
    1113  *
    1114  *  Port Specific Information:
    1115  *
    1116  *  XXX document implementation including references if appropriate
    1117  */
    1118 void _CPU_Initialize(void);
    1119 
    1120 /**
    1121  *  @ingroup CPUInterrupt
    1122  *  This routine installs a "raw" interrupt handler directly into the
    1123  *  processor's vector table.
    1124  *
    1125  *  @param vector (in) is the vector number
    1126  *  @param new_handler (in) is the raw ISR handler to install
    1127  *  @param old_handler (in) is the previously installed ISR Handler
    1128  *
    1129  *  Port Specific Information:
    1130  *
    1131  *  XXX document implementation including references if appropriate
    1132  */
     229    for (;;); \
     230  } while ( 0 )
     231
     232void _CPU_Initialize( void );
     233
    1133234void _CPU_ISR_install_raw_handler(
    1134   uint32_t    vector,
    1135   proc_ptr    new_handler,
    1136   proc_ptr   *old_handler
     235  uint32_t vector,
     236  proc_ptr new_handler,
     237  proc_ptr *old_handler
    1137238);
    1138239
    1139 /**
    1140  *  @ingroup CPUInterrupt
    1141  *  This routine installs an interrupt vector.
    1142  *
    1143  *  @param vector (in) is the vector number
    1144  *  @param new_handler (in) is the RTEMS ISR handler to install
    1145  *  @param old_handler (in) is the previously installed ISR Handler
    1146  *
    1147  *  Port Specific Information:
    1148  *
    1149  *  XXX document implementation including references if appropriate
    1150  */
    1151240void _CPU_ISR_install_vector(
    1152   uint32_t    vector,
    1153   proc_ptr    new_handler,
    1154   proc_ptr   *old_handler
     241  uint32_t vector,
     242  proc_ptr new_handler,
     243  proc_ptr *old_handler
    1155244);
    1156245
    1157 /**
    1158  *  This routine is the CPU dependent IDLE thread body.
    1159  *
    1160  *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
    1161  *         is TRUE.
    1162  *
    1163  *  Port Specific Information:
    1164  *
    1165  *  XXX document implementation including references if appropriate
    1166  */
    1167 void *_CPU_Thread_Idle_body( uintptr_t ignored );
    1168 
    1169 /**
    1170  *  @ingroup CPUContext
    1171  *  This routine switches from the run context to the heir context.
    1172  *
    1173  *  @param run (in) points to the context of the currently executing task
    1174  *  @param heir (in) points to the context of the heir task
    1175  *
    1176  *  Port Specific Information:
    1177  *
    1178  *  XXX document implementation including references if appropriate
    1179  */
    1180 void _CPU_Context_switch(
    1181   Context_Control  *run,
    1182   Context_Control  *heir
    1183 );
    1184 
    1185 /**
    1186  *  @ingroup CPUContext
    1187  *  This routine is generally used only to restart self in an
    1188  *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
    1189  *
    1190  *  @param new_context (in) points to the context to be restored.
    1191  *
    1192  *  @note May be unnecessary to reload some registers.
    1193  *
    1194  *  Port Specific Information:
    1195  *
    1196  *  XXX document implementation including references if appropriate
    1197  */
     246void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
     247
    1198248void _CPU_Context_restore(
    1199249  Context_Control *new_context
    1200250) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
    1201251
    1202 /**
    1203  *  @ingroup CPUContext
    1204  *  This routine saves the floating point context passed to it.
    1205  *
    1206  *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
    1207  *  point context area
    1208  *
    1209  *  @return on output @a *fp_context_ptr will contain the address that
    1210  *  should be used with @ref _CPU_Context_restore_fp to restore this context.
    1211  *
    1212  *  Port Specific Information:
    1213  *
    1214  *  XXX document implementation including references if appropriate
    1215  */
    1216 void _CPU_Context_save_fp(
    1217   Context_Control_fp **fp_context_ptr
    1218 );
    1219 
    1220 /**
    1221  *  @ingroup CPUContext
    1222  *  This routine restores the floating point context passed to it.
    1223  *
    1224  *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
    1225  *  point context area to restore
    1226  *
    1227  *  @return on output @a *fp_context_ptr will contain the address that
    1228  *  should be used with @ref _CPU_Context_save_fp to save this context.
    1229  *
    1230  *  Port Specific Information:
    1231  *
    1232  *  XXX document implementation including references if appropriate
    1233  */
    1234 void _CPU_Context_restore_fp(
    1235   Context_Control_fp **fp_context_ptr
    1236 );
    1237 
    1238 /**
    1239  *  @ingroup CPUEndian
    1240  *  The following routine swaps the endian format of an unsigned int.
    1241  *  It must be static because it is referenced indirectly.
    1242  *
    1243  *  This version will work on any processor, but if there is a better
    1244  *  way for your CPU PLEASE use it.  The most common way to do this is to:
    1245  *
    1246  *     swap least significant two bytes with 16-bit rotate
    1247  *     swap upper and lower 16-bits
    1248  *     swap most significant two bytes with 16-bit rotate
    1249  *
    1250  *  Some CPUs have special instructions which swap a 32-bit quantity in
    1251  *  a single instruction (e.g. i486).  It is probably best to avoid
    1252  *  an "endian swapping control bit" in the CPU.  One good reason is
    1253  *  that interrupts would probably have to be disabled to insure that
    1254  *  an interrupt does not try to access the same "chunk" with the wrong
    1255  *  endian.  Another good reason is that on some CPUs, the endian bit
    1256  *  endianness for ALL fetches -- both code and data -- so the code
    1257  *  will be fetched incorrectly.
    1258  *
    1259  *  @param value (in) is the value to be swapped
    1260  *  @return the value after being endian swapped
    1261  *
    1262  *  Port Specific Information:
    1263  *
    1264  *  XXX document implementation including references if appropriate
    1265  */
    1266 static inline uint32_t CPU_swap_u32(
    1267   uint32_t value
    1268 )
     252static inline uint32_t CPU_swap_u32( uint32_t value )
    1269253{
    1270   uint32_t   byte1, byte2, byte3, byte4, swapped;
     254  uint32_t byte1, byte2, byte3, byte4, swapped;
    1271255
    1272256  byte4 = (value >> 24) & 0xff;
     
    1276260
    1277261  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    1278   return( swapped );
     262
     263  return swapped;
    1279264}
    1280265
    1281 /**
    1282  *  @ingroup CPUEndian
    1283  *  This routine swaps a 16 bir quantity.
    1284  *
    1285  *  @param value (in) is the value to be swapped
    1286  *  @return the value after being endian swapped
    1287  */
    1288266#define CPU_swap_u16( value ) \
    1289267  (((value&0xff) << 8) | ((value >> 8)&0xff))
     268
     269#endif /* ASM */
    1290270
    1291271#ifdef __cplusplus
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