Changeset 2a0a6851 in rtems
- Timestamp:
- 03/30/04 11:47:19 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- e6aeabd
- Parents:
- d86bae8
- Location:
- cpukit/score/cpu/sparc
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/sparc/ChangeLog
rd86bae8 r2a0a6851 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h, rtems/score/sparc.h: Convert to using 4 c99 fixed size types. 5 1 6 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 7 -
cpukit/score/cpu/sparc/cpu.c
rd86bae8 r2a0a6851 84 84 */ 85 85 86 u nsigned32_CPU_ISR_Get_level( void )87 { 88 u nsigned32level;86 uint32_t _CPU_ISR_Get_level( void ) 87 { 88 uint32_t level; 89 89 90 90 sparc_get_interrupt_level( level ); … … 132 132 133 133 void _CPU_ISR_install_raw_handler( 134 u nsigned32vector,134 uint32_t vector, 135 135 proc_ptr new_handler, 136 136 proc_ptr *old_handler 137 137 ) 138 138 { 139 u nsigned32real_vector;139 uint32_t real_vector; 140 140 CPU_Trap_table_entry *tbr; 141 141 CPU_Trap_table_entry *slot; 142 u nsigned32u32_tbr;143 u nsigned32u32_handler;142 uint32_t u32_tbr; 143 uint32_t u32_handler; 144 144 145 145 /* … … 188 188 *slot = _CPU_Trap_slot_template; 189 189 190 u32_handler = (u nsigned32) new_handler;190 u32_handler = (uint32_t ) new_handler; 191 191 192 192 slot->mov_vector_l3 |= vector; … … 219 219 220 220 void _CPU_ISR_install_vector( 221 u nsigned32vector,221 uint32_t vector, 222 222 proc_ptr new_handler, 223 223 proc_ptr *old_handler 224 224 ) 225 225 { 226 u nsigned32real_vector;226 uint32_t real_vector; 227 227 proc_ptr ignored; 228 228 … … 274 274 void _CPU_Context_Initialize( 275 275 Context_Control *the_context, 276 u nsigned32*stack_base,277 u nsigned32size,278 u nsigned32new_level,276 uint32_t *stack_base, 277 uint32_t size, 278 uint32_t new_level, 279 279 void *entry_point, 280 280 boolean is_fp 281 281 ) 282 282 { 283 u nsigned32stack_high; /* highest "stack aligned" address */284 u nsigned32the_size;285 u nsigned32tmp_psr;283 uint32_t stack_high; /* highest "stack aligned" address */ 284 uint32_t the_size; 285 uint32_t tmp_psr; 286 286 287 287 /* … … 290 290 */ 291 291 292 stack_high = ((u nsigned32)(stack_base) + size);292 stack_high = ((uint32_t )(stack_base) + size); 293 293 stack_high &= ~(CPU_STACK_ALIGNMENT - 1); 294 294 … … 299 299 */ 300 300 301 the_context->o7 = ((u nsigned32) entry_point) - 8;301 the_context->o7 = ((uint32_t ) entry_point) - 8; 302 302 the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; 303 303 the_context->i6_fp = stack_high; -
cpukit/score/cpu/sparc/rtems/score/cpu.h
rd86bae8 r2a0a6851 211 211 212 212 typedef struct { 213 u nsigned32l0;214 u nsigned32l1;215 u nsigned32l2;216 u nsigned32l3;217 u nsigned32l4;218 u nsigned32l5;219 u nsigned32l6;220 u nsigned32l7;221 u nsigned32i0;222 u nsigned32i1;223 u nsigned32i2;224 u nsigned32i3;225 u nsigned32i4;226 u nsigned32i5;227 u nsigned32i6_fp;228 u nsigned32i7;213 uint32_t l0; 214 uint32_t l1; 215 uint32_t l2; 216 uint32_t l3; 217 uint32_t l4; 218 uint32_t l5; 219 uint32_t l6; 220 uint32_t l7; 221 uint32_t i0; 222 uint32_t i1; 223 uint32_t i2; 224 uint32_t i3; 225 uint32_t i4; 226 uint32_t i5; 227 uint32_t i6_fp; 228 uint32_t i7; 229 229 void *structure_return_address; 230 230 /* … … 232 232 * should this be necessary. 233 233 */ 234 u nsigned32saved_arg0;235 u nsigned32saved_arg1;236 u nsigned32saved_arg2;237 u nsigned32saved_arg3;238 u nsigned32saved_arg4;239 u nsigned32saved_arg5;240 u nsigned32pad0;234 uint32_t saved_arg0; 235 uint32_t saved_arg1; 236 uint32_t saved_arg2; 237 uint32_t saved_arg3; 238 uint32_t saved_arg4; 239 uint32_t saved_arg5; 240 uint32_t pad0; 241 241 } CPU_Minimum_stack_frame; 242 242 … … 297 297 */ 298 298 double g0_g1; 299 u nsigned32g2;300 u nsigned32g3;301 u nsigned32g4;302 u nsigned32g5;303 u nsigned32g6;304 u nsigned32g7;305 306 u nsigned32l0;307 u nsigned32l1;308 u nsigned32l2;309 u nsigned32l3;310 u nsigned32l4;311 u nsigned32l5;312 u nsigned32l6;313 u nsigned32l7;314 315 u nsigned32i0;316 u nsigned32i1;317 u nsigned32i2;318 u nsigned32i3;319 u nsigned32i4;320 u nsigned32i5;321 u nsigned32i6_fp;322 u nsigned32i7;323 324 u nsigned32o0;325 u nsigned32o1;326 u nsigned32o2;327 u nsigned32o3;328 u nsigned32o4;329 u nsigned32o5;330 u nsigned32o6_sp;331 u nsigned32o7;332 333 u nsigned32psr;299 uint32_t g2; 300 uint32_t g3; 301 uint32_t g4; 302 uint32_t g5; 303 uint32_t g6; 304 uint32_t g7; 305 306 uint32_t l0; 307 uint32_t l1; 308 uint32_t l2; 309 uint32_t l3; 310 uint32_t l4; 311 uint32_t l5; 312 uint32_t l6; 313 uint32_t l7; 314 315 uint32_t i0; 316 uint32_t i1; 317 uint32_t i2; 318 uint32_t i3; 319 uint32_t i4; 320 uint32_t i5; 321 uint32_t i6_fp; 322 uint32_t i7; 323 324 uint32_t o0; 325 uint32_t o1; 326 uint32_t o2; 327 uint32_t o3; 328 uint32_t o4; 329 uint32_t o5; 330 uint32_t o6_sp; 331 uint32_t o7; 332 333 uint32_t psr; 334 334 } Context_Control; 335 335 … … 403 403 double f28_f29; 404 404 double f30_f31; 405 u nsigned32fsr;405 uint32_t fsr; 406 406 } Context_Control_fp; 407 407 … … 443 443 typedef struct { 444 444 CPU_Minimum_stack_frame Stack_frame; 445 u nsigned32psr;446 u nsigned32pc;447 u nsigned32npc;448 u nsigned32g1;449 u nsigned32g2;450 u nsigned32g3;451 u nsigned32g4;452 u nsigned32g5;453 u nsigned32g6;454 u nsigned32g7;455 u nsigned32i0;456 u nsigned32i1;457 u nsigned32i2;458 u nsigned32i3;459 u nsigned32i4;460 u nsigned32i5;461 u nsigned32i6_fp;462 u nsigned32i7;463 u nsigned32y;464 u nsigned32tpc;445 uint32_t psr; 446 uint32_t pc; 447 uint32_t npc; 448 uint32_t g1; 449 uint32_t g2; 450 uint32_t g3; 451 uint32_t g4; 452 uint32_t g5; 453 uint32_t g6; 454 uint32_t g7; 455 uint32_t i0; 456 uint32_t i1; 457 uint32_t i2; 458 uint32_t i3; 459 uint32_t i4; 460 uint32_t i5; 461 uint32_t i6_fp; 462 uint32_t i7; 463 uint32_t y; 464 uint32_t tpc; 465 465 } CPU_Interrupt_frame; 466 466 … … 507 507 void (*idle_task)( void ); 508 508 boolean do_zero_of_workspace; 509 u nsigned32idle_task_stack_size;510 u nsigned32interrupt_stack_size;511 u nsigned32extra_mpci_receive_server_stack;512 void * (*stack_allocate_hook)( u nsigned32);509 uint32_t idle_task_stack_size; 510 uint32_t interrupt_stack_size; 511 uint32_t extra_mpci_receive_server_stack; 512 void * (*stack_allocate_hook)( uint32_t ); 513 513 void (*stack_free_hook)( void* ); 514 514 /* end of fields required on all CPUs */ … … 561 561 562 562 typedef struct { 563 u nsigned32mov_psr_l0; /* mov %psr, %l0 */564 u nsigned32sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */565 u nsigned32jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */566 u nsigned32mov_vector_l3; /* mov _vector, %l3 */563 uint32_t mov_psr_l0; /* mov %psr, %l0 */ 564 uint32_t sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ 565 uint32_t jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ 566 uint32_t mov_vector_l3; /* mov _vector, %l3 */ 567 567 } CPU_Trap_table_entry; 568 568 … … 749 749 sparc_enable_interrupts( _newlevel << 8) 750 750 751 u nsigned32_CPU_ISR_Get_level( void );751 uint32_t _CPU_ISR_Get_level( void ); 752 752 753 753 /* end of ISR handler macros */ … … 771 771 void _CPU_Context_Initialize( 772 772 Context_Control *the_context, 773 u nsigned32*stack_base,774 u nsigned32size,775 u nsigned32new_level,773 uint32_t *stack_base, 774 uint32_t size, 775 uint32_t new_level, 776 776 void *entry_point, 777 777 boolean is_fp … … 824 824 #define _CPU_Fatal_halt( _error ) \ 825 825 do { \ 826 u nsigned32level; \826 uint32_t level; \ 827 827 \ 828 828 level = sparc_disable_interrupts(); \ … … 883 883 884 884 void _CPU_ISR_install_raw_handler( 885 u nsigned32vector,885 uint32_t vector, 886 886 proc_ptr new_handler, 887 887 proc_ptr *old_handler … … 895 895 896 896 void _CPU_ISR_install_vector( 897 u nsigned32vector,897 uint32_t vector, 898 898 proc_ptr new_handler, 899 899 proc_ptr *old_handler … … 978 978 ) 979 979 { 980 u nsigned32byte1, byte2, byte3, byte4, swapped;980 uint32_t byte1, byte2, byte3, byte4, swapped; 981 981 982 982 byte4 = (value >> 24) & 0xff; -
cpukit/score/cpu/sparc/rtems/score/sparc.h
rd86bae8 r2a0a6851 229 229 #define sparc_flash_interrupts( _level ) \ 230 230 do { \ 231 register u nsigned32_ignored = 0; \231 register uint32_t _ignored = 0; \ 232 232 \ 233 233 sparc_enable_interrupts( (_level) ); \ … … 238 238 #define sparc_set_interrupt_level( _new_level ) \ 239 239 do { \ 240 register u nsigned32_new_psr_level = 0; \240 register uint32_t _new_psr_level = 0; \ 241 241 \ 242 242 sparc_get_psr( _new_psr_level ); \ … … 250 250 #define sparc_get_interrupt_level( _level ) \ 251 251 do { \ 252 register u nsigned32_psr_level = 0; \252 register uint32_t _psr_level = 0; \ 253 253 \ 254 254 sparc_get_psr( _psr_level ); \
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