Changeset 29cc1477 in rtems


Ignore:
Timestamp:
Sep 30, 2008, 10:01:38 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
19e6dfa
Parents:
1196226
Message:

added SSP support files, fixed some typos

Location:
c/src/lib/libbsp/arm/lpc24xx
Files:
4 added
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/ChangeLog

    r1196226 r29cc1477  
     12008-09-30      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * ssp/ssp.c, misc/dma.c, include/dma.h, include/ssp.h: New files.
     4
     5        * Makefile.am, preinstall.am, README: Update.
     6
     7        * include/irq.h: Fixed typos.
     8
     9        * include/lpc24xx.h: New defines and types.  Converted to UNIX line
     10        endings.
     11
     12        * misc/system-clocks.c, startup/bspstart.c: Update for utility.h
     13        changes.
     14
    1152008-09-30      Ralf Corsépius <ralf.corsepius@rtems.org>
    216
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    r1196226 r29cc1477  
    33# @file
    44#
    5 # @brief Makefile of LibBSP for the LPC247X boards.
     5# @brief Makefile of LibBSP for the LPC24XX boards.
    66#
    77
     
    2323
    2424nodist_include_HEADERS = include/bspopts.h
     25
    2526nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
    26 DISTCLEANFILES = include/bspopts.h
    2727
    2828include_bsp_HEADERS = ../../shared/include/utility.h \
     
    3434        include/irq.h \
    3535        include/lpc24xx.h \
    36         include/system-clocks.h
     36        include/system-clocks.h \
     37        include/ssp.h \
     38        include/dma.h
    3739
    3840###############################################################################
     
    4143
    4244noinst_LIBRARIES = libbspstart.a
     45
    4346libbspstart_a_SOURCES = ../shared/start/start.S
     47
    4448project_lib_DATA = start.$(OBJEXT)
    4549
    46 dist_project_lib_DATA += ../shared/startup/linkcmds.base startup/linkcmds
     50dist_project_lib_DATA += ../shared/startup/linkcmds.base \
     51        startup/linkcmds
    4752
    4853###############################################################################
    4954#                  LibBSP                                                     #
    5055###############################################################################
     56
    5157noinst_LIBRARIES += libbsp.a
     58
    5259libbsp_a_SOURCES =
    5360
    54 # shared
     61# Shared
    5562libbsp_a_SOURCES += ../../shared/bootcard.c \
    5663        ../../shared/bspclean.c \
     
    6572        ../shared/abort/simple_abort.c
    6673
    67 # startup
     74# Startup
    6875libbsp_a_SOURCES += startup/bspstart.c
    6976
    70 # irq
     77# IRQ
    7178libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
    7279        ../../shared/src/irq-legacy.c \
     
    7481        irq/irq.c
    7582
    76 # console
     83# Console
    7784libbsp_a_SOURCES += ../../shared/console.c \
    7885        console/console-config.c
    7986
    80 # clock
    81 libbsp_a_SOURCES += clock/clock-config.c ../../../shared/clockdrv_shell.h
     87# Clock
     88libbsp_a_SOURCES += clock/clock-config.c \
     89        ../../../shared/clockdrv_shell.h
    8290
    83 # rtc
     91# RTC
    8492libbsp_a_SOURCES += ../../shared/tod.c \
    8593        rtc/rtc-config.c
    8694
    87 # misc
    88 libbsp_a_SOURCES += misc/system-clocks.c
     95# Misc
     96libbsp_a_SOURCES += misc/system-clocks.c \
     97        misc/dma.c
     98
     99# SSP
     100libbsp_a_SOURCES += ssp/ssp.c
    89101
    90102###############################################################################
     
    92104###############################################################################
    93105
    94 start.$(OBJEXT): ../shared/start/start.S
    95         $(CPPASCOMPILE) -o $@ -c $<
     106DISTCLEANFILES = include/bspopts.h
    96107
    97108include $(srcdir)/preinstall.am
  • c/src/lib/libbsp/arm/lpc24xx/README

    r1196226 r29cc1477  
    1111        o Clock
    1212        o RTC
     13        o SSP (SPI mode): This driver is in active development.  Use with care.
  • c/src/lib/libbsp/arm/lpc24xx/include/irq.h

    r1196226 r29cc1477  
    3636#define LPC24XX_IRQ_WDT 0
    3737#define LPC24XX_IRQ_SOFTWARE 1
    38 #define LPC24XX_IRQ_ARM CORE_0 2
    39 #define LPC24XX_IRQ_ARM CORE_1 3
     38#define LPC24XX_IRQ_ARM_CORE_0 2
     39#define LPC24XX_IRQ_ARM_CORE_1 3
    4040#define LPC24XX_IRQ_TIMER_0 4
    4141#define LPC24XX_IRQ_TIMER_1 5
     
    4444#define LPC24XX_IRQ_PWM 8
    4545#define LPC24XX_IRQ_I2C_0 9
    46 #define LPC24XX_IRQ_SPI_SSP0 10
    47 #define LPC24XX_IRQ_SSP1 11
     46#define LPC24XX_IRQ_SPI_SSP_0 10
     47#define LPC24XX_IRQ_SSP_1 11
    4848#define LPC24XX_IRQ_PLL 12
    4949#define LPC24XX_IRQ_RTC 13
     
    6262#define LPC24XX_IRQ_TIMER_2 26
    6363#define LPC24XX_IRQ_TIMER_3 27
    64 #define LPC24XX_IRQ_UART2 28
    65 #define LPC24XX_IRQ_UART3 29
     64#define LPC24XX_IRQ_UART_2 28
     65#define LPC24XX_IRQ_UART_3 29
    6666#define LPC24XX_IRQ_I2C_2 30
    6767#define LPC24XX_IRQ_I2S 31
     
    7777#define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
    7878
    79 #define BSP_FEATURE_IRQ_EXTENSION
    80 
    8179/** @} */
    8280
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    r1196226 r29cc1477  
    945945
    946946/* DMA channel 0 registers */
     947#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
    947948#define GPDMA_CH0_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
    948949#define GPDMA_CH0_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
     
    952953
    953954/* DMA channel 1 registers */
     955#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
    954956#define GPDMA_CH1_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
    955957#define GPDMA_CH1_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
     
    11221124/* Register Fields */
    11231125
     1126/* PCONP */
     1127
     1128#define PCONP_PCTIM0 0x00000002U
     1129
     1130#define PCONP_PCTIM1 0x00000004U
     1131
     1132#define PCONP_PCUART0 0x00000008U
     1133
     1134#define PCONP_PCUART1 0x00000010U
     1135
     1136#define PCONP_PCPWM0 0x00000020U
     1137
     1138#define PCONP_PCPWM1 0x00000040U
     1139
     1140#define PCONP_PCI2C0 0x00000080U
     1141
     1142#define PCONP_PCSPI 0x00000100U
     1143
     1144#define PCONP_PCRTC 0x00000200U
     1145
     1146#define PCONP_PCSSP1 0x00000400U
     1147
     1148#define PCONP_PCEMC 0x00000800U
     1149
     1150#define PCONP_PCAD 0x00001000U
     1151
     1152#define PCONP_PCCAN1 0x00002000U
     1153
     1154#define PCONP_PCCAN2 0x00004000U
     1155
     1156#define PCONP_PCI2C1 0x00080000U
     1157
     1158#define PCONP_PCLCD 0x00100000U
     1159
     1160#define PCONP_PCSSP0 0x00200000U
     1161
     1162#define PCONP_PCTIM2 0x00400000U
     1163
     1164#define PCONP_PCTIM3 0x00800000U
     1165
     1166#define PCONP_PCUART2 0x01000000U
     1167
     1168#define PCONP_PCUART3 0x02000000U
     1169
     1170#define PCONP_PCI2C2 0x04000000U
     1171
     1172#define PCONP_PCI2S 0x08000000U
     1173
     1174#define PCONP_PCSDC 0x10000000U
     1175
     1176#define PCONP_PCGPDMA 0x20000000U
     1177
     1178#define PCONP_PCENET 0x40000000U
     1179
     1180#define PCONP_PCUSB 0x80000000U
     1181
    11241182/* CLKSRCSEL */
    11251183
     
    11271185
    11281186#define GET_CLKSRCSEL_CLKSRC( reg) \
    1129   GET_REG_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
     1187  GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
    11301188
    11311189#define SET_CLKSRCSEL_CLKSRC( reg, val) \
    1132   SET_REG_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
     1190  SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
    11331191
    11341192/* PLLCON */
     
    11431201
    11441202#define GET_PLLCFG_MSEL( reg) \
    1145   GET_REG_FIELD( reg, PLLCFG_MSEL_MASK, 0)
     1203  GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
    11461204
    11471205#define SET_PLLCFG_MSEL( reg, val) \
    1148   SET_REG_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
     1206  SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
    11491207
    11501208#define PLLCFG_NSEL_MASK 0x00ff0000U
    11511209
    11521210#define GET_PLLCFG_NSEL( reg) \
    1153   GET_REG_FIELD( reg, PLLCFG_NSEL_MASK, 16)
     1211  GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
    11541212
    11551213#define SET_PLLCFG_NSEL( reg, val) \
    1156   SET_REG_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
     1214  SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
    11571215
    11581216/* PLLSTAT */
     
    11611219
    11621220#define GET_PLLSTAT_MSEL( reg) \
    1163   GET_REG_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
     1221  GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
    11641222
    11651223#define SET_PLLSTAT_MSEL( reg, val) \
    1166   SET_REG_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
     1224  SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
    11671225
    11681226#define PLLSTAT_NSEL_MASK 0x00ff0000U
    11691227
    11701228#define GET_PLLSTAT_NSEL( reg) \
    1171   GET_REG_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
     1229  GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
    11721230
    11731231#define SET_PLLSTAT_NSEL( reg, val) \
    1174   SET_REG_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
     1232  SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
    11751233
    11761234#define PLLSTAT_PLLE 0x01000000U
     
    11851243
    11861244#define GET_CCLKCFG_CCLKSEL( reg) \
    1187   GET_REG_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
     1245  GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
    11881246
    11891247#define SET_CCLKCFG_CCLKSEL( reg, val) \
    1190   SET_REG_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
     1248  SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
    11911249
    11921250/* MEMMAP */
     
    11951253
    11961254#define GET_MEMMAP_MAP( reg) \
    1197   GET_REG_FIELD( reg, MEMMAP_MAP_MASK, 0)
     1255  GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
    11981256
    11991257#define SET_MEMMAP_MAP( reg, val) \
    1200   SET_REG_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
     1258  SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
    12011259
    12021260/* TIR */
     
    12551313
    12561314#define GET_PCLKSEL0_PCLK_WDT( reg) \
    1257   GET_REG_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
     1315  GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
    12581316
    12591317#define SET_PCLKSEL0_PCLK_WDT( reg, val) \
    1260   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
     1318  SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
    12611319
    12621320#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
    12631321
    12641322#define GET_PCLKSEL0_PCLK_TIMER0( reg) \
    1265   GET_REG_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
     1323  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
    12661324
    12671325#define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
    1268   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
     1326  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
    12691327
    12701328#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
    12711329
    12721330#define GET_PCLKSEL0_PCLK_TIMER1( reg) \
    1273   GET_REG_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
     1331  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
    12741332
    12751333#define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
    1276   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
     1334  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
    12771335
    12781336#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
    12791337
    12801338#define GET_PCLKSEL0_PCLK_UART0( reg) \
    1281   GET_REG_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
     1339  GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
    12821340
    12831341#define SET_PCLKSEL0_PCLK_UART0( reg, val) \
    1284   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
     1342  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
    12851343
    12861344#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
    12871345
    12881346#define GET_PCLKSEL0_PCLK_UART1( reg) \
    1289   GET_REG_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
     1347  GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
    12901348
    12911349#define SET_PCLKSEL0_PCLK_UART1( reg, val) \
    1292   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
     1350  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
    12931351
    12941352#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
    12951353
    12961354#define GET_PCLKSEL0_PCLK_PWM0( reg) \
    1297   GET_REG_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
     1355  GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
    12981356
    12991357#define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
    1300   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
     1358  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
    13011359
    13021360#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
    13031361
    13041362#define GET_PCLKSEL0_PCLK_PWM1( reg) \
    1305   GET_REG_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
     1363  GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
    13061364
    13071365#define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
    1308   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
     1366  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
    13091367
    13101368#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
    13111369
    13121370#define GET_PCLKSEL0_PCLK_I2C0( reg) \
    1313   GET_REG_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
     1371  GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
    13141372
    13151373#define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
    1316   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
     1374  SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
    13171375
    13181376#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
    13191377
    13201378#define GET_PCLKSEL0_PCLK_SPI( reg) \
    1321   GET_REG_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
     1379  GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
    13221380
    13231381#define SET_PCLKSEL0_PCLK_SPI( reg, val) \
    1324   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
     1382  SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
    13251383
    13261384#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
    13271385
    13281386#define GET_PCLKSEL0_PCLK_RTC( reg) \
    1329   GET_REG_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
     1387  GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
    13301388
    13311389#define SET_PCLKSEL0_PCLK_RTC( reg, val) \
    1332   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
     1390  SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
    13331391
    13341392#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
    13351393
    13361394#define GET_PCLKSEL0_PCLK_SSP1( reg) \
    1337   GET_REG_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
     1395  GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
    13381396
    13391397#define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
    1340   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
     1398  SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
    13411399
    13421400#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
    13431401
    13441402#define GET_PCLKSEL0_PCLK_DAC( reg) \
    1345   GET_REG_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
     1403  GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
    13461404
    13471405#define SET_PCLKSEL0_PCLK_DAC( reg, val) \
    1348   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
     1406  SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
    13491407
    13501408#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
    13511409
    13521410#define GET_PCLKSEL0_PCLK_ADC( reg) \
    1353   GET_REG_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
     1411  GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
    13541412
    13551413#define SET_PCLKSEL0_PCLK_ADC( reg, val) \
    1356   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
     1414  SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
    13571415
    13581416#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
    13591417
    13601418#define GET_PCLKSEL0_PCLK_CAN1( reg) \
    1361   GET_REG_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
     1419  GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
    13621420
    13631421#define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
    1364   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
     1422  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
    13651423
    13661424#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
    13671425
    13681426#define GET_PCLKSEL0_PCLK_CAN2( reg) \
    1369   GET_REG_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
     1427  GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
    13701428
    13711429#define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
    1372   SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
     1430  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
    13731431
    13741432/* PCLKSEL1 */
     
    13771435
    13781436#define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
    1379   GET_REG_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
     1437  GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
    13801438
    13811439#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
    1382   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
     1440  SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
    13831441
    13841442#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
    13851443
    13861444#define GET_PCLKSEL1_PCLK_GPIO( reg) \
    1387   GET_REG_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
     1445  GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
    13881446
    13891447#define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
    1390   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
     1448  SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
    13911449
    13921450#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
    13931451
    13941452#define GET_PCLKSEL1_PCLK_PCB( reg) \
    1395   GET_REG_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
     1453  GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
    13961454
    13971455#define SET_PCLKSEL1_PCLK_PCB( reg, val) \
    1398   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
     1456  SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
    13991457
    14001458#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
    14011459
    14021460#define GET_PCLKSEL1_PCLK_I2C1( reg) \
    1403   GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
     1461  GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
    14041462
    14051463#define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
    1406   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
     1464  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
    14071465
    14081466#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
    14091467
    14101468#define GET_PCLKSEL1_PCLK_SSP0( reg) \
    1411   GET_REG_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
     1469  GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
    14121470
    14131471#define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
    1414   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
     1472  SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
    14151473
    14161474#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
    14171475
    14181476#define GET_PCLKSEL1_PCLK_TIMER2( reg) \
    1419   GET_REG_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
     1477  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
    14201478
    14211479#define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
    1422   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
     1480  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
    14231481
    14241482#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
    14251483
    14261484#define GET_PCLKSEL1_PCLK_TIMER3( reg) \
    1427   GET_REG_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
     1485  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
    14281486
    14291487#define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
    1430   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
     1488  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
    14311489
    14321490#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
    14331491
    14341492#define GET_PCLKSEL1_PCLK_UART2( reg) \
    1435   GET_REG_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
     1493  GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
    14361494
    14371495#define SET_PCLKSEL1_PCLK_UART2( reg, val) \
    1438   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
     1496  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
    14391497
    14401498#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
    14411499
    14421500#define GET_PCLKSEL1_PCLK_UART3( reg) \
    1443   GET_REG_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
     1501  GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
    14441502
    14451503#define SET_PCLKSEL1_PCLK_UART3( reg, val) \
    1446   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
     1504  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
    14471505
    14481506#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
    14491507
    14501508#define GET_PCLKSEL1_PCLK_I2C2( reg) \
    1451   GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
     1509  GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
    14521510
    14531511#define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
    1454   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
     1512  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
    14551513
    14561514#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
    14571515
    14581516#define GET_PCLKSEL1_PCLK_I2S( reg) \
    1459   GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
     1517  GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
    14601518
    14611519#define SET_PCLKSEL1_PCLK_I2S( reg, val) \
    1462   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
     1520  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
    14631521
    14641522#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
    14651523
    14661524#define GET_PCLKSEL1_PCLK_MCI( reg) \
    1467   GET_REG_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
     1525  GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
    14681526
    14691527#define SET_PCLKSEL1_PCLK_MCI( reg, val) \
    1470   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
     1528  SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
    14711529
    14721530#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
    14731531
    14741532#define GET_PCLKSEL1_PCLK_SYSCON( reg) \
    1475   GET_REG_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
     1533  GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
    14761534
    14771535#define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
    1478   SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
     1536  SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
    14791537
    14801538/* RTC_ILR */
     
    14941552#define RTC_CCR_CLKSRC 0x00000010U
    14951553
     1554/* SSP */
     1555
     1556typedef struct {
     1557  uint32_t cr0;
     1558  uint32_t cr1;
     1559  uint32_t dr;
     1560  uint32_t sr;
     1561  uint32_t cpsr;
     1562  uint32_t imsc;
     1563  uint32_t ris;
     1564  uint32_t mis;
     1565  uint32_t icr;
     1566  uint32_t dmacr;
     1567} lpc24xx_ssp;
     1568
     1569/* SSP_CR0 */
     1570
     1571#define SSP_CR0_DSS_MASK 0x0000000fU
     1572
     1573#define GET_SSP_CR0_DSS( reg) \
     1574  GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
     1575
     1576#define SET_SSP_CR0_DSS( reg, val) \
     1577  SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
     1578
     1579#define SSP_CR0_FRF_MASK 0x00000030U
     1580
     1581#define GET_SSP_CR0_FRF( reg) \
     1582  GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
     1583
     1584#define SET_SSP_CR0_FRF( reg, val) \
     1585  SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
     1586
     1587#define SSP_CR0_CPOL 0x00000040U
     1588
     1589#define SSP_CR0_CPHA 0x00000080U
     1590
     1591#define SSP_CR0_SCR_MASK 0x0000ff00U
     1592
     1593#define GET_SSP_CR0_SCR( reg) \
     1594  GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
     1595
     1596#define SET_SSP_CR0_SCR( reg, val) \
     1597  SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
     1598
     1599/* SSP_CR1 */
     1600
     1601#define SSP_CR1_LBM 0x00000001U
     1602
     1603#define SSP_CR1_SSE 0x00000002U
     1604
     1605#define SSP_CR1_MS 0x00000004U
     1606
     1607#define SSP_CR1_SOD 0x00000008U
     1608
     1609/* SSP_SR */
     1610
     1611#define SSP_SR_TFE 0x00000001U
     1612
     1613#define SSP_SR_TNF 0x00000002U
     1614
     1615#define SSP_SR_RNE 0x00000004U
     1616
     1617#define SSP_SR_RFF 0x00000008U
     1618
     1619#define SSP_SR_BSY 0x00000010U
     1620
     1621/* SSP_IMSC */
     1622
     1623#define SSP_IMSC_RORIM 0x00000001U
     1624
     1625#define SSP_IMSC_RTIM 0x00000002U
     1626
     1627#define SSP_IMSC_RXIM 0x00000004U
     1628
     1629#define SSP_IMSC_TXIM 0x00000008U
     1630
     1631/* SSP_RIS */
     1632
     1633#define SSP_RIS_RORRIS 0x00000001U
     1634
     1635#define SSP_RIS_RTRIS 0x00000002U
     1636
     1637#define SSP_RIS_RXRIS 0x00000004U
     1638
     1639#define SSP_RIS_TXRIS 0x00000008U
     1640
     1641/* SSP_MIS */
     1642
     1643#define SSP_MIS_RORRIS 0x00000001U
     1644
     1645#define SSP_MIS_RTRIS 0x00000002U
     1646
     1647#define SSP_MIS_RXRIS 0x00000004U
     1648
     1649#define SSP_MIS_TXRIS 0x00000008U
     1650
     1651/* SSP_ICR */
     1652
     1653#define SSP_ICR_RORRIS 0x00000001U
     1654
     1655#define SSP_ICR_RTRIS 0x00000002U
     1656
     1657#define SSP_ICR_RXRIS 0x00000004U
     1658
     1659#define SSP_ICR_TXRIS 0x00000008U
     1660
     1661/* SSP_DMACR */
     1662
     1663#define SSP_DMACR_RXDMAE 0x00000001U
     1664
     1665#define SSP_DMACR_TXDMAE 0x00000002U
     1666
     1667/* GPDMA */
     1668
     1669typedef struct {
     1670  uint32_t src;
     1671  uint32_t dest;
     1672  uint32_t lli;
     1673  uint32_t ctrl;
     1674  uint32_t cfg;
     1675} lpc24xx_dma_channel;
     1676
     1677#define GPDMA_CH_NUMBER 2
     1678
     1679#define GPDMA_STATUS_CH_0 0x00000001U
     1680
     1681#define GPDMA_STATUS_CH_1 0x00000002U
     1682
     1683#define GPDMA_CH_BASE_ADDR( i) \
     1684  ((volatile lpc24xx_dma_channel *) \
     1685    ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
     1686
     1687/* GPDMA_CONFIG */
     1688
     1689#define GPDMA_CONFIG_EN 0x00000001U
     1690
     1691#define GPDMA_CONFIG_MODE 0x00000002U
     1692
     1693/* GPDMA_ENABLED_CHNS */
     1694
     1695#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
     1696
     1697#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
     1698
     1699/* GPDMA_CH_CTRL */
     1700
     1701#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
     1702
     1703#define GET_GPDMA_CH_CTRL_TSZ( reg) \
     1704  GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
     1705
     1706#define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
     1707  SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
     1708
     1709#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
     1710
     1711#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
     1712
     1713#define GET_GPDMA_CH_CTRL_SBSZ( reg) \
     1714  GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
     1715
     1716#define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
     1717  SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
     1718
     1719#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
     1720
     1721#define GET_GPDMA_CH_CTRL_DBSZ( reg) \
     1722  GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
     1723
     1724#define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
     1725  SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
     1726
     1727#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
     1728
     1729#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
     1730
     1731#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
     1732
     1733#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
     1734
     1735#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
     1736
     1737#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
     1738
     1739#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
     1740
     1741#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
     1742
     1743#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
     1744
     1745#define GET_GPDMA_CH_CTRL_SW( reg) \
     1746  GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
     1747
     1748#define SET_GPDMA_CH_CTRL_SW( reg, val) \
     1749  SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
     1750
     1751#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
     1752
     1753#define GET_GPDMA_CH_CTRL_DW( reg) \
     1754  GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
     1755
     1756#define SET_GPDMA_CH_CTRL_DW( reg, val) \
     1757  SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
     1758
     1759#define GPDMA_CH_CTRL_W_8 0x00000000U
     1760
     1761#define GPDMA_CH_CTRL_W_16 0x00000001U
     1762
     1763#define GPDMA_CH_CTRL_W_32 0x00000002U
     1764
     1765#define GPDMA_CH_CTRL_SI 0x04000000U
     1766
     1767#define GPDMA_CH_CTRL_DI 0x08000000U
     1768
     1769#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
     1770
     1771#define GET_GPDMA_CH_CTRL_PROT( reg) \
     1772  GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
     1773
     1774#define SET_GPDMA_CH_CTRL_PROT( reg, val) \
     1775  SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
     1776
     1777#define GPDMA_CH_CTRL_ITC 0x80000000U
     1778
     1779/* GPDMA_CH_CFG */
     1780
     1781#define GPDMA_CH_CFG_EN 0x00000001U
     1782
     1783#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
     1784
     1785#define GET_GPDMA_CH_CFG_SRCPER( reg) \
     1786  GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
     1787
     1788#define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
     1789  SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
     1790
     1791#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
     1792
     1793#define GET_GPDMA_CH_CFG_DESTPER( reg) \
     1794  GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
     1795
     1796#define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
     1797  SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
     1798
     1799#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
     1800
     1801#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
     1802
     1803#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
     1804
     1805#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
     1806
     1807#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
     1808
     1809#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
     1810
     1811#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
     1812
     1813#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
     1814
     1815#define GET_GPDMA_CH_CFG_FLOW( reg) \
     1816  GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
     1817
     1818#define SET_GPDMA_CH_CFG_FLOW( reg, val) \
     1819  SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
     1820
     1821#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
     1822
     1823#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
     1824
     1825#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
     1826
     1827#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
     1828
     1829#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
     1830
     1831#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
     1832
     1833#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
     1834
     1835#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
     1836
     1837#define GPDMA_CH_CFG_IE 0x00004000U
     1838
     1839#define GPDMA_CH_CFG_ITC 0x00008000U
     1840
     1841#define GPDMA_CH_CFG_LOCK 0x00010000U
     1842
     1843#define GPDMA_CH_CFG_ACTIVE 0x00020000U
     1844
     1845#define GPDMA_CH_CFG_HALT 0x00040000U
     1846
     1847/* Ethernet (MAC) */
     1848
     1849typedef struct {
     1850  uint32_t start;
     1851  uint32_t control;
     1852} lpc24xx_eth_transfer_descriptor;
     1853
     1854typedef struct {
     1855  uint32_t status;
     1856  uint32_t hash_crc;
     1857} lpc24xx_eth_transfer_status;
     1858
     1859#define ETH_TRANSFER_DESCRIPTOR_SIZE 8
     1860
     1861#define ETH_TRANSFER_STATUS_SIZE 8
     1862
     1863#define ETH_TRANSFER_CTRL_SIZE \
     1864  (ETH_TRANSFER_DESCRIPTOR_SIZE + ETH_TRANSFER_STATUS_SIZE)
     1865
     1866/* ETH_RX_CTRL */
     1867
     1868#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
     1869
     1870#define GET_ETH_RX_CTRL_SIZE( reg) \
     1871  GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
     1872
     1873#define SET_ETH_RX_CTRL_SIZE( reg, val) \
     1874  SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
     1875
     1876#define ETH_RX_CTRL_INTERRUPT 0x80000000U
     1877
     1878/* ETH_RX_STAT */
     1879
     1880#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
     1881
     1882#define GET_ETH_RX_STAT_RXSIZE( reg) \
     1883  GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
     1884
     1885#define SET_ETH_RX_STAT_RXSIZE( reg, val) \
     1886  SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
     1887
     1888#define ETH_RX_STAT_BYTES 0x00000100U
     1889
     1890#define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
     1891
     1892#define ETH_RX_STAT_VLAN 0x00080000U
     1893
     1894#define ETH_RX_STAT_FAIL_FILTER 0x00100000U
     1895
     1896#define ETH_RX_STAT_MULTICAST 0x00200000U
     1897
     1898#define ETH_RX_STAT_BROADCAST 0x00400000U
     1899
     1900#define ETH_RX_STAT_CRC_ERROR 0x00800000U
     1901
     1902#define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
     1903
     1904#define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
     1905
     1906#define ETH_RX_STAT_RANGE_ERROR 0x04000000U
     1907
     1908#define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
     1909
     1910#define ETH_RX_STAT_OVERRUN 0x10000000U
     1911
     1912#define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
     1913
     1914#define ETH_RX_STAT_LAST_FLAG 0x40000000U
     1915
     1916#define ETH_RX_STAT_ERROR 0x80000000U
     1917
     1918/* ETH_TX_CTRL */
     1919
     1920#define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
     1921
     1922#define GET_ETH_TX_CTRL_SIZE( reg) \
     1923  GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
     1924
     1925#define SET_ETH_TX_CTRL_SIZE( reg, val) \
     1926  SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
     1927
     1928#define ETH_TX_CTRL_OVERRIDE 0x04000000U
     1929
     1930#define ETH_TX_CTRL_HUGE 0x08000000U
     1931
     1932#define ETH_TX_CTRL_PAD 0x10000000U
     1933
     1934#define ETH_TX_CTRL_CRC 0x20000000U
     1935
     1936#define ETH_TX_CTRL_LAST 0x40000000U
     1937
     1938#define ETH_TX_CTRL_INTERRUPT 0x80000000U
     1939
     1940/* ETH_TX_STAT */
     1941
     1942#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
     1943
     1944#define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
     1945  GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
     1946
     1947#define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
     1948  SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
     1949
     1950#define ETH_TX_STAT_DEFER 0x02000000U
     1951
     1952#define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
     1953
     1954#define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
     1955
     1956#define ETH_TX_STAT_LATE_COLLISION 0x10000000U
     1957
     1958#define ETH_TX_STAT_UNDERRUN 0x20000000U
     1959
     1960#define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
     1961
     1962#define ETH_TX_STAT_ERROR 0x80000000U
     1963
     1964/* ETH_INT */
     1965
     1966#define ETH_INT_RX_OVERRUN 0x00000001U
     1967
     1968#define ETH_INT_RX_ERROR 0x00000002U
     1969
     1970#define ETH_INT_RX_FINISHED 0x00000004U
     1971
     1972#define ETH_INT_RX_DONE 0x00000008U
     1973
     1974#define ETH_INT_TX_UNDERRUN 0x00000010U
     1975
     1976#define ETH_INT_TX_ERROR 0x00000020U
     1977
     1978#define ETH_INT_TX_FINISHED 0x00000040U
     1979
     1980#define ETH_INT_TX_DONE 0x00000080U
     1981
     1982#define ETH_INT_SOFT 0x00001000U
     1983
     1984#define ETH_INT_WAKEUP 0x00002000U
     1985
     1986/* ETH_RX_FIL_CTRL */
     1987
     1988#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
     1989
     1990#define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
     1991
     1992#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
     1993
     1994#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
     1995
     1996#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
     1997
     1998#define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
     1999
     2000#define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
     2001
     2002#define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
     2003
     2004/* ETH_CMD */
     2005
     2006#define ETH_CMD_RX_ENABLE 0x00000001U
     2007
     2008#define ETH_CMD_TX_ENABLE 0x00000002U
     2009
     2010#define ETH_CMD_REG_RESET 0x00000008U
     2011
     2012#define ETH_CMD_TX_RESET 0x00000010U
     2013
     2014#define ETH_CMD_RX_RESET 0x00000020U
     2015
     2016#define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
     2017
     2018#define ETH_CMD_PASS_RX_FILTER 0X00000080U
     2019
     2020#define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
     2021
     2022#define ETH_CMD_RMII 0x00000200U
     2023
     2024#define ETH_CMD_FULL_DUPLEX 0x00000400U
     2025
    14962026#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
  • c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c

    r1196226 r29cc1477  
    7272
    7373  /* Get PLL output frequency */
    74   if (REG_FLAG_IS_SET( PLLSTAT, PLLSTAT_PLLC)) {
     74  if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) {
    7575    uint32_t pllcfg = PLLCFG;
    7676    unsigned n = GET_PLLCFG_NSEL( pllcfg) + 1;
     
    111111void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cclksel)
    112112{
    113   bool pll_enabled = REG_FLAG_IS_SET( PLLSTAT, PLLSTAT_PLLE);
     113  bool pll_enabled = IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLE);
    114114
    115115  /* Disconnect PLL if necessary */
    116   if (REG_FLAG_IS_SET( PLLSTAT, PLLSTAT_PLLC)) {
     116  if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) {
    117117    if (pll_enabled) {
    118118      lpc24xx_pll_config( PLLCON_PLLE);
     
    140140
    141141  /* Wait for lock */
    142   while (REG_FLAG_IS_CLEARED( PLLSTAT, PLLSTAT_PLOCK)) {
     142  while (IS_FLAG_CLEARED( PLLSTAT, PLLSTAT_PLOCK)) {
    143143    /* Wait */
    144144  }
  • c/src/lib/libbsp/arm/lpc24xx/preinstall.am

    r1196226 r29cc1477  
    8686PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/system-clocks.h
    8787
     88$(PROJECT_INCLUDE)/bsp/ssp.h: include/ssp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     89        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ssp.h
     90PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ssp.h
     91
     92$(PROJECT_INCLUDE)/bsp/dma.h: include/dma.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     93        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/dma.h
     94PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/dma.h
     95
    8896$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    8997        $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c

    r1196226 r29cc1477  
    2323#include <bsp.h>
    2424#include <bsp/bootcard.h>
     25#include <bsp/dma.h>
    2526#include <bsp/irq.h>
    2627#include <bsp/linker-symbols.h>
     
    6263    }
    6364  }
     65
     66  /* DMA */
     67  lpc24xx_dma_initialize();
    6468}
    6569
    6670#define ULSR_THRE 0x00000020U
    6771
    68 static void my_BSP_output_char( char c)
     72static void lpc24xx_BSP_output_char( char c)
    6973{
    70   while (REG_FLAG_IS_CLEARED( U0LSR, ULSR_THRE)) {
     74  while (IS_FLAG_CLEARED( U0LSR, ULSR_THRE)) {
    7175    /* Wait */
    7276  }
     
    7478
    7579  if (c == '\n') {
    76     while (REG_FLAG_IS_CLEARED( U0LSR, ULSR_THRE)) {
     80    while (IS_FLAG_CLEARED( U0LSR, ULSR_THRE)) {
    7781      /* Wait */
    7882    }
     
    8185}
    8286
    83 BSP_output_char_function_type BSP_output_char = my_BSP_output_char;
     87BSP_output_char_function_type BSP_output_char = lpc24xx_BSP_output_char;
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