Changeset 293c0e3 in rtems for cpukit/score


Ignore:
Timestamp:
Mar 15, 2002, 7:47:36 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
5cf3f41
Parents:
5ab8aef
Message:

2002-03-13 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
  • rtems/score/cpu.h: Fixed register numbering in comments and made interrupt enable/disable more robust.
Location:
cpukit/score/cpu/mips
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/mips/ChangeLog

    r5ab8aef r293c0e3  
     12002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
     4        * rtems/score/cpu.h: Fixed register numbering in comments and made
     5        interrupt enable/disable more robust.
     6       
    172002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
    2 
    38        * cpu_asm.S: Added support for the debug exception vector, cleaned
    49        up the exception processing & exception return stuff.  Re-added
  • cpukit/score/cpu/mips/cpu_asm.S

    r5ab8aef r293c0e3  
    946946        li      t1,SR_EXL | SR_IE
    947947#elif __mips == 1
    948         li      t1,SR_IEC | SR_KUC      /* ints off, kernel mode on (kernel mode enabled is bit clear..argh!) */
     948        /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
     949        li      t1,SR_IEC | SR_KUP | SR_KUC     
    949950#endif
    950951        not     t1
    951952        and     t0, t1
     953
     954#if __mips == 1
     955        /* make sure previous int enable is on  because we're returning from an interrupt
     956        ** which means interrupts have to be enabled
     957        */
     958        li      t1,SR_IEP
     959        or      t0,t1
     960#endif
    952961        MTC0    t0, C0_SR
    953962        NOP
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r5ab8aef r293c0e3  
    554554  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
    555555  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
    556   /* end of __mips == 1 so NREGS == 80 */
     556  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
     557  /* end of __mips == 1 so NREGS == 81 */
    557558#if  __mips == 3
    558   __MIPS_REGISTER_TYPE  tlblo1;   /* 80 -- NOT FILLED IN */
    559   __MIPS_REGISTER_TYPE  pagemask; /* 81 -- NOT FILLED IN */
    560   __MIPS_REGISTER_TYPE  wired;    /* 82 -- NOT FILLED IN */
    561   __MIPS_REGISTER_TYPE  count;    /* 83 -- NOT FILLED IN */
    562   __MIPS_REGISTER_TYPE  compare;  /* 84 -- NOT FILLED IN */
    563   __MIPS_REGISTER_TYPE  config;   /* 85 -- NOT FILLED IN */
    564   __MIPS_REGISTER_TYPE  lladdr;   /* 86 -- NOT FILLED IN */
    565   __MIPS_REGISTER_TYPE  watchlo;  /* 87 -- NOT FILLED IN */
    566   __MIPS_REGISTER_TYPE  watchhi;  /* 88 -- NOT FILLED IN */
    567   __MIPS_REGISTER_TYPE  ecc;      /* 89 -- NOT FILLED IN */
    568   __MIPS_REGISTER_TYPE  cacheerr; /* 90 -- NOT FILLED IN */
    569   __MIPS_REGISTER_TYPE  taglo;    /* 91 -- NOT FILLED IN */
    570   __MIPS_REGISTER_TYPE  taghi;    /* 92 -- NOT FILLED IN */
    571   __MIPS_REGISTER_TYPE  errpc;    /* 93 -- NOT FILLED IN */
    572   __MIPS_REGISTER_TYPE  xctxt;    /* 94 -- NOT FILLED IN */
    573  /* end of __mips == 3 so NREGS == 95 */
     559  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
     560  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
     561  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
     562  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
     563  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
     564  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
     565  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
     566  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
     567  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
     568  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
     569  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
     570  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
     571  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
     572  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
     573  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
     574 /* end of __mips == 3 so NREGS == 96 */
    574575#endif
    575576
     
    756757#define _CPU_ISR_Disable( _level ) \
    757758  do { \
    758     mips_get_sr( _level ); \
    759     mips_set_sr( _level & ~SR_INTERRUPT_ENABLE_BITS ); \
    760     _level &= SR_INTERRUPT_ENABLE_BITS; \
     759    unsigned int _scratch; \
     760    mips_get_sr( _scratch ); \
     761    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
     762    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
    761763  } while(0)
    762764
     
    783785#define _CPU_ISR_Flash( _xlevel ) \
    784786  do { \
    785     _CPU_ISR_Enable( _xlevel ); \
    786     _CPU_ISR_Disable( _xlevel ); \
     787    unsigned int _scratch2 = _xlevel; \
     788    _CPU_ISR_Enable( _scratch2 ); \
     789    _CPU_ISR_Disable( _scratch2 ); \
     790    _xlevel = _scratch2; \
    787791  } while(0)
    788792
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