Changeset 287e4a8b in rtems


Ignore:
Timestamp:
Oct 29, 2009, 4:05:05 PM (10 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, master
Children:
429978f
Parents:
1fe3e3cf
Message:

2009-10-29 Till Straumann <strauman@…>

  • shared/irq/irq_asm.S: Beautification; ajusted margins and spaces to make the whole thing more readable.
Location:
c/src/lib/libbsp/i386
Files:
2 edited

Legend:

Unmodified
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Removed
  • c/src/lib/libbsp/i386/ChangeLog

    r1fe3e3cf r287e4a8b  
     12009-10-29      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * shared/irq/irq_asm.S: Beautification; ajusted margins and
     4        spaces to make the whole thing more readable.
     5
    162009-10-29      Till Straumann <strauman@slac.stanford.edu>
    27
  • c/src/lib/libbsp/i386/shared/irq/irq_asm.S

    r1fe3e3cf r287e4a8b  
    2020#endif
    2121
    22                BEGIN_CODE
     22        BEGIN_CODE
    2323
    2424SYM (_ISR_Handler):
    25        /*
    26         *  Before this was point is reached the vectors unique
    27         *  entry point did the following:
    28         *
    29         *     1. saved scratch registers registers eax edx ecx"
    30         *     2. put the vector number in ecx.
    31         *
    32         * BEGINNING OF ESTABLISH SEGMENTS
    33         *
    34         *  WARNING: If an interrupt can occur when the segments are
    35         *           not correct, then this is where we should establish
    36         *           the segments.  In addition to establishing the
    37         *           segments, it may be necessary to establish a stack
    38         *           in the current data area on the outermost interrupt.
    39         *
    40         *  NOTE:  If the previous values of the segment registers are
    41         *         pushed, do not forget to adjust SAVED_REGS.
    42         *
    43         *  NOTE:  Make sure the exit code which restores these
    44         *         when this type of code is needed.
    45         */
    46 
    47        /***** ESTABLISH SEGMENTS CODE GOES HERE  ******/
    48 
    49        /*
    50         * END OF ESTABLISH SEGMENTS
    51         */
    52 
    53         /*
    54         *  Now switch stacks if necessary
    55         */
    56 
    57         movw      SYM (i8259s_cache), ax /* move current i8259 interrupt mask in ax */
    58         pushl     eax                         /* push it on the stack */
     25        /*
     26        *  Before this was point is reached the vectors unique
     27        *  entry point did the following:
     28        *
     29        *     1. saved scratch registers registers eax edx ecx"
     30        *     2. put the vector number in ecx.
     31        *
     32        * BEGINNING OF ESTABLISH SEGMENTS
     33        *
     34        *  WARNING: If an interrupt can occur when the segments are
     35        *           not correct, then this is where we should establish
     36        *           the segments.  In addition to establishing the
     37        *           segments, it may be necessary to establish a stack
     38        *           in the current data area on the outermost interrupt.
     39        *
     40        *  NOTE:  If the previous values of the segment registers are
     41        *         pushed, do not forget to adjust SAVED_REGS.
     42        *
     43        *  NOTE:  Make sure the exit code which restores these
     44        *         when this type of code is needed.
     45        */
     46
     47        /***** ESTABLISH SEGMENTS CODE GOES HERE  ******/
     48
     49        /*
     50        * END OF ESTABLISH SEGMENTS
     51        */
     52
     53        /*
     54        *  Now switch stacks if necessary
     55        */
     56
     57        movw      SYM (i8259s_cache), ax /* move current i8259 interrupt mask in ax */
     58        pushl     eax                    /* push it on the stack */
    5959        /*
    6060         * compute the new PIC mask:
     
    6262         * <new mask> = <old mask> | irq_mask_or_tbl[<intr number aka ecx>]
    6363         */
    64         movw      SYM (irq_mask_or_tbl) (,ecx,2), dx
    65         orw       dx, ax
     64        movw      SYM (irq_mask_or_tbl) (,ecx,2), dx
     65        orw       dx, ax
    6666        /*
    6767         * Install new computed value on the i8259 and update cache
    6868         * accordingly
    6969         */
     70        movw      ax, SYM (i8259s_cache)
     71        outb      $PIC_MASTER_IMR_IO_PORT
     72        movb      ah, al
     73        outb      $PIC_SLAVE_IMR_IO_PORT
     74
     75        /*
     76         * acknowledge the interrupt
     77         *
     78         */
     79        movb      $PIC_EOI, al
     80        cmpl      $7, ecx
     81        jbe      .master
     82        outb      $PIC_SLAVE_COMMAND_IO_PORT
     83.master:
     84        outb      $PIC_MASTER_COMMAND_IO_PORT
     85
     86.check_stack_switch:
     87        pushl     ebp
     88        movl      esp, ebp                  /* ebp = previous stack pointer */
     89        cmpl      $0, SYM (_ISR_Nest_level) /* is this the outermost interrupt? */
     90        jne       nested                    /* No, then continue */
     91        movl      SYM (_CPU_Interrupt_stack_high), esp
     92
     93        /*
     94         *  We want to insure that the old stack pointer is on the
     95         *  stack we will be on at the end of the ISR when we restore it.
     96         *  By saving it on every interrupt, all we have to do is pop it
     97         *  near the end of every interrupt.
     98         */
     99
     100nested:
     101        incl      SYM (_ISR_Nest_level)     /* one nest level deeper */
     102        incl      SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
     103
     104        /*
     105     * Ensure CPU_STACK_ALIGNMENT for C-code.
     106     *  esp = (esp - 4) & ~(CPU_STACK_ALIGNMENT - 1)
     107         * makes sure 'esp' is aligned AND there is enough space
     108         * for the vector argument on the stack!
     109         */
     110        subl      $4, esp
     111
     112        andl      $ - CPU_STACK_ALIGNMENT, esp
     113        /*
     114         * re-enable interrupts at processor level as the current
     115         * interrupt source is now masked via i8259
     116         */
     117        sti
     118
     119    /*
     120         *  ECX is preloaded with the vector number but it is a scratch register
     121         *  so we must save it again.
     122         */
     123
     124        movl      ecx, (esp)  /* store vector arg in stack */
     125        call      C_dispatch_isr
     126
     127        /*
     128         * disable interrupts_again
     129         */
     130        cli
     131
     132        /*
     133         * restore stack
     134         */
     135        movl      ebp, esp
     136        popl      ebp
     137
     138        /*
     139         * restore the original i8259 masks
     140         */
     141        popl      eax
    70142        movw      ax, SYM (i8259s_cache)
    71143        outb      $PIC_MASTER_IMR_IO_PORT
     
    73145        outb      $PIC_SLAVE_IMR_IO_PORT
    74146
    75         /*
    76          * acknowledge the interrupt
    77          *
    78          */
    79         movb    $PIC_EOI, al
    80         cmpl    $7, ecx
    81         jbe     .master
    82         outb    $PIC_SLAVE_COMMAND_IO_PORT
    83 .master:
    84         outb    $PIC_MASTER_COMMAND_IO_PORT
    85 
    86 .check_stack_switch:
    87         pushl     ebp
    88         movl      esp, ebp                  /* ebp = previous stack pointer */
    89         cmpl      $0, SYM (_ISR_Nest_level) /* is this the outermost interrupt? */
    90         jne       nested                    /* No, then continue */
    91         movl      SYM (_CPU_Interrupt_stack_high), esp
    92 
    93         /*
    94          *  We want to insure that the old stack pointer is on the
    95          *  stack we will be on at the end of the ISR when we restore it.
    96          *  By saving it on every interrupt, all we have to do is pop it
    97          *  near the end of every interrupt.
    98          */
    99 
    100 nested:
    101         incl      SYM (_ISR_Nest_level)     /* one nest level deeper */
    102         incl      SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
    103 
    104         /*
    105      * Ensure CPU_STACK_ALIGNMENT for C-code.
    106      *  esp = (esp - 4) & ~(CPU_STACK_ALIGNMENT - 1)
    107          * makes sure 'esp' is aligned AND there is enough space
    108          * for the vector argument on the stack!
    109          */
    110         subl $4, esp
    111 
    112         andl $ - CPU_STACK_ALIGNMENT, esp
    113         /*
    114          * re-enable interrupts at processor level as the current
    115          * interrupt source is now masked via i8259
    116          */
    117         sti
    118 
    119     /*
    120          *  ECX is preloaded with the vector number but it is a scratch register
    121          *  so we must save it again.
    122          */
    123 
    124         movl ecx, (esp)  /* store vector arg in stack */
    125         call      C_dispatch_isr
    126 
    127         /*
    128          * disable interrupts_again
    129          */
    130         cli
    131 
    132         /*
    133          * restore stack
    134          */
    135         movl      ebp, esp
    136         popl      ebp
    137 
    138         /*
    139          * restore the original i8259 masks
    140          */
    141         popl      eax
    142         movw      ax, SYM (i8259s_cache)
    143         outb      $PIC_MASTER_IMR_IO_PORT
    144         movb      ah, al
    145         outb      $PIC_SLAVE_IMR_IO_PORT
    146 
    147         decl      SYM (_ISR_Nest_level)     /* one less ISR nest level */
    148                                             /* If interrupts are nested, */
    149                                             /*   then dispatching is disabled */
    150 
    151         decl      SYM (_Thread_Dispatch_disable_level)
    152                                             /* unnest multitasking */
    153                                             /* Is dispatch disabled */
    154         jne       .exit                     /* Yes, then exit */
    155 
    156         cmpb      $0, SYM (_Context_Switch_necessary)
    157                                             /* Is task switch necessary? */
    158         jne       .schedule                 /* Yes, then call the scheduler */
    159 
    160         cmpb      $0, SYM (_ISR_Signals_to_thread_executing)
    161                                             /* signals sent to Run_thread */
    162                                             /*   while in interrupt handler? */
    163         je        .exit                     /* No, exit */
     147        decl      SYM (_ISR_Nest_level)     /* one less ISR nest level */
     148                                            /* If interrupts are nested, */
     149                                            /*   then dispatching is disabled */
     150
     151        decl      SYM (_Thread_Dispatch_disable_level)
     152                                            /* unnest multitasking */
     153                                            /* Is dispatch disabled */
     154        jne       .exit                     /* Yes, then exit */
     155
     156        cmpb      $0, SYM (_Context_Switch_necessary)
     157                                            /* Is task switch necessary? */
     158        jne       .schedule                 /* Yes, then call the scheduler */
     159
     160        cmpb      $0, SYM (_ISR_Signals_to_thread_executing)
     161                                            /* signals sent to Run_thread */
     162                                            /*   while in interrupt handler? */
     163        je        .exit                     /* No, exit */
    164164
    165165.bframe:
    166         movb      $0, SYM (_ISR_Signals_to_thread_executing)
     166        movb      $0, SYM (_ISR_Signals_to_thread_executing)
    167167        /*
    168168         * This code is the less critical path. In order to have a single
     
    171171         * exception.
    172172         */
    173         call    _ThreadProcessSignalsFromIrq
    174 
    175         jmp .exit
     173        call      _ThreadProcessSignalsFromIrq
     174
     175        jmp       .exit
    176176
    177177.schedule:
     
    181181         * directly
    182182         */
    183         call _Thread_Dispatch
     183        call      _Thread_Dispatch
    184184        /*
    185185         * fall through exit to restore complete contex (scratch registers
     
    187187         */
    188188.exit:
    189        /*
    190         * BEGINNING OF DE-ESTABLISH SEGMENTS
    191         *
    192         *  NOTE:  Make sure there is code here if code is added to
    193         *         load the segment registers.
    194         *
    195         */
    196 
    197        /******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/
    198 
    199        /*
    200         * END OF DE-ESTABLISH SEGMENTS
    201         */
    202         popl    edx
    203         popl    ecx
    204         popl    eax
     189        /*
     190        * BEGINNING OF DE-ESTABLISH SEGMENTS
     191        *
     192        *  NOTE:  Make sure there is code here if code is added to
     193        *         load the segment registers.
     194        *
     195        */
     196
     197        /******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/
     198
     199        /*
     200        * END OF DE-ESTABLISH SEGMENTS
     201        */
     202        popl      edx
     203        popl      ecx
     204        popl      eax
    205205        iret
    206206
    207207#define DISTINCT_INTERRUPT_ENTRY(_vector) \
    208         .p2align 4                         ; \
    209         PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
     208        .p2align 4                         ; \
     209        PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
    210210SYM (rtems_irq_prologue_ ## _vector ):             \
    211         pushl   eax             ; \
    212         pushl   ecx             ; \
    213         pushl   edx             ; \
    214         movl    $ _vector, ecx  ; \
    215         jmp   SYM (_ISR_Handler) ;
     211        pushl     eax                ; \
     212        pushl     ecx                ; \
     213        pushl     edx                ; \
     214        movl      $ _vector, ecx     ; \
     215        jmp       SYM (_ISR_Handler) ;
    216216
    217217DISTINCT_INTERRUPT_ENTRY(0)
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