Changeset 2793778 in rtems


Ignore:
Timestamp:
Apr 19, 2013, 11:00:14 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
6c094da
Parents:
be04e62
git-author:
Sebastian Huber <sebastian.huber@…> (04/19/13 11:00:14)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/23/13 07:59:56)
Message:

bsp/mpc5200: Remove Erratum 342/339 comment

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/start/start.S

    rbe04e62 r2793778  
    516516
    517517#endif
    518         /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf:       */
    519         /* set 5 delays to their maximum to support two banks           */
    520 #if 0
    521         LWI     r30, 0xCC222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
    522 #else
    523         /* EB 04.12.08:
    524          * on MPC5200B, Erratum342 is no longer applicable.
    525          * on MPC5200_, Single Write2Read/Prec is only 3 bits,
    526          *     therefore the MSB of the set value (1100) was ignored
    527          * in the MPC5200B, this bit is implemented in results in
    528          *     SSSLLLOOOWWW access to SDRAM. To make the mem ctrl settings compatible with the MPC5200_,
    529          *     we use a 4 for now.
    530          */
    531518        LWI     r30, 0xC4222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
    532 #endif
    533519        stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
    534520                                                /* Refr.2No-Read delay=0x06, Write latency=0x0 */
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