Changeset 2764bd43 in rtems


Ignore:
Timestamp:
May 29, 2015, 1:54:27 PM (4 years ago)
Author:
Alexander Krutwig <alexander.krutwig@…>
Branches:
4.11, master
Children:
f9a2d36
Parents:
1f6cdba6
git-author:
Alexander Krutwig <alexander.krutwig@…> (05/29/15 13:54:27)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/30/15 14:46:36)
Message:

sparc: Disable FPU in interrupt context

Update #2270.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/irq_asm.S

    r1f6cdba6 r2764bd43  
    88 *  On-Line Applications Research Corporation (OAR).
    99 *
    10  *  Copyright (c) 2014 embedded brains GmbH
     10 *  Copyright (c) 2014-2015 embedded brains GmbH
    1111 *
    1212 *  The license and distribution terms for this file may be
     
    424424        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
    425425
     426#if SPARC_HAS_FPU == 1
     427        /*
     428         * We cannot use an intermediate value for operations with the PSR[EF]
     429         * bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
     430         */
     431        sethi    %hi(SPARC_PSR_EF_MASK), %l5
     432#endif
     433
    426434        /*
    427435         *  If ISR nest level was zero (now 1), then switch stack.
     
    441449
    442450        ld       [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
     451
     452#if SPARC_HAS_FPU == 1
     453        /*
     454         * Test if the interrupted thread uses the floating point unit
     455         * (PSR[EF] == 1).  In case it uses the floating point unit, then store
     456         * the floating point status register.  This has the side-effect that
     457         * all pending floating point operations complete before the store
     458         * completes.  The PSR[EF] bit is restored after the call to the
     459         * interrupt handler.  Thus post-switch actions (e.g. signal handlers)
     460         * and context switch extensions may still corrupt the floating point
     461         * context.
     462         */
     463        andcc    %l0, %l5, %g0
     464        bne,a    dont_switch_stacks
     465         st      %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
     466#endif
    443467
    444468dont_switch_stacks:
     
    472496        or       %g5, SPARC_PSR_PIL_MASK, %g5
    473497pil_fixed:
     498
     499#if SPARC_HAS_FPU == 1
     500        /*
     501         * Clear the PSR[EF] bit of the interrupted context to ensure that
     502         * interrupt service routines cannot corrupt the floating point context.
     503         */
     504        andn     %g5, %l5, %g5
     505#endif
     506
    474507        wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
    475508
  • cpukit/score/cpu/sparc/cpu.c

    r1f6cdba6 r2764bd43  
    2929  SPARC_PER_CPU_ISR_DISPATCH_DISABLE
    3030);
     31
     32#if SPARC_HAS_FPU == 1
     33  RTEMS_STATIC_ASSERT(
     34    offsetof( Per_CPU_Control, cpu_per_cpu.fsr)
     35      == SPARC_PER_CPU_FSR_OFFSET,
     36    SPARC_PER_CPU_FSR_OFFSET
     37  );
     38#endif
    3139
    3240#define SPARC_ASSERT_OFFSET(field, off) \
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    r1f6cdba6 r2764bd43  
    342342#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
    343343
    344 #define CPU_PER_CPU_CONTROL_SIZE 4
     344#if ( SPARC_HAS_FPU == 1 )
     345  #define CPU_PER_CPU_CONTROL_SIZE 8
     346#else
     347  #define CPU_PER_CPU_CONTROL_SIZE 4
     348#endif
    345349
    346350/**
     
    349353 */
    350354#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
     355
     356#if ( SPARC_HAS_FPU == 1 )
     357  /**
     358   * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
     359   * Per_CPU_Control begin.
     360   */
     361  #define SPARC_PER_CPU_FSR_OFFSET 4
     362#endif
    351363
    352364/**
     
    381393   */
    382394  uint32_t isr_dispatch_disable;
     395
     396#if ( SPARC_HAS_FPU == 1 )
     397  /**
     398   * @brief Memory location to store the FSR register during interrupt
     399   * processing.
     400   *
     401   * This is a write-only field.  The FSR is written to force a completion of
     402   * floating point operations in progress.
     403   */
     404  uint32_t fsr;
     405#endif
    383406} CPU_Per_CPU_control;
    384407
Note: See TracChangeset for help on using the changeset viewer.