Changeset 2764bd43 in rtems

Timestamp:

May 29, 2015, 1:54:27 PM (4 years ago)

Author:

Alexander Krutwig <alexander.krutwig@…>

Branches:

4.11, master

Children:

f9a2d36

Parents:

1f6cdba6

git-author:

Alexander Krutwig <alexander.krutwig@…> (05/29/15 13:54:27)

git-committer:

Sebastian Huber <sebastian.huber@…> (05/30/15 14:46:36)

Message:

sparc: Disable FPU in interrupt context

Update #2270.

Files:

• c/src/lib/libbsp/sparc/shared/irq_asm.S (modified) (4 diffs)
• cpukit/score/cpu/sparc/cpu.c (modified) (1 diff)
• cpukit/score/cpu/sparc/rtems/score/cpu.h (modified) (3 diffs)

c/src/lib/libbsp/sparc/shared/irq_asm.S

@@ -8 +8 @@
  *  On-Line Applications Research Corporation (OAR).
  *
- *  Copyright (c) 2014 embedded brains GmbH
+ *  Copyright (c) 2014-2015 embedded brains GmbH
  *
  *  The license and distribution terms for this file may be
@@ -424 +424 @@
         st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
 
+#if SPARC_HAS_FPU == 1
+        /*
+         * We cannot use an intermediate value for operations with the PSR[EF]
+         * bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
+         */
+        sethi    %hi(SPARC_PSR_EF_MASK), %l5
+#endif
+
         /*
          *  If ISR nest level was zero (now 1), then switch stack.
@@ -441 +449 @@
 
         ld       [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
+
+#if SPARC_HAS_FPU == 1
+        /*
+         * Test if the interrupted thread uses the floating point unit
+         * (PSR[EF] == 1).  In case it uses the floating point unit, then store
+         * the floating point status register.  This has the side-effect that
+         * all pending floating point operations complete before the store
+         * completes.  The PSR[EF] bit is restored after the call to the
+         * interrupt handler.  Thus post-switch actions (e.g. signal handlers)
+         * and context switch extensions may still corrupt the floating point
+         * context.
+         */
+        andcc    %l0, %l5, %g0
+        bne,a    dont_switch_stacks
+         st      %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
+#endif
 
 dont_switch_stacks:
@@ -472 +496 @@
         or       %g5, SPARC_PSR_PIL_MASK, %g5
 pil_fixed:
+
+#if SPARC_HAS_FPU == 1
+        /*
+         * Clear the PSR[EF] bit of the interrupted context to ensure that
+         * interrupt service routines cannot corrupt the floating point context.
+         */
+        andn     %g5, %l5, %g5
+#endif
+
         wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
 

cpukit/score/cpu/sparc/cpu.c

@@ -29 +29 @@
   SPARC_PER_CPU_ISR_DISPATCH_DISABLE
 );
+
+#if SPARC_HAS_FPU == 1
+  RTEMS_STATIC_ASSERT(
+    offsetof( Per_CPU_Control, cpu_per_cpu.fsr)
+      == SPARC_PER_CPU_FSR_OFFSET,
+    SPARC_PER_CPU_FSR_OFFSET
+  );
+#endif
 
 #define SPARC_ASSERT_OFFSET(field, off) \

cpukit/score/cpu/sparc/rtems/score/cpu.h

@@ -342 +342 @@
 #define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
 
-#define CPU_PER_CPU_CONTROL_SIZE 4
+#if ( SPARC_HAS_FPU == 1 )
+  #define CPU_PER_CPU_CONTROL_SIZE 8
+#else
+  #define CPU_PER_CPU_CONTROL_SIZE 4
+#endif
 
 /**
@@ -349 +353 @@
  */
 #define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
+
+#if ( SPARC_HAS_FPU == 1 )
+  /**
+   * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
+   * Per_CPU_Control begin.
+   */
+  #define SPARC_PER_CPU_FSR_OFFSET 4
+#endif
 
 /**
@@ -381 +393 @@
    */
   uint32_t isr_dispatch_disable;
+
+#if ( SPARC_HAS_FPU == 1 )
+  /**
+   * @brief Memory location to store the FSR register during interrupt
+   * processing.
+   *
+   * This is a write-only field.  The FSR is written to force a completion of
+   * floating point operations in progress.
+   */
+  uint32_t fsr;
+#endif
 } CPU_Per_CPU_control;