Changeset 273af8f in umon


Ignore:
Timestamp:
Jul 16, 2015, 11:26:43 AM (4 years ago)
Author:
Jarielle Catbagan <jcatbagan93@…>
Branches:
master
Children:
8a80d54
Parents:
b9f0b9e
git-author:
Jarielle Catbagan <jcatbagan93@…> (07/16/15 11:26:43)
git-committer:
Ed Sutter <edsutterjr@…> (07/18/15 13:13:24)
Message:

BBB: cpuio.c/rom_reset.S: Configure the MPU, Core, DDR, and Per PLLs and initialize the DDR3 memory

Location:
ports/beagleboneblack
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • ports/beagleboneblack/cpuio.c

    rb9f0b9e r273af8f  
    266266#endif
    267267}
     268
     269void
     270mpu_pll_init(void)
     271{
     272        uint32_t cm_clkmode_dpll_mpu;
     273        uint32_t cm_clksel_dpll_mpu;
     274        uint32_t cm_div_m2_dpll_mpu;
     275
     276        // Put MPU PLL in MN Bypass mode
     277        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
     278        cm_clkmode_dpll_mpu &= ~0x00000007;
     279        cm_clkmode_dpll_mpu |= 0x00000004;
     280        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
     281        // Wait for MPU PLL to enter MN Bypass mode
     282        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
     283
     284        // Set the ARM core frequency to 1 GHz
     285        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
     286        cm_clksel_dpll_mpu &= ~0x0007FF7F;
     287        cm_clksel_dpll_mpu |= 1000 << 8;
     288        cm_clksel_dpll_mpu |= 23;
     289        CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
     290        cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
     291        cm_div_m2_dpll_mpu &= ~0x0000001F;
     292        cm_div_m2_dpll_mpu |= 0x00000001;
     293        CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
     294
     295        // Lock MPU PLL
     296        cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
     297        cm_clkmode_dpll_mpu &= ~0x00000007;
     298        cm_clkmode_dpll_mpu |= 0x00000007;
     299        CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
     300        // Wait for MPU PLL to lock
     301        while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
     302}
     303
     304void
     305core_pll_init(void)
     306{
     307        uint32_t cm_clkmode_dpll_core;
     308        uint32_t cm_clksel_dpll_core;
     309        uint32_t cm_div_m4_dpll_core;
     310        uint32_t cm_div_m5_dpll_core;
     311        uint32_t cm_div_m6_dpll_core;
     312
     313        // Put Core PLL in MN Bypass mode
     314        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
     315        cm_clkmode_dpll_core &= ~0x00000007;
     316        cm_clkmode_dpll_core |= 0x00000004;
     317        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
     318        // Wait for Core PLL to enter MN Bypass mode
     319        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
     320
     321        // Configure the multiplier and divider
     322        cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
     323        cm_clksel_dpll_core &= ~0x0007FF7F;
     324        cm_clksel_dpll_core |= 1000 << 8;
     325        cm_clksel_dpll_core |= 23;
     326        CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
     327        // Configure the M4, M5, and M6 dividers
     328        cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
     329        cm_div_m4_dpll_core &= ~0x0000001F;
     330        cm_div_m4_dpll_core |= 10;
     331        CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
     332        cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
     333        cm_div_m5_dpll_core &= ~0x0000001F;
     334        cm_div_m5_dpll_core |= 8;
     335        CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
     336        cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
     337        cm_div_m6_dpll_core &= ~0x0000001F;
     338        cm_div_m6_dpll_core |= 4;
     339        CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
     340
     341        // Lock Core PLL
     342        cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
     343        cm_clkmode_dpll_core &= ~0x00000007;
     344        cm_clkmode_dpll_core |= 0x00000007;
     345        CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
     346        // Wait for Core PLL to lock
     347        while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
     348}
     349
     350void
     351ddr_pll_init(void)
     352{
     353        uint32_t cm_clkmode_dpll_ddr;
     354        uint32_t cm_clksel_dpll_ddr;
     355        uint32_t cm_div_m2_dpll_ddr;
     356
     357        // Put DDR PLL in MN Bypass mode
     358        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
     359        cm_clkmode_dpll_ddr &= ~0x00000007;
     360        cm_clkmode_dpll_ddr |= 0x00000004;
     361        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
     362        // Wait for DDR PLL to enter MN Bypass mode
     363        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
     364
     365        // Set the DDR frequency to 400 MHz
     366        cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
     367        cm_clksel_dpll_ddr &= ~0x0007FF7F;
     368        cm_clksel_dpll_ddr |= 400 << 8;
     369        cm_clksel_dpll_ddr |= 23;
     370        CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
     371        // Set M2 divider
     372        cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
     373        cm_div_m2_dpll_ddr &= ~0x0000001F;
     374        cm_div_m2_dpll_ddr |= 1;
     375        CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
     376
     377        // Lock the DDR PLL
     378        cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
     379        cm_clkmode_dpll_ddr &= ~0x00000007;
     380        cm_clkmode_dpll_ddr |= 0x00000007;
     381        CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
     382        // Wait for DDR PLL to lock
     383        while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
     384}
     385
     386void
     387per_pll_init(void)
     388{
     389        uint32_t cm_clkmode_dpll_per;
     390        uint32_t cm_clksel_dpll_per;
     391        uint32_t cm_div_m2_dpll_per;
     392
     393        // Put Per PLL in MN Bypass mode
     394        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
     395        cm_clkmode_dpll_per &= ~0x00000007;
     396        cm_clkmode_dpll_per |= 0x00000004;
     397        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
     398        // Wait for Per PLL to enter MN Bypass mode
     399        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
     400
     401        // Configure the multiplier and divider
     402        cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
     403        cm_clksel_dpll_per &= ~0xFF0FFFFF;
     404        cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
     405                CM_CLKSEL_DPLL_PER_DPLL_DIV;
     406        CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
     407        // Set M2 divider
     408        cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
     409        cm_div_m2_dpll_per &= ~0x0000007F;
     410        cm_div_m2_dpll_per |= 5;
     411        CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
     412
     413        // Lock the Per PLL
     414        cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
     415        cm_clkmode_dpll_per &= ~0x00000007;
     416        cm_clkmode_dpll_per |= 0x00000007;
     417        CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
     418        // Wait for Per PLL to lock
     419        while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
     420}
     421
     422void
     423pll_init(void)
     424{
     425        mpu_pll_init();
     426        core_pll_init();
     427        ddr_pll_init();
     428        per_pll_init();
     429}
     430
     431void
     432ddr_init(void)
     433{
     434        uint32_t reg;
     435
     436        // Enable the control module:
     437        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
     438
     439        // Enable EMIF module
     440        reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
     441        reg &= ~3;
     442        reg |= 2;
     443        CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
     444        while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
     445
     446        // Configure VTP control
     447        CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
     448        CNTL_MODULE_REG(VTP_CTRL) &= ~1;
     449        CNTL_MODULE_REG(VTP_CTRL) |= 1;
     450        // Wait for VTP control to be ready
     451        while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
     452
     453        // Configure the DDR PHY CMDx/DATAx registers
     454        DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
     455        DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
     456        DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
     457        DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
     458        DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
     459        DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
     460
     461        DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
     462        DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
     463        DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
     464        DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
     465
     466        DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
     467        DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
     468        DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
     469        DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
     470
     471        CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
     472        CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
     473        CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
     474        CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
     475        CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
     476
     477        CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
     478
     479        CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
     480
     481        // Enable dynamic power down when no read is being performed and set read latency
     482        // to CAS Latency + 2 - 1
     483        EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
     484        EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
     485
     486        // Configure the AC timing characteristics
     487        EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
     488        EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
     489        EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
     490        EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
     491        EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
     492        EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
     493
     494        // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
     495        EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
     496        // set the referesh rate shadow register to the same value as previous
     497        EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
     498
     499        // Configure the ZQ Calibration
     500        EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
     501
     502        // Configure the SDRAM characteristics
     503        reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
     504                SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
     505                SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
     506                SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
     507                SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
     508                SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
     509                SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
     510        EMIF0_REG(SDRAM_CONFIG) = reg;
     511        CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
     512
     513        // Set the external bank position to 0
     514        EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
     515}
  • ports/beagleboneblack/rom_reset.S

    rb9f0b9e r273af8f  
    5757   
    5858    .extern start
     59    .extern pll_init
     60    .extern ddr_init
    5961
    6062    .global reset
     
    172174    /* Reset the stack pointer for the SVC mode (our current mode) */
    173175    ldr sp, =(MonStack + MONSTACKSIZE - 4)
     176
     177    /* Initialize the MPU, Core, DDR, and Per PLLs.  Furthermore,
     178     * initialize the external DDR3 memory as well.
     179     */
     180dev_init:
     181    bl pll_init
     182    bl ddr_init
    174183
    175184    /*
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