Index: c/src/lib/libbsp/sparc/erc32/ChangeLog
===================================================================
--- c/src/lib/libbsp/sparc/erc32/ChangeLog	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/ChangeLog	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -1,2 +1,24 @@
+2000-11-13	Jiri Gaisler <jgais@ws.estec.esa.nl>
+
+	* Makefile.am, configure.in, gnatsupp/Makefile.am,
+	gnatsupp/gnatsupp.c, include/Makefile.am, include/bsp.h,
+	start/Makefile.am, startup/Makefile.am, startup/setvec.c,
+	wrapup/Makefile.am:
+	* erc32sonic: New directory.
+	* erc32sonic/Makefile.am, erc32sonic/erc32sonic.c,
+	erc32sonic/.cvsignore: New files.
+	* include/erc32.h: New file.
+	* startup/boardinit.S: New file.
+	Big update of SPARC support for ERC32 and LEON.
+	Added support for ERC32 without floating point.
+	Added SONIC support as configured on Tharsys ERC32 board.
+	The bsp's share various code in the shared directory:
+	   gnat-support, start-up code, etc.
+	To decrease the foot-print, I removed the 16 kbyte start-up
+	stack that was put in .bss and never reused once the system
+	was up. The stack is now put between the heap and the
+	workspace. To reclaim it, the user can do a rtems_region_extend
+	to merge the stack to the heap region once the system is up.
+
 2000-11-09	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
Index: c/src/lib/libbsp/sparc/erc32/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/Makefile.am	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -8,5 +8,6 @@
 # wrapup is the one that actually builds and installs the library
 #  from the individual .rel files built in other directories
-SUBDIRS = . start include startup gnatsupp console clock timer wrapup tools
+SUBDIRS = . include start startup gnatsupp console clock timer \
+    erc32sonic wrapup tools
 
 include $(top_srcdir)/../../bsp.am
Index: c/src/lib/libbsp/sparc/erc32/configure.in
===================================================================
--- c/src/lib/libbsp/sparc/erc32/configure.in	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/configure.in	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -18,5 +18,8 @@
 RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
 RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
+RTEMS_CHECK_NETWORKING
 RTEMS_CANONICAL_HOST
+
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
 
 RTEMS_CONFIG_BUILD_SUBDIRS(tools)
@@ -29,4 +32,5 @@
 clock/Makefile
 console/Makefile
+erc32sonic/Makefile
 gnatsupp/Makefile
 include/Makefile
Index: c/src/lib/libbsp/sparc/erc32/erc32sonic/.cvsignore
===================================================================
--- c/src/lib/libbsp/sparc/erc32/erc32sonic/.cvsignore	(revision 270042352bb97ab71be15205deded8fe44199b1e)
+++ c/src/lib/libbsp/sparc/erc32/erc32sonic/.cvsignore	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
Index: c/src/lib/libbsp/sparc/erc32/erc32sonic/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/erc32sonic/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
+++ c/src/lib/libbsp/sparc/erc32/erc32sonic/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -0,0 +1,35 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/erc32sonic.rel
+
+C_FILES = erc32sonic.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
+
+OBJS = $(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
+
+$(PGM): $(OBJS)
+	$(make-rel)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+
+all-local: $(ARCH) $(OBJS) $(PGM)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = erc32sonic.c
+
+include $(top_srcdir)/../../../../../../automake/local.am
Index: c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
===================================================================
--- c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c	(revision 270042352bb97ab71be15205deded8fe44199b1e)
+++ c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -0,0 +1,110 @@
+/*
+ *  THARSYS VME SPARC RT board SONIC Configuration Information
+ *
+ *  References:
+ *
+ *  1) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
+ *     DY 4 Systems Inc., Kanata, Ontario, September, 1996.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <libchip/sonic.h>
+#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
+#include <stdio.h>
+#endif
+
+void erc32_sonic_write_register(
+  void       *base,
+  unsigned32  regno,
+  unsigned32  value
+)
+{
+  volatile unsigned32 *p = base;
+
+#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
+  printf( "%p Write 0x%04x to %s (0x%02x)\n",
+      &p[regno], value, SONIC_Reg_name[regno], regno );
+  fflush( stdout );
+#endif
+  p[regno] = 0x0ffff & value;
+}
+
+unsigned32 erc32_sonic_read_register(
+  void       *base,
+  unsigned32  regno
+)
+{
+  volatile unsigned32 *p = base;
+  unsigned32           value;
+
+  value = p[regno];
+#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
+  printf( "%p Read 0x%04x from %s (0x%02x)\n",
+      &p[regno], value, SONIC_Reg_name[regno], regno );
+  fflush( stdout );
+#endif
+  return 0x0ffff & value;
+}
+
+/*
+ * Default sizes of transmit and receive descriptor areas
+ */
+#define RDA_COUNT     20 /* 20 */
+#define TDA_COUNT     20 /* 10 */
+
+/*
+ * Default device configuration register values
+ * Conservative, generic values.
+ * DCR:
+ *      No extended bus mode
+ *      Unlatched bus retry
+ *      Programmable outputs unused
+ *      Asynchronous bus mode
+ *      User definable pins unused
+ *      No wait states (access time controlled by DTACK*)
+ *      32-bit DMA
+ *      Empty/Fill DMA mode
+ *      Maximum Transmit/Receive FIFO
+ * DC2:
+ *      Extended programmable outputs unused
+ *      Normal HOLD request
+ *      Packet compress output unused
+ *      No reject on CAM match
+ */
+#define SONIC_DCR  ( DCR_DW32 | DCR_RFT24 | DCR_TFT28)
+#define SONIC_DC2 (0)
+
+/*
+ * Default location of device registers
+ */
+#define SONIC_BASE_ADDRESS 0x10000100
+
+/*
+ * Default interrupt vector
+ */
+#define SONIC_VECTOR 0x1E
+
+sonic_configuration_t erc32_sonic_configuration = {
+  SONIC_BASE_ADDRESS,        /* base address */ 
+  SONIC_VECTOR,              /* vector number */ 
+  SONIC_DCR,                 /* DCR register value */
+  SONIC_DC2,                 /* DC2 register value */
+  TDA_COUNT,                 /* number of transmit descriptors */
+  RDA_COUNT,                 /* number of receive descriptors */
+  erc32_sonic_write_register,
+  erc32_sonic_read_register
+};
+
+int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
+{
+
+  ERC32_MEC.IO_Configuration |= (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
+  ERC32_MEC.Control &= ~0xe0000;	/* Disable DMA time-out and parity */
+  ERC32_MEC.Control |= 0x10001; 		/* Enable DMA */
+  ERC32_MEC.Interrupt_Mask &= ~0x000340;
+  *((volatile int *) 0x10000300) = 0;
+  return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration ));
+  
+}
Index: c/src/lib/libbsp/sparc/erc32/gnatsupp/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/gnatsupp/Makefile.am	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/gnatsupp/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -5,9 +5,9 @@
 AUTOMAKE_OPTIONS = foreign 1.4
 
-VPATH = @srcdir@:@srcdir@/../../../shared
+VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
 
 PGM = $(ARCH)/gnatsupp.rel
 
-C_FILES = gnatsupp.c
+C_FILES = gnatsupp.c gnatcommon.c
 C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
 
@@ -29,5 +29,5 @@
 .PRECIOUS: $(PGM)
 
-EXTRA_DIST = gnatsupp.c
+EXTRA_DIST = gnatsupp.c gnatcommon.c
 
 include $(top_srcdir)/../../../../../../automake/local.am
Index: c/src/lib/libbsp/sparc/erc32/gnatsupp/gnatsupp.c
===================================================================
--- c/src/lib/libbsp/sparc/erc32/gnatsupp/gnatsupp.c	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/gnatsupp/gnatsupp.c	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -6,109 +6,7 @@
  */
 
-#include <bsp.h>
-#include <signal.h>
-
-/*
- * Synchronous trap handler. Map the trap number of SIGFPE, SIGSEGV
- * or SIGILL to generate the corresponding Ada exception.
- */
-
-rtems_isr __gnat_exception_handler
-  (rtems_vector_number trap)
-{
-  rtems_unsigned32 real_trap;
-  rtems_unsigned32 signal;
-
-  real_trap = SPARC_REAL_TRAP_NUMBER (trap);
-  switch (real_trap)
-    {
-    case 0x08:			/* FPU exception */
-    case 0x0A:			/* TAG overflow */
-    case 0x82:			/* divide by zero */
-      signal = SIGFPE;		/* Will cause Constraint_Error */
-      break;
-    case 0x01:			/* Instruction access exception */
-    case 0x09:			/* Data access exception */
-      signal = SIGSEGV;		/* Will cause Storage_Error */
-      break;
-    default:			/* Anything else ... */
-      signal = SIGILL;		/* Will cause Program_Error */
-      break;
-    }
-  kill (getpid (), signal);
-}
-
-/*
- * Asynchronous trap handler. As it happens, the interrupt trap numbers for
- * SPARC is 17 - 31, so we just map then directly on the same signal number.
- */
-
-rtems_isr __gnat_interrupt_handler
-  (rtems_vector_number trap)
-{
-  rtems_unsigned32 real_trap;
-
-  real_trap = SPARC_REAL_TRAP_NUMBER (trap);
-
-  kill (getpid (), real_trap);
-
-}
-
-/*
- * Default signal handler with error reporting 
- */
-
-void
-__gnat_signals_Abormal_termination_handler (int signo)
-{
-  switch (signo)
-    {
-    case SIGFPE:
-      DEBUG_puts ("\nConstraint_Error\n");
-      break;
-    case SIGSEGV:
-      DEBUG_puts ("\nStorage_Error\n");
-      break;
-    default:
-      DEBUG_puts ("\nProgram_Error\n");
-      break;
-    }
-  exit (1);
-}
-
-const struct sigaction __gnat_error_vector =
-{0, -1,
- {__gnat_signals_Abormal_termination_handler}};
-
 void
 __gnat_install_handler ()
 {
-  rtems_unsigned32 trap;
-  rtems_isr_entry previous_isr;
-
-  sigaction (SIGSEGV, &__gnat_error_vector, NULL);
-  sigaction (SIGFPE, &__gnat_error_vector, NULL);
-  sigaction (SIGILL, &__gnat_error_vector, NULL);
-
-  for (trap = 0; trap < 256; trap++)
-    {
-
-      /*
-         *  Skip window overflow, underflow, and flush as well as software
-         *  trap 0 which we will use as a shutdown. Also avoid trap 0x70 - 0x7f
-         *  which cannot happen and where some of the space is used to pass
-         *  paramaters to the program. Trap 0x1d is used by the clock tick,
-         *  0x80 for system traps and 0x81 - 0x83 by the remote debugging stub.
-	 *  Avoid 0x15 (UART B interrupt) which is also used by the stub 
-	 *  to generate a 'break-in' interrupt.
-       */
-
-      if ((trap >= 0x11) && (trap <= 0x1f))
-	{
-	  if ((trap != 0x1d) && (trap != 0x15))
-	    rtems_interrupt_catch (__gnat_interrupt_handler, trap, &previous_isr);
-	}
-      else if ((trap != 5 && trap != 6) && ((trap < 0x70) || (trap > 0x83)))
-	set_vector (__gnat_exception_handler, SPARC_SYNCHRONOUS_TRAP (trap), 1);
-    }
+  __gnat_install_handler_common (0x1d, 0x15);
 }
Index: c/src/lib/libbsp/sparc/erc32/include/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/include/Makefile.am	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/include/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -5,5 +5,5 @@
 AUTOMAKE_OPTIONS = foreign 1.4
 
-H_FILES = bsp.h coverhd.h
+H_FILES = bsp.h coverhd.h erc32.h
 
 $(PROJECT_INCLUDE):
Index: c/src/lib/libbsp/sparc/erc32/include/bsp.h
===================================================================
--- c/src/lib/libbsp/sparc/erc32/include/bsp.h	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/include/bsp.h	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -42,4 +42,13 @@
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
 #define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
+
+/*
+ * Network driver configuration
+ */
+
+struct rtems_bsdnet_ifconfig;
+extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config);
+#define RTEMS_BSP_NETWORK_DRIVER_NAME	"sonic1"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_erc32_sonic_driver_attach
 
 /*
Index: c/src/lib/libbsp/sparc/erc32/include/erc32.h
===================================================================
--- c/src/lib/libbsp/sparc/erc32/include/erc32.h	(revision 270042352bb97ab71be15205deded8fe44199b1e)
+++ c/src/lib/libbsp/sparc/erc32/include/erc32.h	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -0,0 +1,520 @@
+/*  erc32.h
+ *
+ *  This include file contains information pertaining to the ERC32.
+ *  The ERC32 is a custom SPARC V7 implementation based on the Cypress
+ *  601/602 chipset.  This CPU has a number of on-board peripherals and
+ *  was developed by the European Space Agency to target space applications.
+ *
+ *  NOTE:  Other than where absolutely required, this version currently 
+ *         supports only the peripherals and bits used by the basic board 
+ *         support package. This includes at least significant pieces of 
+ *         the following items:
+ *
+ *           + UART Channels A and B
+ *           + General Purpose Timer
+ *           + Real Time Clock
+ *           + Watchdog Timer (so it can be disabled)
+ *           + Control Register (so powerdown mode can be enabled)
+ *           + Memory Control Register
+ *           + Interrupt Control
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+ 
+#ifndef _INCLUDE_ERC32_h
+#define _INCLUDE_ERC32_h
+
+#include <rtems/score/sparc.h>
+ 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  Interrupt Sources
+ *
+ *  The interrupt source numbers directly map to the trap type and to 
+ *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
+ *  and the Interrupt Pending Registers.
+ */
+
+#define ERC32_INTERRUPT_MASKED_ERRORS             1
+#define ERC32_INTERRUPT_EXTERNAL_1                2
+#define ERC32_INTERRUPT_EXTERNAL_2                3
+#define ERC32_INTERRUPT_UART_A_RX_TX              4
+#define ERC32_INTERRUPT_UART_B_RX_TX              5
+#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR  6
+#define ERC32_INTERRUPT_UART_ERROR                7
+#define ERC32_INTERRUPT_DMA_ACCESS_ERROR          8
+#define ERC32_INTERRUPT_DMA_TIMEOUT               9
+#define ERC32_INTERRUPT_EXTERNAL_3               10
+#define ERC32_INTERRUPT_EXTERNAL_4               11
+#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER    12
+#define ERC32_INTERRUPT_REAL_TIME_CLOCK          13
+#define ERC32_INTERRUPT_EXTERNAL_5               14
+#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT         15
+
+#ifndef ASM
+
+/*
+ *  Trap Types for on-chip peripherals
+ *
+ *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
+ *
+ *  NOTE: The priority level for each source corresponds to the least 
+ *        significant nibble of the trap type.
+ */
+
+#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
+
+#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
+
+#define ERC32_Is_MEC_Trap( _trap ) \
+  ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
+    (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
+
+/*
+ *  Structure for ERC32 memory mapped registers.  
+ *
+ *  Source: Section 3.25.2 - Register Address Map
+ *
+ *  NOTE:  There is only one of these structures per CPU, its base address 
+ *         is 0x01f80000, and the variable MEC is placed there by the 
+ *         linkcmds file.
+ */
+
+typedef struct {
+  volatile unsigned32  Control;                              /* offset 0x00 */
+  volatile unsigned32  Software_Reset;                       /* offset 0x04 */
+  volatile unsigned32  Power_Down;                           /* offset 0x08 */
+  volatile unsigned32  Unimplemented_0;                      /* offset 0x0c */
+  volatile unsigned32  Memory_Configuration;                 /* offset 0x10 */
+  volatile unsigned32  IO_Configuration;                     /* offset 0x14 */
+  volatile unsigned32  Wait_State_Configuration;             /* offset 0x18 */
+  volatile unsigned32  Unimplemented_1;                      /* offset 0x1c */
+  volatile unsigned32  Memory_Access_0;                      /* offset 0x20 */
+  volatile unsigned32  Memory_Access_1;                      /* offset 0x24 */
+  volatile unsigned32  Unimplemented_2[ 7 ];                 /* offset 0x28 */
+  volatile unsigned32  Interrupt_Shape;                      /* offset 0x44 */
+  volatile unsigned32  Interrupt_Pending;                    /* offset 0x48 */
+  volatile unsigned32  Interrupt_Mask;                       /* offset 0x4c */
+  volatile unsigned32  Interrupt_Clear;                      /* offset 0x50 */
+  volatile unsigned32  Interrupt_Force;                      /* offset 0x54 */
+  volatile unsigned32  Unimplemented_3[ 2 ];                 /* offset 0x58 */
+                                                             /* offset 0x60 */
+  volatile unsigned32  Watchdog_Program_and_Timeout_Acknowledge; 
+  volatile unsigned32  Watchdog_Trap_Door_Set;               /* offset 0x64 */
+  volatile unsigned32  Unimplemented_4[ 6 ];                 /* offset 0x68 */
+  volatile unsigned32  Real_Time_Clock_Counter;              /* offset 0x80 */
+  volatile unsigned32  Real_Time_Clock_Scalar;               /* offset 0x84 */
+  volatile unsigned32  General_Purpose_Timer_Counter;        /* offset 0x88 */
+  volatile unsigned32  General_Purpose_Timer_Scalar;         /* offset 0x8c */
+  volatile unsigned32  Unimplemented_5[ 2 ];                 /* offset 0x90 */
+  volatile unsigned32  Timer_Control;                        /* offset 0x98 */
+  volatile unsigned32  Unimplemented_6;                      /* offset 0x9c */
+  volatile unsigned32  System_Fault_Status;                  /* offset 0xa0 */
+  volatile unsigned32  First_Failing_Address;                /* offset 0xa4 */
+  volatile unsigned32  First_Failing_Data;                   /* offset 0xa8 */
+  volatile unsigned32  First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
+  volatile unsigned32  Error_and_Reset_Status;               /* offset 0xb0 */
+  volatile unsigned32  Error_Mask;                           /* offset 0xb4 */
+  volatile unsigned32  Unimplemented_7[ 2 ];                 /* offset 0xb8 */
+  volatile unsigned32  Debug_Control;                        /* offset 0xc0 */
+  volatile unsigned32  Breakpoint;                           /* offset 0xc4 */
+  volatile unsigned32  Watchpoint;                           /* offset 0xc8 */
+  volatile unsigned32  Unimplemented_8;                      /* offset 0xcc */
+  volatile unsigned32  Test_Control;                         /* offset 0xd0 */
+  volatile unsigned32  Test_Data;                            /* offset 0xd4 */
+  volatile unsigned32  Unimplemented_9[ 2 ];                 /* offset 0xd8 */
+  volatile unsigned32  UART_Channel_A;                       /* offset 0xe0 */
+  volatile unsigned32  UART_Channel_B;                       /* offset 0xe4 */
+  volatile unsigned32  UART_Status;                          /* offset 0xe8 */
+} ERC32_Register_Map;
+
+#endif
+
+/*
+ *  The following constants are intended to be used ONLY in assembly
+ *  language files.
+ *
+ *  NOTE:  The intended style of usage is to load the address of MEC
+ *         into a register and then use these as displacements from
+ *         that register.
+ */
+
+#ifdef ASM
+
+#define  ERC32_MEC_CONTROL_OFFSET                                  0x00
+#define  ERC32_MEC_SOFTWARE_RESET_OFFSET                           0x04
+#define  ERC32_MEC_POWER_DOWN_OFFSET                               0x08
+#define  ERC32_MEC_UNIMPLEMENTED_0_OFFSET                          0x0C
+#define  ERC32_MEC_MEMORY_CONFIGURATION_OFFSET                     0x10
+#define  ERC32_MEC_IO_CONFIGURATION_OFFSET                         0x14
+#define  ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET                 0x18
+#define  ERC32_MEC_UNIMPLEMENTED_1_OFFSET                          0x1C
+#define  ERC32_MEC_MEMORY_ACCESS_0_OFFSET                          0x20
+#define  ERC32_MEC_MEMORY_ACCESS_1_OFFSET                          0x24
+#define  ERC32_MEC_UNIMPLEMENTED_2_OFFSET                          0x28
+#define  ERC32_MEC_INTERRUPT_SHAPE_OFFSET                          0x44
+#define  ERC32_MEC_INTERRUPT_PENDING_OFFSET                        0x48
+#define  ERC32_MEC_INTERRUPT_MASK_OFFSET                           0x4C
+#define  ERC32_MEC_INTERRUPT_CLEAR_OFFSET                          0x50
+#define  ERC32_MEC_INTERRUPT_FORCE_OFFSET                          0x54
+#define  ERC32_MEC_UNIMPLEMENTED_3_OFFSET                          0x58
+#define  ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
+#define  ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET                   0x64
+#define  ERC32_MEC_UNIMPLEMENTED_4_OFFSET                          0x6C
+#define  ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET                  0x80
+#define  ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET                   0x84
+#define  ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET            0x88
+#define  ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET             0x8C
+#define  ERC32_MEC_UNIMPLEMENTED_5_OFFSET                          0x90
+#define  ERC32_MEC_TIMER_CONTROL_OFFSET                            0x98
+#define  ERC32_MEC_UNIMPLEMENTED_6_OFFSET                          0x9C
+#define  ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET                      0xA0
+#define  ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET                    0xA4
+#define  ERC32_MEC_FIRST_FAILING_DATA_OFFSET                       0xA8
+#define  ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET    0xAC
+#define  ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET                   0xB0
+#define  ERC32_MEC_ERROR_MASK_OFFSET                               0xB4
+#define  ERC32_MEC_UNIMPLEMENTED_7_OFFSET                          0xB8
+#define  ERC32_MEC_DEBUG_CONTROL_OFFSET                            0xC0
+#define  ERC32_MEC_BREAKPOINT_OFFSET                               0xC4
+#define  ERC32_MEC_WATCHPOINT_OFFSET                               0xC8
+#define  ERC32_MEC_UNIMPLEMENTED_8_OFFSET                          0xCC
+#define  ERC32_MEC_TEST_CONTROL_OFFSET                             0xD0
+#define  ERC32_MEC_TEST_DATA_OFFSET                                0xD4
+#define  ERC32_MEC_UNIMPLEMENTED_9_OFFSET                          0xD8
+#define  ERC32_MEC_UART_CHANNEL_A_OFFSET                           0xE0
+#define  ERC32_MEC_UART_CHANNEL_B_OFFSET                           0xE4
+#define  ERC32_MEC_UART_STATUS_OFFSET                              0xE8
+
+#endif
+
+/*
+ *  The following defines the bits in the Configuration Register.
+ */
+
+#define ERC32_CONFIGURATION_POWER_DOWN_MASK               0x00000001
+#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED            0x00000001
+#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED           0x00000000
+
+#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK           0x00000002
+#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED        0x00000002
+#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED       0x00000000
+
+#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK              0x00000004
+#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED           0x00000004
+#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED          0x00000000
+
+#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK        0x00000008
+#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED     0x00000008
+#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED    0x00000000
+
+
+/*
+ *  The following defines the bits in the Memory Configuration Register.
+ */
+
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001C00
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K  ( 0 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K  ( 1 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB   ( 2 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB   ( 3 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB   ( 4 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB   ( 5 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB  ( 6 << 10 )
+#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB  ( 7 << 10 )
+
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
+ 
+/*
+ *  The following defines the bits in the Timer Control Register.
+ */
+
+#define ERC32_MEC_TIMER_CONTROL_GCR    0x00000001  /* 1 = reload at 0 */
+                                               /* 0 = stop at 0 */
+#define ERC32_MEC_TIMER_CONTROL_GCL    0x00000002  /* 1 = load and start */
+                                               /* 0 = no function */
+#define ERC32_MEC_TIMER_CONTROL_GSE    0x00000004  /* 1 = enable counting */
+                                               /* 0 = hold scalar and counter */
+#define ERC32_MEC_TIMER_CONTROL_GSL    0x00000008  /* 1 = load scalar and start */
+                                               /* 0 = no function */
+
+#define ERC32_MEC_TIMER_CONTROL_RTCCR  0x00000100  /* 1 = reload at 0 */
+                                               /* 0 = stop at 0 */
+#define ERC32_MEC_TIMER_CONTROL_RTCCL  0x00000200  /* 1 = load and start */
+                                               /* 0 = no function */
+#define ERC32_MEC_TIMER_CONTROL_RTCSE  0x00000400  /* 1 = enable counting */
+                                               /* 0 = hold scalar and counter */
+#define ERC32_MEC_TIMER_CONTROL_RTCSL  0x00000800  /* 1 = load scalar and start */
+                                               /* 0 = no function */
+
+/*
+ *  The following defines the bits in the UART Control Registers.
+ *
+ */
+
+#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
+ 
+/*
+ *  The following defines the bits in the MEC UART Control Registers.
+ */
+
+#define ERC32_MEC_UART_STATUS_DR   0x00000001 /* Data Ready */
+#define ERC32_MEC_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
+#define ERC32_MEC_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
+#define ERC32_MEC_UART_STATUS_FE   0x00000010 /* RX Framing Error */
+#define ERC32_MEC_UART_STATUS_PE   0x00000020 /* RX Parity Error */
+#define ERC32_MEC_UART_STATUS_OE   0x00000040 /* RX Overrun Error */
+#define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
+#define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
+#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
+#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
+#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
+#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
+
+#define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
+#define ERC32_MEC_UART_STATUS_TSEA  (ERC32_MEC_UART_STATUS_TSE << 0)
+#define ERC32_MEC_UART_STATUS_THEA  (ERC32_MEC_UART_STATUS_THE << 0)
+#define ERC32_MEC_UART_STATUS_FEA   (ERC32_MEC_UART_STATUS_FE  << 0)
+#define ERC32_MEC_UART_STATUS_PEA   (ERC32_MEC_UART_STATUS_PE  << 0)
+#define ERC32_MEC_UART_STATUS_OEA   (ERC32_MEC_UART_STATUS_OE  << 0)
+#define ERC32_MEC_UART_STATUS_CUA   (ERC32_MEC_UART_STATUS_CU  << 0)
+#define ERC32_MEC_UART_STATUS_TXEA  (ERC32_MEC_UART_STATUS_TXE << 0)
+
+#define ERC32_MEC_UART_STATUS_DRB   (ERC32_MEC_UART_STATUS_DR  << 16)
+#define ERC32_MEC_UART_STATUS_TSEB  (ERC32_MEC_UART_STATUS_TSE << 16)
+#define ERC32_MEC_UART_STATUS_THEB  (ERC32_MEC_UART_STATUS_THE << 16)
+#define ERC32_MEC_UART_STATUS_FEB   (ERC32_MEC_UART_STATUS_FE  << 16)
+#define ERC32_MEC_UART_STATUS_PEB   (ERC32_MEC_UART_STATUS_PE  << 16)
+#define ERC32_MEC_UART_STATUS_OEB   (ERC32_MEC_UART_STATUS_OE  << 16)
+#define ERC32_MEC_UART_STATUS_CUB   (ERC32_MEC_UART_STATUS_CU  << 16)
+#define ERC32_MEC_UART_STATUS_TXEB  (ERC32_MEC_UART_STATUS_TXE << 16)
+
+#ifndef ASM
+
+/*
+ *  This is used to manipulate the on-chip registers.
+ *
+ *  The following symbol must be defined in the linkcmds file and point
+ *  to the correct location.
+ */
+
+extern ERC32_Register_Map ERC32_MEC;
+ 
+/*
+ *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
+ *  and the Interrupt Pending Registers.
+ *
+ *  NOTE: For operations which are not atomic, this code disables interrupts
+ *        to guarantee there are no intervening accesses to the same register.
+ *        The operations which read the register, modify the value and then
+ *        store the result back are vulnerable.
+ */
+
+#define ERC32_Clear_interrupt( _source ) \
+  do { \
+    ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
+  } while (0)
+
+#define ERC32_Force_interrupt( _source ) \
+  do { \
+    unsigned32 _level; \
+    \
+    _level = sparc_disable_interrupts(); \
+    ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
+    ERC32_MEC.Interrupt_Force = (1 << (_source)); \
+    sparc_enable_interrupts( _level ); \
+  } while (0)
+ 
+#define ERC32_Is_interrupt_pending( _source ) \
+  (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
+ 
+#define ERC32_Is_interrupt_masked( _source ) \
+  (ERC32_MEC.Interrupt_Masked & (1 << (_source)))
+ 
+#define ERC32_Mask_interrupt( _source ) \
+  do { \
+    unsigned32 _level; \
+    \
+    _level = sparc_disable_interrupts(); \
+      ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
+    sparc_enable_interrupts( _level ); \
+  } while (0)
+ 
+#define ERC32_Unmask_interrupt( _source ) \
+  do { \
+    unsigned32 _level; \
+    \
+    _level = sparc_disable_interrupts(); \
+      ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
+    sparc_enable_interrupts( _level ); \
+  } while (0)
+
+#define ERC32_Disable_interrupt( _source, _previous ) \
+  do { \
+    unsigned32 _level; \
+    unsigned32 _mask = 1 << (_source); \
+    \
+    _level = sparc_disable_interrupts(); \
+      (_previous) = ERC32_MEC.Interrupt_Mask; \
+      ERC32_MEC.Interrupt_Mask = _previous | _mask; \
+    sparc_enable_interrupts( _level ); \
+    (_previous) &= _mask; \
+  } while (0)
+ 
+#define ERC32_Restore_interrupt( _source, _previous ) \
+  do { \
+    unsigned32 _level; \
+    unsigned32 _mask = 1 << (_source); \
+    \
+    _level = sparc_disable_interrupts(); \
+      ERC32_MEC.Interrupt_Mask = \
+        (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
+    sparc_enable_interrupts( _level ); \
+  } while (0)
+
+/*
+ *  The following macros attempt to hide the fact that the General Purpose
+ *  Timer and Real Time Clock Timer share the Timer Control Register.  Because
+ *  the Timer Control Register is write only, we must mirror it in software
+ *  and insure that writes to one timer do not alter the current settings
+ *  and status of the other timer.
+ *
+ *  This code promotes the view that the two timers are completely independent.
+ *  By exclusively using the routines below to access the Timer Control 
+ *  Register, the application can view the system as having a General Purpose
+ *  Timer Control Register and a Real Time Clock Timer Control Register 
+ *  rather than the single shared value.
+ *
+ *  Each logical timer control register is organized as follows:
+ *
+ *    D0 - Counter Reload
+ *          1 = reload counter at zero and restart
+ *          0 = stop counter at zero
+ *
+ *    D1 - Counter Load
+ *          1 = load counter with preset value and restart
+ *          0 = no function
+ *
+ *    D2 - Enable
+ *          1 = enable counting
+ *          0 = hold scaler and counter
+ *
+ *    D3 - Scaler Load
+ *          1 = load scalar with preset value and restart
+ *          0 = no function
+ *
+ *  To insure the management of the mirror is atomic, we disable interrupts
+ *  around updates.
+ */
+
+#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000001
+#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
+
+#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER       0x00000002
+
+#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING    0x00000004
+#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
+
+#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER        0x00000008
+
+#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK        0x00000001
+#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK        0x00000004
+
+#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK       0x0000000F
+#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000005
+
+SCORE_EXTERN unsigned32 _ERC32_MEC_Timer_Control_Mirror;
+
+/*
+ *  This macros manipulate the General Purpose Timer portion of the 
+ *  Timer Control register and promote the view that there are actually
+ *  two independent Timer Control Registers.
+ */
+
+#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
+  do { \
+    unsigned32 _level; \
+    unsigned32 _control; \
+    unsigned32 __value; \
+    \
+    __value = ((_value) & 0x0f); \
+    _level = sparc_disable_interrupts(); \
+      _control = _ERC32_MEC_Timer_Control_Mirror; \
+      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
+      _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
+      _control |= __value; \
+      /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control );  */ \
+      ERC32_MEC.Timer_Control = _control; \
+    sparc_enable_interrupts( _level ); \
+  } while ( 0 )
+
+#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
+  do { \
+    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
+  } while ( 0 )
+
+/*
+ *  This macros manipulate the Real Timer Clock Timer portion of the 
+ *  Timer Control register and promote the view that there are actually
+ *  two independent Timer Control Registers.
+ */
+ 
+#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
+  do { \
+    unsigned32 _level; \
+    unsigned32 _control; \
+    unsigned32 __value; \
+    \
+    __value = ((_value) & 0x0f) << 8; \
+    _level = sparc_disable_interrupts(); \
+      _control = _ERC32_MEC_Timer_Control_Mirror; \
+      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
+      _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
+      _control |= __value; \
+      /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
+      ERC32_MEC.Timer_Control = _control; \
+    sparc_enable_interrupts( _level ); \
+  } while ( 0 )
+ 
+#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
+  do { \
+    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
+  } while ( 0 )
+
+
+#endif /* !ASM */
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif /* !_INCLUDE_ERC32_h */
+/* end of include file */
+
Index: c/src/lib/libbsp/sparc/erc32/start/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/start/Makefile.am	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/start/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -4,4 +4,6 @@
 
 AUTOMAKE_OPTIONS = foreign 1.4
+
+VPATH = @srcdir@:@srcdir@/../../shared
 
 PGM = $(ARCH)/start.o
Index: c/src/lib/libbsp/sparc/erc32/start/start.S
===================================================================
--- c/src/lib/libbsp/sparc/erc32/start/start.S	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ 	(revision )
@@ -1,338 +1,0 @@
-/*
- *  startsis.s
- *
- *  Start code for the ERC32.
- *
- *  This is based on the file srt0.s provided with the binary
- *  distribution of the SPARC Instruction Simulator (SIS) found
- *  at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
- *
- *  $Id$
- */
-
-#include <asm.h>
-#include <libcpu/erc32.h>
-
-/*
- *  Unexpected trap will halt the processor by forcing it to error state
- */
-
-#define BAD_TRAP \
-  ta 0; \
-  nop; \
-  nop; \
-  nop;
-
-/*
- *  Software trap. Treat as BAD_TRAP for the time being...
- */
-
-#define SOFT_TRAP BAD_TRAP
-
-
-  .seg    "text"
-  PUBLIC(start)
-  .global start
-
-SYM(start):
-start:
-
-/* 
- *  The trap table has to be the first code in a boot PROM.  But because
- *  the Memory Configuration comes up thinking we only have 4K of PROM, we
- *  cannot have a full trap table and still have room left over to 
- *  reprogram the Memory Configuration register correctly.  This file
- *  uses an abbreviated trap which has every entry which might be used
- *  before RTEMS installs its own trap table.
- */
-
-
-  PUBLIC(trap_table)
-SYM(trap_table):
-
-  RTRAP( 0, SYM(hard_reset) );                   ! 00 reset trap 
-  BAD_TRAP;                                     ! 01 instruction access 
-                                                !    exception
-  BAD_TRAP;                                     ! 02 illegal instruction
-  BAD_TRAP;                                     ! 03 privileged instruction
-  BAD_TRAP;                                     ! 04 fp disabled
-  TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow
-  TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow
-  BAD_TRAP;                                     ! 07 memory address not aligned
-  BAD_TRAP;                                     ! 08 fp exception
-  BAD_TRAP;                                     ! 09 data access exception
-  BAD_TRAP;                                     ! 0A tag overflow
-  BAD_TRAP;                                     ! 0B undefined
-  BAD_TRAP;                                     ! 0C undefined
-  BAD_TRAP;                                     ! 0D undefined
-  BAD_TRAP;                                     ! 0E undefined
-  BAD_TRAP;                                     ! 0F undefined
-  BAD_TRAP;                                     ! 10 undefined
-
-  /* 
-   *  ERC32 defined traps
-   */
-
-  BAD_TRAP;                                     ! 11 masked errors
-  BAD_TRAP;                                     ! 12 external 1
-  BAD_TRAP;                                     ! 13 external 2
-  BAD_TRAP;                                     ! 14 UART A RX/TX
-  BAD_TRAP;                                     ! 15 UART B RX/TX
-  BAD_TRAP;                                     ! 16 correctable memory error
-  BAD_TRAP;                                     ! 17 UART error
-  BAD_TRAP;                                     ! 18 DMA access error
-  BAD_TRAP;                                     ! 19 DMA timeout
-  BAD_TRAP;                                     ! 1A external 3
-  BAD_TRAP;                                     ! 1B external 4
-  BAD_TRAP;                                     ! 1C general purpose timer
-  BAD_TRAP;                                     ! 1D real time clock
-  BAD_TRAP;                                     ! 1E external 5
-  BAD_TRAP;                                     ! 1F watchdog timeout
-
-
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 20 - 23 undefined
-  BAD_TRAP;                                     ! 24 cp_disabled
-            BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 25 - 27 undefined
-  BAD_TRAP;                                     ! 28 cp_exception
-            BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 29 - 2B undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 2C - 2F undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 30 - 33 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 34 - 37 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 38 - 3B undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 3C - 3F undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 40 - 43 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 44 - 47 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 48 - 4B undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 4C - 4F undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 50 - 53 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 54 - 57 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 58 - 5B undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 5C - 5F undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 60 - 63 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 64 - 67 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 68 - 6B undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 6C - 6F undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 70 - 73 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 74 - 77 undefined
-  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 78 - 7B undefined
-
-/* 
-   This is a sad patch to make sure that we know where the
-   MEC timer control register mirror is so we can stop the timers
-   from an external debugger. It is needed because the control
-   register is write-only. Trap 0x7C cannot occure in ERC32...
-
-   We also use this location to store the last location of the
-   usable RAM in order not to overwrite the remote debugger with
-   the RTEMS work-space area.
-
-*/
-
-	.global __ERC32_MEC_Timer_Control_Mirror, SYM(rdb_start), SYM(CLOCK_SPEED)
-
-SYM(rdb_start):
-__ERC32_MEC_Timer_Control_Mirror:
-
-  BAD_TRAP; BAD_TRAP;                           ! 7C - 7D undefined
-
-SYM(CLOCK_SPEED):
-
-  .word	0x0a, 0, 0, 0				! 7E (10 MHz default)
-  
-  BAD_TRAP; 					! 7F undefined
-
-  /* 
-   *  Software traps
-   *
-   *  NOTE: At the risk of being redundant... this is not a full
-   *        table.  The setjmp on the SPARC requires a window flush trap
-   *        handler and RTEMS will preserve the entries that were
-   *        installed before.
-   */
-
-  TRAP( 0x80, SYM(syscall) ); 			! 80 syscall SW trap
-  SOFT_TRAP; SOFT_TRAP;  	            	! 81 - 82
-  TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap
-
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 84 - 87
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 88 - 8B
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 8C - 8F
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 90 - 93
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 94 - 97
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 98 - 9B
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 9C - 9F
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A0 - A3
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A4 - A7
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A8 - AB
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! AC - AF
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B0 - B3
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B4 - B7
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B8 - BB
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! BC - BF
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C0 - C3
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C4 - C7
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C8 - CB
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! CC - CF
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D0 - D3
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D4 - D7
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D8 - DB
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! DC - DF
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E0 - E3
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E4 - E7
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E8 - EB
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! EC - EF
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F0 - F3
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F4 - F7
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F8 - FB
-  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! FC - FF
-
-/*
- *  This is the hard reset code.
- */
-
-#define PSR_INIT   0x10c0       /* Disable traps, set s and ps */
-#define WIM_INIT   2
-#define STACK_SIZE 16 * 1024
-
-        PUBLIC(hard_reset)
-SYM(hard_reset):
-
-        set     SYM(trap_table), %g1           ! Initialize TBR
-        mov     %g1, %tbr
-
-	set	(SYM(rdb_start)), %g6	   ! End of work-space area
-	st	%sp, [%g6]
-
-
-/* Check if MEC is initialised. If not, this means that we are
-   running on the simulator. Initiate some of the parameters
-   that are done by the boot-prom otherwise.
-*/
-
-        set     SYM(ERC32_MEC), %g3  ! g3 = base address of peripherals
-	ld	[%g3], %g2		
-	set	0xfe080000, %g1
-	andcc	%g1, %g2, %g0
- 	bne	2f
- 
- /* Set the correct memory size in MEC memory config register */
- 
- 	set	SYM(PROM_SIZE), %l0	
- 	set	0, %l1
- 	srl	%l0, 18, %l0
-1:
- 	tst	%l0
- 	srl	%l0, 1, %l0
- 	bne,a	1b
- 	inc	%l1
- 	sll	%l1, 8, %l1
- 
- 	set	SYM(RAM_SIZE), %l0	
- 	srl	%l0, 19, %l0
-1:
- 	tst	%l0
- 	srl	%l0, 1, %l0
- 	bne,a	1b
- 	inc	%l1
- 	sll	%l1, 10, %l1
- 
-                                           ! set the Memory Configuration
-        st     %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
-          
- 	set	SYM(RAM_START), %l1  ! Cannot use RAM_END due to bug in linker
- 	set	SYM(RAM_SIZE), %l2
- 	add	%l1, %l2, %sp
- 	st	%sp, [%g6]	
-
-
-	set	SYM(CLOCK_SPEED), %g6	! Use 14 MHz in simulator
-	set	14, %g1
-	st	%g1, [%g6]
-
-/* Common initialisation */
-2:
-        set     WIM_INIT, %g1           ! Initialize WIM
-        mov     %g1, %wim               
-
-        set     PSR_INIT, %g1
-        wr      %g1, 0x20, %psr         ! enable traps
-
-        nop
-        nop
-        nop
-
-        sethi   %hi(stack_space + STACK_SIZE), %g1
-        or      %g1,%lo(stack_space + STACK_SIZE),%g1 
-                                        ! g1 = top of stack
-        mov     %g1, %sp                ! Set stack pointer
-        mov     %sp, %fp                ! Set frame pointer
-        nop
-
-        /*
-         *  Copy the initialized data to RAM
-         *
-         *  FROM:   _endtext 
-         *  TO:     _data_start 
-         *  LENGTH: (__bss_start - _data_start) bytes
-         */
- 
-
-        sethi %hi(_endtext),%g2
-        or    %g2,%lo(_endtext),%g2     ! g2 = start of initialized data in ROM
-
-        sethi %hi(_data_start),%g3
-        or    %g3,%lo(_data_start),%g3  ! g3 = start of initialized data in RAM
-
-        sethi %hi(__bss_start),%g4
-        or    %g4,%lo(__bss_start),%g4  ! g4 = end of initialized data in RAM
-
-	cmp   %g2, %g3
-	be    1f
-	nop
-
-copy_data:
-        ldd   [ %g2 ], %g6
-        std   %g6 , [ %g3 ]             ! copy this double word
-        add   %g3, 8, %g3               ! bump the destination pointer
-        add   %g2, 8, %g2               ! bump the source pointer
-        cmp   %g3, %g4                  ! Is the pointer past the end of dest?
-        bl    copy_data
-        nop
-
-        /* clear the bss */
-1:
-
-        sethi %hi(_edata),%g2
-        or    %g2,%lo(_edata),%g2       ! g2 = start of bss
-        sethi %hi(_end),%g3
-        or    %g3,%lo(_end),%g3         ! g3 = end of bss
-        mov   %g0,%g1                   ! so std has two zeros
-zerobss:
-        std    %g0,[%g2]
-        add    %g2,8,%g2
-        cmp    %g2,%g3
-        bleu,a zerobss
-        nop
-
-        mov     %0, %o2                 ! environ
-        mov     %0, %o1                 ! argv
-        mov     %0, %o0                 ! argc
-        call    SYM(boot_card)
-        sub     %sp, 0x60, %sp          ! room for boot_card to save args
-        nop
-
-        PUBLIC(BSP_fatal_return)
-SYM(BSP_fatal_return):
-	mov	1, %g1
-        ta      0                       ! Halt if _main returns ...
-        nop
-
-        /*
-         *  There does not seem to be a way to get this aligned AND
-         *  in the BSS.
-         */
- 
-        .align  32
-        .comm   stack_space, STACK_SIZE
-
-/* end of file */
Index: c/src/lib/libbsp/sparc/erc32/startup/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/startup/Makefile.am	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/startup/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -5,5 +5,5 @@
 AUTOMAKE_OPTIONS = foreign 1.4
 
-VPATH = @srcdir@:@srcdir@/../../../shared
+VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
 
 PGM = $(ARCH)/startup.rel
@@ -13,5 +13,8 @@
 C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
 
-OBJS = $(C_O_FILES)
+S_FILES = boardinit.S
+S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
+
+OBJS = $(C_O_FILES) $(S_O_FILES)
 
 include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
@@ -38,5 +41,5 @@
 .PRECIOUS: $(PGM)
 
-EXTRA_DIST = bspclean.c bspstart.c linkcmds setvec.c spurious.c
+EXTRA_DIST = linkcmds setvec.c spurious.c boardinit.S
 
 include $(top_srcdir)/../../../../../../automake/local.am
Index: c/src/lib/libbsp/sparc/erc32/startup/boardinit.S
===================================================================
--- c/src/lib/libbsp/sparc/erc32/startup/boardinit.S	(revision 270042352bb97ab71be15205deded8fe44199b1e)
+++ c/src/lib/libbsp/sparc/erc32/startup/boardinit.S	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -0,0 +1,84 @@
+/*
+ *  boardinit.s
+ *
+ *  Initialise various ERC32 registers
+ *
+ *  $Id$
+ */
+
+#include <asm.h>
+#include <erc32.h>
+
+        .global __bsp_board_init
+__bsp_board_init:
+
+
+/* Check if MEC is initialised. If not, this means that we are
+   running on the simulator. Initiate some of the parameters
+   that are done by the boot-prom otherwise.
+*/
+
+        set     SYM(ERC32_MEC), %g3  ! g3 = base address of peripherals
+	ld	[%g3], %g2		
+	set	0xfe080000, %g1
+	andcc	%g1, %g2, %g0
+ 	bne	2f
+ 
+ /* Stop the watchdog */
+
+	st	%g0, [%g3 + SYM(ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET)]
+
+ /* Set zero waitstates */
+
+	st	%g0, [%g3 + SYM(ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET)]
+
+ /* Set the correct memory size in MEC memory config register */
+ 
+ 	set	SYM(PROM_SIZE), %l0	
+ 	set	0, %l1
+ 	srl	%l0, 18, %l0
+1:
+ 	tst	%l0
+ 	srl	%l0, 1, %l0
+ 	bne,a	1b
+ 	inc	%l1
+ 	sll	%l1, 8, %l1
+ 
+ 	set	SYM(RAM_SIZE), %l0	
+ 	srl	%l0, 19, %l0
+1:
+ 	tst	%l0
+ 	srl	%l0, 1, %l0
+ 	bne,a	1b
+ 	inc	%l1
+ 	sll	%l1, 10, %l1
+ 
+                                           ! set the Memory Configuration
+        st     %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
+          
+ 	set	SYM(RAM_START), %l1  ! Cannot use RAM_END due to bug in linker
+ 	set	SYM(RAM_SIZE), %l2
+ 	add	%l1, %l2, %sp
+
+	set	SYM(CLOCK_SPEED), %g6	! Use 14 MHz in simulator
+	set	14, %g1
+	st	%g1, [%g6]
+
+2:
+
+ /* Initialise timer */
+
+ 	set	SYM(_ERC32_MEC_Timer_Control_Mirror), %l2
+	st	%g0, [%l2]
+	st	%g0, [%g3 + SYM(ERC32_MEC_TIMER_CONTROL_OFFSET)]
+
+ /* Enable power-down */
+
+	ld	[%g3 + SYM(ERC32_MEC_CONTROL_OFFSET)], %l2
+	or	%l2, ERC32_CONFIGURATION_POWER_DOWN_ALLOWED, %l2
+	st	%l2, [%g3 + SYM(ERC32_MEC_CONTROL_OFFSET)]
+
+	retl
+	nop
+
+/* end of file */
Index: c/src/lib/libbsp/sparc/erc32/startup/bspclean.c
===================================================================
--- c/src/lib/libbsp/sparc/erc32/startup/bspclean.c	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ 	(revision )
@@ -1,37 +1,0 @@
-/*  bspclean.c
- *
- *  This file contains cleanup code executed when the application exits.
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
- *  Agency (ESA).
- *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
- *  European Space Agency.
- *
- *  $Id$
- */
-
-#include <bsp.h>
-
-/*
- * The app has "exited" (rtems_shutdown_executive returns control to main)
- */
-
-void bsp_cleanup( void )
-{
-    /*
-     * "halt" by trapping to the simulator command line.
-     * set %g1 to 1 to detect clean exit.
-     */
-
-
-  asm volatile( "mov 1, %g1; ta 0" );
-}
Index: c/src/lib/libbsp/sparc/erc32/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/sparc/erc32/startup/bspstart.c	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ 	(revision )
@@ -1,283 +1,0 @@
-/*
- *  This set of routines starts the application.  It includes application,
- *  board, and monitor specific initialization and configuration.
- *  The generic CPU dependent initialization has been performed
- *  before any of these are invoked.
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
- *  Agency (ESA).
- *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
- *  European Space Agency.
- *
- *  $Id$
- */
-
-#include <string.h>
-
-#include <bsp.h>
-#include <rtems/libio.h>
-#include <rtems/libcsupport.h>
-
-/*
- *  The original table from the application and our copy of it with
- *  some changes.
- */
- 
-extern rtems_configuration_table  Configuration;
-rtems_configuration_table         BSP_Configuration;
-
-rtems_cpu_table   Cpu_table;
-
-/*
- *  Tells us where to put the workspace in case remote debugger is present.
- */
-
-extern rtems_unsigned32  rdb_start;
-
-/*
- *  Mirror of the Timer Control Register
- */
-
-unsigned32 _ERC32_MEC_Timer_Control_Mirror;
-
-/*
- * Amount to increment itimer by each pass
- * It is a variable instead of a #define to allow the 'looptest'
- * script to bump it without recompiling rtems
- *
- *  NOTE:  This is based on the PA-RISC simulator.  I don't know if we
- *         can actually pull this trick on the SPARC simulator.
- */
-
-rtems_unsigned32 CPU_SPARC_CLICKS_PER_TICK;
-
-#if SIMSPARC_FAST_IDLE
-
-/*
- * Many of the tests are very slow on the simulator because they have
- * have 5 second delays hardwired in.
- *
- * Try to speed those tests up by speeding up the clock when in the idle task.
- *
- *  NOTE:  At the current setting, 5 second delays in the tests take 
- *         approximately 5 seconds of wall time. 
- */
-
-rtems_extension fast_idle_switch_hook(
-  rtems_tcb *current_task,
-  rtems_tcb *heir_task
-)
-{
-    static rtems_unsigned32 normal_clock = ~0;
-    static rtems_unsigned32 fast_clock;
-
-    /* init our params on first call */
-    if (normal_clock == ~0)
-    {
-        normal_clock = CPU_SPARC_CLICKS_PER_TICK;
-        fast_clock = CPU_SPARC_CLICKS_PER_TICK / 0x08;
-        if (fast_clock == 0)    /* handle pathological case */
-            fast_clock++;
-    }
-
-    /*
-     * Run the clock faster when idle is in place.
-     */
-
-    if (heir_task == _Thread_Idle)
-        CPU_SPARC_CLICKS_PER_TICK = fast_clock;
-    else if (current_task == _Thread_Idle)
-        CPU_SPARC_CLICKS_PER_TICK = normal_clock;
-}
-
-#endif
-
-/*
- *  Use the shared implementations of the following routines
- */
- 
-void bsp_postdriver_hook(void);
-void bsp_libc_init( void *, unsigned32, int );
-extern void bsp_spurious_initialize();
-
-/*
- *  bsp_pretasking_hook
- *
- *  BSP pretasking hook.  Called just before drivers are initialized.
- *  Used to setup libc and install any BSP extensions.
- */
-
-void bsp_pretasking_hook(void)
-{
-  extern int end;
-  rtems_unsigned32 heap_start;
-  rtems_unsigned32 heap_size;
-
-  heap_start = (rtems_unsigned32) &end;
-  if (heap_start & (CPU_ALIGNMENT-1))
-    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
-
-  heap_size = BSP_Configuration.work_space_start - (void *)&end;
-  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
-
-  bsp_libc_init((void *) heap_start, heap_size, 0);
-
-
-#if SIMSPARC_FAST_IDLE
-  /*
-   *  Install the fast idle task switch extension
-   *
-   *  On MP systems, might not want to do this; it confuses at least
-   *  one test (mp06) on the PA-RISC simulator
-   */
-
-#if 0
-  if (BSP_Configuration.User_multiprocessing_table == 0)
-#endif
-  {
-    rtems_extensions_table  fast_idle_extension;
-    rtems_id                extension_id;
-    rtems_status_code       rc;
-
-    memset(&fast_idle_extension, 0, sizeof(fast_idle_extension));
-
-    fast_idle_extension.thread_switch  = fast_idle_switch_hook;
-
-    rc = rtems_extension_create(
-      rtems_build_name('F', 'D', 'L', 'E'),
-      &fast_idle_extension, 
-      &extension_id
-    );
-    if (rc != RTEMS_SUCCESSFUL)
-      rtems_fatal_error_occurred(rc);
-  }
-#endif
-
-#ifdef RTEMS_DEBUG
-  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
-#endif
-
-  bsp_spurious_initialize();
-}
-
-/*
- *  ERC32_Idle_thread_body
- *
- *  ERC32 specific idle task that enters low power mode.
- */
-
-void ERC32_Idle_thread_body( void ) 
-{
-  while (1) {
-    ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
-  }
-}
-
-
-
-/*
- *  bsp_start
- *
- *  This routine does the bulk of the system initialization.
- */
-
-void bsp_start( void )
-{
-  unsigned char *work_space_start;
-
-  /* Check if MEC is initialised */
-
-  if (!(ERC32_MEC.Control & 0xfe080000)) {
-
-  /*
-   *  DISABLE THE HARDWARE WATCHDOG!!!
-   */
-
-    ERC32_MEC.Watchdog_Trap_Door_Set = 0;          /* value is irrelevant */
-
-  /*
-   *  Reduce the number of wait states to 0 for all memory areas.
-   */
-
-    ERC32_MEC.Wait_State_Configuration = 0; 
-
-  }
-
-  /*
-   *  Initialize the mirror of the Timer Control register.
-   */
-
-  _ERC32_MEC_Timer_Control_Mirror = 0;
-  ERC32_MEC.Timer_Control = 0;
-
-  ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
-  
-  /*
-   * Set up our hooks
-   * Make sure libc_init is done before drivers initialized so that
-   * they can use atexit()
-   */
-
-  Cpu_table.pretasking_hook = bsp_pretasking_hook;    /* init libc, etc. */
-  Cpu_table.postdriver_hook = bsp_postdriver_hook;
-
-  /*
-   *  SIS does zero out memory BUT only when IT begins execution.  Thus
-   *  if we want to have a clean slate in the workspace each time we
-   *  begin execution of OUR application, then we must zero the workspace.
-   */
-  Cpu_table.do_zero_of_workspace = TRUE;
-
-  /*
-   *  ERC32 specific idle task.
-   */
-
-  Cpu_table.idle_task = ERC32_Idle_thread_body;
-
-  /*
-   *  This should be enough interrupt stack.
-   */
-
-  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
-
-  work_space_start = 
-    (unsigned char *)rdb_start - BSP_Configuration.work_space_size;
-
-  if ( work_space_start <= (unsigned char *)&end ) {
-    DEBUG_puts( "bspstart: Not enough RAM!!!\n" );
-    BSP_fatal_return();
-  }
-
-  BSP_Configuration.work_space_start = work_space_start;
-
-#if SIMSPARC_FAST_IDLE
-  /*
-   * Add 1 extension for fast idle
-   */
-
-  BSP_Configuration.maximum_extensions++;
-#endif
-
-  /*
-   * Add 1 extension for MPCI_fatal
-   */
-
-  if (BSP_Configuration.User_multiprocessing_table)
-    BSP_Configuration.maximum_extensions++;
-
-  /*
-   * Set the "clicks per tick" for the simulator
-   *  used by XXX/clock/clock.c to schedule interrupts
-   */
-
-  CPU_SPARC_CLICKS_PER_TICK = BSP_Configuration.microseconds_per_tick;
-}
Index: c/src/lib/libbsp/sparc/erc32/startup/setvec.c
===================================================================
--- c/src/lib/libbsp/sparc/erc32/startup/setvec.c	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/startup/setvec.c	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -61,2 +61,11 @@
 }
 
+/* ERC32 power-down function */
+
+void _CPU_Thread_Idle_body( void )
+{
+  while (1) {
+    ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
+  }
+}
+
Index: c/src/lib/libbsp/sparc/erc32/wrapup/Makefile.am
===================================================================
--- c/src/lib/libbsp/sparc/erc32/wrapup/Makefile.am	(revision feead2261885d85a23f0cc4d10b40a5878c0c705)
+++ c/src/lib/libbsp/sparc/erc32/wrapup/Makefile.am	(revision 270042352bb97ab71be15205deded8fe44199b1e)
@@ -5,5 +5,10 @@
 AUTOMAKE_OPTIONS = foreign 1.4
 
-BSP_PIECES = startup console clock timer gnatsupp
+# We only build the networking device driver if HAS_NETWORKING was defined
+if HAS_NETWORKING
+NETWORKING_DRIVER = erc32sonic
+endif
+
+BSP_PIECES = startup console clock timer gnatsupp $(NETWORKING_DRIVER)
 # pieces to pick up out of libcpu/sparc
 CPU_PIECES = reg_win syscall
