Changeset 26853a06 in rtems

Timestamp:

03/15/23 13:41:53 (7 months ago)

Author:

Alan Cudmore <alan.cudmore@…>

Branches:

master

Children:

4021b87

Parents:

ca1c4e70

git-author:

Alan Cudmore <alan.cudmore@…> (03/15/23 13:41:53)

git-committer:

Joel Sherrill <joel@…> (03/28/23 19:04:04)

Message:

bsps/riscv: add riscv/kendrytek210 BSP variant source changes

This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.

Updates #4876

Location:

bsps/riscv/riscv

Files:

• config/kendrytek210.cfg (added)
• console/console-config.c (modified) (5 diffs)
• console/fe310-uart.c (modified) (1 diff)
• include/bsp.h (modified) (1 diff)
• include/bsp/k210.h (added)
• include/bsp/riscv.h (modified) (1 diff)
• start/bspstart.c (modified) (2 diffs)

bsps/riscv/riscv/console/console-config.c

@@ -56 +56 @@
 #include <string.h>
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
 #include <bsp/fe310-uart.h>
 static fe310_uart_context fe310_uart_instance;
@@ -240 +240 @@
 #endif
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
     if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) {
       fe310_uart_context *ctx;
@@ -256 +256 @@
       }
 
-      rtems_termios_device_context_initialize(&ctx->base, "FE310UART");
+      rtems_termios_device_context_initialize(&ctx->base, "SIFIVEUART");
     }
 #endif
@@ -291 +291 @@
 #endif
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
   fe310_uart_context *ctx;
   char fe310_path[] = "/dev/ttyS0";
@@ -327 +327 @@
 #endif
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
   ctx = &fe310_uart_instance;
   rtems_termios_device_install(

bsps/riscv/riscv/console/fe310-uart.c

@@ -54 +54 @@
   size_t i;
 
-  ctx->regs->div = riscv_get_core_frequency() / 115200 - 1;
+  ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF;
   ctx->regs->txctrl |= 1;
   ctx->regs->rxctrl |= 1;

bsps/riscv/riscv/include/bsp.h

@@ -61 +61 @@
 #include <rtems/devnull.h>
 
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+   #include <bsp/k210.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {

bsps/riscv/riscv/include/bsp/riscv.h

@@ -57 +57 @@
 #endif
 
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void);
+#endif
+
 #ifdef __cplusplus
 }

bsps/riscv/riscv/start/bspstart.c

@@ -210 +210 @@
   }
 #endif
+
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+  uint32_t cpu_clock;
+
+  cpu_clock = k210_get_frequency();
+  return cpu_clock;
+#else
   return 0;
+#endif
+
 }
 
@@ -223 +232 @@
   return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);
 }
+
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void)
+{
+  k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;
+  uint32_t cpu_clock = 0;
+  uint32_t clk_freq;
+  uint32_t pll0, nr, nf, od;
+  uint32_t node;
+  const char *fdt;
+  const fdt32_t *val;
+  int len;
+
+  fdt = bsp_fdt_get();
+  node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
+  val = fdt_getprop(fdt, node, "clock-frequency", &len);
+  if (val != NULL && len == 4) {
+    clk_freq = fdt32_to_cpu(*val);
+
+    if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {
+       /* PLL0 selected */
+       pll0 = sysctl->pll0;
+       nr = PLL_CLK_R(pll0) + 1;
+       nf = PLL_CLK_F(pll0) + 1;
+       od = PLL_CLK_OD(pll0) + 1;
+       cpu_clock = (clk_freq / nr * nf / od)/2;
+    } else {
+       /* OSC selected */
+       cpu_clock = clk_freq;
+    }
+  }
+  return cpu_clock;
+}
+#endif
 
 void bsp_start(void)