Changeset 2628ebb in rtems


Ignore:
Timestamp:
Nov 2, 2005, 11:25:39 PM (15 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
912ab10e
Parents:
408bb71
Message:

2005-11-02 straumanatslacdotstanford.edu

  • rtems/powerpc/registers.h: recognize mpc7457 CPU; added definitions for high bats (#4..7) on 7450 CPUs
Location:
cpukit/score/cpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/ChangeLog

    r408bb71 r2628ebb  
     12005-11-02      straumanatslacdotstanford.edu
     2 
     3    * rtems/powerpc/registers.h: recognize mpc7457 CPU; added definitions
     4    for high bats (#4..7) on 7450 CPUs
     5 
    162005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
    27
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    r408bb71 r2628ebb  
    2424
    2525/* Bit encodings for Machine State Register (MSR) */
     26#define MSR_VE          (1<<25)         /* Alti-Vec enable (7400+) */
    2627#define MSR_POW         (1<<18)         /* Enable Power Management */
    2728#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
     
    4748/* Bit encodings for Hardware Implementation Register (HID0)
    4849   on PowerPC 603, 604, etc. processors (not 601). */
     50
     51/* WARNING: HID0/HID1 are *truely* implementation dependent!
     52 *          you *cannot* rely on the same bits to be present,
     53 *          at the same place or even in the same register
     54 *          on different CPU familys.
     55 *          E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the
     56 *          on the 7450s. IFFT is XBSEN on 7450 and so on...
     57 */
    4958#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
    5059#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
     
    6069#define HID0_PAR        (1<<24)
    6170#define HID0_DOZE       (1<<23)
     71/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !!          */
     72#define HID0_7455_HIGH_BAT_EN (1<<23)
     73
    6274#define HID0_NAP        (1<<22)
    6375#define HID0_SLEEP      (1<<21)
     
    6981#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
    7082#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
     83/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */
     84#define HID0_7455_XBSEN       (1<<8)
    7185#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
    7286#define HID0_BTIC       (1<<5)          /* Branch Target Instruction Cache [Enable] */
     
    122136#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
    123137#define IBAT3L  535
     138
     139/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
     140#define IBAT4U  560     /* Instruction BAT #0 Upper/Lower */
     141#define IBAT4L  561
     142#define IBAT5U  562     /* Instruction BAT #1 Upper/Lower */
     143#define IBAT5L  563
     144#define IBAT6U  564     /* Instruction BAT #2 Upper/Lower */
     145#define IBAT6L  565
     146#define IBAT7U  566     /* Instruction BAT #3 Upper/Lower */
     147#define IBAT7L  567
     148
    124149#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
    125150#define DBAT0L  537
     
    130155#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
    131156#define DBAT3L  543
     157
     158/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */
     159#define DBAT4U  568     /* Instruction BAT #0 Upper/Lower */
     160#define DBAT4L  569
     161#define DBAT5U  570     /* Instruction BAT #1 Upper/Lower */
     162#define DBAT5L  571
     163#define DBAT6U  572     /* Instruction BAT #2 Upper/Lower */
     164#define DBAT6L  573
     165#define DBAT7U  574     /* Instruction BAT #3 Upper/Lower */
     166#define DBAT7L  575
     167
    132168#define DMISS   976     /* TLB Lookup/Refresh registers */
    133169#define DCMP    977
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