Changeset 254b4450 in rtems for c


Ignore:
Timestamp:
04/01/97 23:07:52 (27 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
9a11e1f
Parents:
467eae4d
Message:

This set of changes is the build of what was required to convert to
GNU autoconf. This is the first large step in allowing an RTEMS
user to perform a one-tree build (per crossgcc FAQ) including RTEMS
in the build process. With this change RTEMS is configured in
built in the same style as the GNU tools, yet retains the basic
structure of its traditional Makefiles (ala Tony Bennett).
Jiri Gaisler (jgais@…) deserves (and received)
a big thank you for doing this.

There are still issues to be resolved but as of this commit, all target
which can be built on a linux host have been using a modified version
of the source Jiri submitted. This source was merged and most targets
built in the tree before this commit.

There are some issues which remain to be resolved but they are primarily
related to host OS dependencies, script issues, the use of gawk
for hack_specs, and the dependence on gcc snapshots. These will
be resolved.

Location:
c
Files:
432 added
8 edited

Legend:

Unmodified
Added
Removed
  • c/build-tools/src/unhex.c

    r467eae4d r254b4450  
    8989#define ERR_MASK   (ERR_ERRNO | ERR_FATAL | ERR_ABORT) /* all */
    9090
    91 #if (defined(sparc) && (sunos < 500))
    92 #define stol(p) strtol(p, (char **) NULL, 0)            /* Sunos */
     91#ifdef HAVE_STRTOUL
     92#define stol(p) strtoul(p, (char **) NULL, 0)
    9393#else
    94 #define stol(p) strtoul(p, (char **) NULL, 0)           /* Solaris */
     94#define stol(p) strtol(p, (char **) NULL, 0)
    9595#endif
    9696 
  • c/build-tools/unhex.c

    r467eae4d r254b4450  
    8989#define ERR_MASK   (ERR_ERRNO | ERR_FATAL | ERR_ABORT) /* all */
    9090
    91 #if (defined(sparc) && (sunos < 500))
    92 #define stol(p) strtol(p, (char **) NULL, 0)            /* Sunos */
     91#ifdef HAVE_STRTOUL
     92#define stol(p) strtoul(p, (char **) NULL, 0)
    9393#else
    94 #define stol(p) strtoul(p, (char **) NULL, 0)           /* Solaris */
     94#define stol(p) strtol(p, (char **) NULL, 0)
    9595#endif
    9696 
  • c/src/exec/score/cpu/hppa1.1/cpu_asm.s

    r467eae4d r254b4450  
    1 #
    2 # TODO:
    3 #       Context_switch needs to only save callee save registers
    4 #       I think this means can skip:    r1, r2, r19-29, r31
    5 #       Ref:     p 3-2 of Procedure Calling Conventions Manual
    6 #       This should be #ifndef DEBUG so that debugger has
    7 #       accurate visibility into all registers
    8 #
    9 #  This file contains the assembly code for the HPPA implementation
    10 #  of RTEMS.
    11 #
    12 #  COPYRIGHT (c) 1994,95 by Division Incorporated
    13 #
    14 #  To anyone who acknowledges that this file is provided "AS IS"
    15 #  without any express or implied warranty:
    16 #      permission to use, copy, modify, and distribute this file
    17 #      for any purpose is hereby granted without fee, provided that
    18 #      the above copyright notice and this notice appears in all
    19 #      copies, and that the name of Division Incorporated not be
    20 #      used in advertising or publicity pertaining to distribution
    21 #      of the software without specific, written prior permission.
    22 #      Division Incorporated makes no representations about the
    23 #      suitability of this software for any purpose.
    24 #
    25 #  $Id$
    26 #
     1/*
     2 * TODO:
     3 *       Context_switch needs to only save callee save registers
     4 *       I think this means can skip:    r1, r2, r19-29, r31
     5 *       Ref:     p 3-2 of Procedure Calling Conventions Manual
     6 *       This should be #ifndef DEBUG so that debugger has
     7 *       accurate visibility into all registers
     8 *
     9 *  This file contains the assembly code for the HPPA implementation
     10 *  of RTEMS.
     11 *
     12 *  COPYRIGHT (c) 1994,95 by Division Incorporated
     13 *
     14 *  To anyone who acknowledges that this file is provided "AS IS"
     15 *  without any express or implied warranty:
     16 *      permission to use, copy, modify, and distribute this file
     17 *      for any purpose is hereby granted without fee, provided that
     18 *      the above copyright notice and this notice appears in all
     19 *      copies, and that the name of Division Incorporated not be
     20 *      used in advertising or publicity pertaining to distribution
     21 *      of the software without specific, written prior permission.
     22 *      Division Incorporated makes no representations about the
     23 *      suitability of this software for any purpose.
     24 *
     25 *  $Id$
     26 */
    2727
    2828#include <rtems/score/hppa.h>
     
    4040        .SUBSPA $CODE$
    4141
    42 #
    43 # Special register usage for context switch and interrupts
    44 # Stay away from %cr28 which is used for TLB misses on 72000
    45 #
     42/*
     43 * Special register usage for context switch and interrupts
     44 * Stay away from %cr28 which is used for TLB misses on 72000
     45 */
    4646
    4747isr_arg0           .reg    %cr24
     
    4949isr_r8             .reg    %cr26
    5050
    51 #
    52 # Interrupt stack frame looks like this
    53 #
    54 #  offset                                   item
    55 # -----------------------------------------------------------------
    56 #   INTEGER_CONTEXT_OFFSET             Context_Control
    57 #   FP_CONTEXT_OFFSET                  Context_Control_fp
    58 #
    59 # It is padded out to a multiple of 64
    60 #
    61 
    62 
    63 PAGE^L
    64 #  void _Generic_ISR_Handler()
    65 #
    66 #  This routine provides the RTEMS interrupt management.
    67 #
    68 #   We jump here from the interrupt vector.
    69 #   The HPPA hardware has done some stuff for us:
    70 #       PSW saved in IPSW
    71 #       PSW set to 0
    72 #       PSW[E] set to default (0)
    73 #       PSW[M] set to 1 iff this is HPMC
    74 #
    75 #       IIA queue is frozen (since PSW[Q] is now 0)
    76 #       privilege level promoted to 0
    77 #       IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap
    78 #       registers GR  1,8,9,16,17,24,25 copied to shadow regs
    79 #                 SHR 0 1 2  3  4  5  6
    80 #
    81 #   Our vector stub (in the BSP) MUST have done the following: 
    82 #
    83 #   a) Saved the original %r9 into %isr_r9 (%cr25)
    84 #   b) Placed the vector number in %r9
    85 #   c) Was allowed to also destroy $isr_r8 (%cr26),
    86 #      but the stub was NOT allowed to destroy any other registers.
    87 #
    88 #   The typical stub sequence (in the BSP) should look like this:
    89 #
    90 #   a)     mtctl   %r9,isr_r9     ; (save r9 in cr25)
    91 #   b)     ldi     vector,%r9     ; (load constant vector number in r9)
    92 #   c)     mtctl   %r8,isr_r8     ; (save r8 in cr26)
    93 #   d)     ldil    L%MY_BSP_first_level_interrupt_handler,%r8
    94 #   e)     ldo     R%MY_BSP_first_level_interrupt_handler(%r8),%r8
    95 #                                 ; (point to BSP raw handler table)
    96 #   f)     ldwx,s  %r9(%r8),%r8   ; (load value from raw handler table)
    97 #   g)     bv      0(%r8)         ; (call raw handler: _Generic_ISR_Handler)
    98 #   h)     mfctl   isr_r8,%r8     ; (restore r8 from cr26 in delay slot)
    99 #
    100 #   Optionally, steps (c) thru (h) _could_ be replaced with a single
    101 #          bl,n    _Generic_ISR_Handler,%r0
    102 #
    103 #
    104 #
     51/*
     52 * Interrupt stack frame looks like this
     53 *
     54 *  offset                                   item
     55 * -----------------------------------------------------------------
     56 *   INTEGER_CONTEXT_OFFSET             Context_Control
     57 *   FP_CONTEXT_OFFSET                  Context_Control_fp
     58 *
     59 * It is padded out to a multiple of 64
     60 */
     61
     62
     63/*PAGE^L
     64 *  void _Generic_ISR_Handler()
     65 *
     66 *  This routine provides the RTEMS interrupt management.
     67 *
     68 *   We jump here from the interrupt vector.
     69 *   The HPPA hardware has done some stuff for us:
     70 *       PSW saved in IPSW
     71 *       PSW set to 0
     72 *       PSW[E] set to default (0)
     73 *       PSW[M] set to 1 iff this is HPMC
     74 *
     75 *       IIA queue is frozen (since PSW[Q] is now 0)
     76 *       privilege level promoted to 0
     77 *       IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap
     78 *       registers GR  1,8,9,16,17,24,25 copied to shadow regs
     79 *                 SHR 0 1 2  3  4  5  6
     80 *
     81 *   Our vector stub (in the BSP) MUST have done the following: 
     82 *
     83 *   a) Saved the original %r9 into %isr_r9 (%cr25)
     84 *   b) Placed the vector number in %r9
     85 *   c) Was allowed to also destroy $isr_r8 (%cr26),
     86 *      but the stub was NOT allowed to destroy any other registers.
     87 *
     88 *   The typical stub sequence (in the BSP) should look like this:
     89 *
     90 *   a)     mtctl   %r9,isr_r9     ; (save r9 in cr25)
     91 *   b)     ldi     vector,%r9     ; (load constant vector number in r9)
     92 *   c)     mtctl   %r8,isr_r8     ; (save r8 in cr26)
     93 *   d)     ldil    L%MY_BSP_first_level_interrupt_handler,%r8
     94 *   e)     ldo     R%MY_BSP_first_level_interrupt_handler(%r8),%r8
     95 *                                 ; (point to BSP raw handler table)
     96 *   f)     ldwx,s  %r9(%r8),%r8   ; (load value from raw handler table)
     97 *   g)     bv      0(%r8)         ; (call raw handler: _Generic_ISR_Handler)
     98 *   h)     mfctl   isr_r8,%r8     ; (restore r8 from cr26 in delay slot)
     99 *
     100 *   Optionally, steps (c) thru (h) _could_ be replaced with a single
     101 *          bl,n    _Generic_ISR_Handler,%r0
     102 *
     103 *
     104 */
    105105        .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0
    106106_Generic_ISR_Handler:
     
    111111        mtctl     arg0, isr_arg0
    112112
    113 # save interrupt state
     113/*
     114 * save interrupt state
     115 */
    114116        mfctl     ipsw, arg0
    115117        stw       arg0, IPSW_OFFSET(sp)
     
    131133        stw       arg0, SAR_OFFSET(sp)
    132134
    133 #
    134 # Build an interrupt frame to hold the contexts we will need.
    135 # We have already saved the interrupt items on the stack
    136 
    137 # At this point the following registers are damaged wrt the interrupt
    138 #  reg    current value        saved value
    139 # ------------------------------------------------
    140 #  arg0   scratch               isr_arg0  (cr24)
    141 #  r9     vector number         isr_r9    (cr25)
    142 #
    143 # Point to beginning of integer context and
    144 # save the integer context
     135/*
     136 * Build an interrupt frame to hold the contexts we will need.
     137 * We have already saved the interrupt items on the stack
     138 *
     139 * At this point the following registers are damaged wrt the interrupt
     140 *  reg    current value        saved value
     141 * ------------------------------------------------
     142 *  arg0   scratch               isr_arg0  (cr24)
     143 *  r9     vector number         isr_r9    (cr25)
     144 *
     145 * Point to beginning of integer context and
     146 * save the integer context
     147 */
    145148        stw         %r1,R1_OFFSET(sp)
    146149        stw         %r2,R2_OFFSET(sp)
     
    151154        stw         %r7,R7_OFFSET(sp)
    152155        stw         %r8,R8_OFFSET(sp)
    153 # skip r9
     156/*
     157 * skip r9
     158 */
    154159        stw         %r10,R10_OFFSET(sp)
    155160        stw         %r11,R11_OFFSET(sp)
     
    168173        stw         %r24,R24_OFFSET(sp)
    169174        stw         %r25,R25_OFFSET(sp)
    170 # skip arg0
     175/*
     176 * skip arg0
     177 */
    171178        stw         %r27,R27_OFFSET(sp)
    172179        stw         %r28,R28_OFFSET(sp)
     
    175182        stw         %r31,R31_OFFSET(sp)
    176183
    177 # Now most registers are available since they have been saved
    178 #
    179 # The following items are currently wrong in the integer context
    180 #  reg    current value        saved value
    181 # ------------------------------------------------
    182 #  arg0   scratch               isr_arg0  (cr24)
    183 #  r9     vector number         isr_r9    (cr25)
    184 #
    185 # Fix them
     184/* Now most registers are available since they have been saved
     185 *
     186 * The following items are currently wrong in the integer context
     187 *  reg    current value        saved value
     188 * ------------------------------------------------
     189 *  arg0   scratch               isr_arg0  (cr24)
     190 *  r9     vector number         isr_r9    (cr25)
     191 *
     192 * Fix them
     193 */
    186194
    187195         mfctl      isr_arg0,%r3
     
    191199         stw        %r3,R9_OFFSET(sp)
    192200
    193 #
    194 # At this point we are done with isr_arg0, and isr_r9 control registers
    195 #
    196 # Prepare to re-enter virtual mode
    197 # We need Q in case the interrupt handler enables interrupts
    198 #
     201/*
     202 * At this point we are done with isr_arg0, and isr_r9 control registers
     203 *
     204 * Prepare to re-enter virtual mode
     205 * We need Q in case the interrupt handler enables interrupts
     206 */
    199207
    200208        ldil      L%CPU_PSW_DEFAULT, arg0
     
    202210        mtctl     arg0, ipsw
    203211
    204 # Now jump to "rest_of_isr_handler" with the rfi
    205 # We are assuming the space queues are all correct already
     212/*
     213 * Now jump to "rest_of_isr_handler" with the rfi
     214 * We are assuming the space queues are all correct already
     215 */
    206216
    207217        ldil      L%rest_of_isr_handler, arg0
     
    214224        nop
    215225
    216 # At this point we are back in virtual mode and all our
    217 #  normal addressing is once again ok.
    218 #
    219 #  It is now ok to take an exception or trap
    220 #
     226/*
     227 * At this point we are back in virtual mode and all our
     228 *  normal addressing is once again ok.
     229 *
     230 *  It is now ok to take an exception or trap
     231 */
    221232
    222233rest_of_isr_handler:
    223234
    224 # Point to beginning of float context and
    225 # save the floating point context -- doing whatever patches are necessary
     235/*
     236 * Point to beginning of float context and
     237 * save the floating point context -- doing whatever patches are necessary
     238 */
     239
    226240        .call ARGW0=GR
    227241        bl          _CPU_Save_float_context,%r2
    228242        ldo         FP_CONTEXT_OFFSET(sp),arg0
    229243
    230 # save the ptr to interrupt frame as an argument for the interrupt handler
     244/*
     245 * save the ptr to interrupt frame as an argument for the interrupt handler
     246 */
     247
    231248        copy        sp, arg1
    232249
    233 # Advance the frame to point beyond all interrupt contexts (integer & float)
    234 # this also includes the pad to align to 64byte stack boundary
     250/*
     251 * Advance the frame to point beyond all interrupt contexts (integer & float)
     252 * this also includes the pad to align to 64byte stack boundary
     253 */
    235254        ldo         CPU_INTERRUPT_FRAME_SIZE(sp), sp
    236255
    237 #    r3  -- &_ISR_Nest_level
    238 #    r5  -- value _ISR_Nest_level
    239 #    r4  -- &_Thread_Dispatch_disable_level
    240 #    r6  -- value _Thread_Dispatch_disable_level
    241 #    r9  -- vector number
     256/*
     257 *    r3  -- &_ISR_Nest_level
     258 *    r5  -- value _ISR_Nest_level
     259 *    r4  -- &_Thread_Dispatch_disable_level
     260 *    r6  -- value _Thread_Dispatch_disable_level
     261 *    r9  -- vector number
     262 */
    242263
    243264        .import   _ISR_Nest_level,data
     
    251272        ldw       0(%r4),%r6
    252273
    253 # increment interrupt nest level counter.  If outermost interrupt
    254 # switch the stack and squirrel away the previous sp.
     274/*
     275 * increment interrupt nest level counter.  If outermost interrupt
     276 * switch the stack and squirrel away the previous sp.
     277 */
    255278        addi      1,%r5,%r5
    256279        stw       %r5, 0(%r3)
    257280
    258 # compute and save new stack (with frame)
    259 # just in case we are nested -- simpler this way
     281/*
     282 * compute and save new stack (with frame)
     283 * just in case we are nested -- simpler this way
     284 */
    260285        comibf,=  1,%r5,stack_done
    261286        ldo       128(sp),%r7
    262287
    263 #
    264 # Switch to interrupt stack allocated by the interrupt manager (intr.c)
    265 #
     288/*
     289 * Switch to interrupt stack allocated by the interrupt manager (intr.c)
     290 */
    266291        .import   _CPU_Interrupt_stack_low,data
    267292        ldil      L%_CPU_Interrupt_stack_low,%r7
     
    270295
    271296stack_done:
    272 # save our current stack pointer where the "old sp" is supposed to be
     297/*
     298 * save our current stack pointer where the "old sp" is supposed to be
     299 */
    273300        stw       sp, -4(%r7)
    274 # and switch stacks (or advance old stack in nested case)
     301/*
     302 * and switch stacks (or advance old stack in nested case)
     303 */
    275304        copy      %r7, sp
    276305
    277 # increment the dispatch disable level counter.
     306/*
     307 * increment the dispatch disable level counter.
     308 */
    278309        addi      1,%r6,%r6
    279310        stw       %r6, 0(%r4)
    280311
    281 # load address of user handler
    282 # Note:  No error checking is done, it is assumed that the
    283 #        vector table contains a valid address or a stub
    284 #        spurious handler.
     312/*
     313 * load address of user handler
     314 * Note:  No error checking is done, it is assumed that the
     315 *        vector table contains a valid address or a stub
     316 *        spurious handler.
     317 */
    285318        .import   _ISR_Vector_table,data
    286319        ldil      L%_ISR_Vector_table,%r8
     
    288321        ldwx,s    %r9(%r8),%r8
    289322
    290 # invoke user interrupt handler
    291 # Interrupts are currently disabled, as per RTEMS convention
    292 # The handler has the option of re-enabling interrupts
    293 # NOTE:  can not use 'bl' since it uses "pc-relative" addressing
    294 #    and we are using a hard coded address from a table
    295 #  So... we fudge r2 ourselves (ala dynacall)
    296 #  arg0 = vector number, arg1 = ptr to rtems_interrupt_frame
     323/*
     324 * invoke user interrupt handler
     325 * Interrupts are currently disabled, as per RTEMS convention
     326 * The handler has the option of re-enabling interrupts
     327 * NOTE:  can not use 'bl' since it uses "pc-relative" addressing
     328 *    and we are using a hard coded address from a table
     329 *  So... we fudge r2 ourselves (ala dynacall)
     330 *  arg0 = vector number, arg1 = ptr to rtems_interrupt_frame
     331 */
    297332        copy      %r9, %r26
    298333        .call  ARGW0=GR, ARGW1=GR
     
    302337post_user_interrupt_handler:
    303338
    304 # Back from user handler(s)
    305 # Disable external interrupts (since the interrupt handler could
    306 # have turned them on) and return to the interrupted task stack (assuming
    307 # (_ISR_Nest_level == 0)
     339/*
     340 * Back from user handler(s)
     341 * Disable external interrupts (since the interrupt handler could
     342 * have turned them on) and return to the interrupted task stack (assuming
     343 * (_ISR_Nest_level == 0)
     344 */
    308345
    309346        rsm        HPPA_PSW_I + HPPA_PSW_R, %r0
    310347        ldw        -4(sp), sp
    311348
    312 #    r3  -- (most of) &_ISR_Nest_level
    313 #    r5  -- value _ISR_Nest_level
    314 #    r4  -- (most of) &_Thread_Dispatch_disable_level
    315 #    r6  -- value _Thread_Dispatch_disable_level
    316 #    r7  -- (most of) &_ISR_Signals_to_thread_executing
    317 #    r8  -- value _ISR_Signals_to_thread_executing
     349/*
     350 *    r3  -- (most of) &_ISR_Nest_level
     351 *    r5  -- value _ISR_Nest_level
     352 *    r4  -- (most of) &_Thread_Dispatch_disable_level
     353 *    r6  -- value _Thread_Dispatch_disable_level
     354 *    r7  -- (most of) &_ISR_Signals_to_thread_executing
     355 *    r8  -- value _ISR_Signals_to_thread_executing
     356 */
    318357
    319358        .import   _ISR_Nest_level,data
     
    328367        ldil       L%_ISR_Signals_to_thread_executing,%r7
    329368
    330 # decrement isr nest level
     369/*
     370 * decrement isr nest level
     371 */
    331372        addi      -1, %r5, %r5
    332373        stw       %r5, R%_ISR_Nest_level(%r3)
    333374
    334 # decrement dispatch disable level counter and, if not 0, go on
     375/*
     376 * decrement dispatch disable level counter and, if not 0, go on
     377 */
    335378        addi       -1,%r6,%r6
    336379        comibf,=   0,%r6,isr_restore
    337380        stw        %r6, R%_Thread_Dispatch_disable_level(%r4)
    338381
    339 # check whether or not a context switch is necessary
     382/*
     383 * check whether or not a context switch is necessary
     384 */
    340385        .import    _Context_Switch_necessary,data
    341386        ldil       L%_Context_Switch_necessary,%r8
     
    343388        comibf,=,n 0,%r8,ISR_dispatch
    344389
    345 # check whether or not a context switch is necessary because an ISR
    346 #    sent signals to the interrupted task
     390/*
     391 * check whether or not a context switch is necessary because an ISR
     392 *    sent signals to the interrupted task
     393 */
    347394        ldw        R%_ISR_Signals_to_thread_executing(%r7),%r8
    348395        comibt,=,n 0,%r8,isr_restore
    349396
    350397
    351 # OK, something happened while in ISR and we need to switch to a task
    352 # other than the one which was interrupted or the
    353 #    ISR_Signals_to_thread_executing case
    354 # We also turn on interrupts, since the interrupted task had them
    355 #   on (obviously :-) and Thread_Dispatch is happy to leave ints on.
    356 #
     398/*
     399 * OK, something happened while in ISR and we need to switch to a task
     400 * other than the one which was interrupted or the
     401 *    ISR_Signals_to_thread_executing case
     402 * We also turn on interrupts, since the interrupted task had them
     403 *   on (obviously :-) and Thread_Dispatch is happy to leave ints on.
     404 */
    357405
    358406ISR_dispatch:
     
    370418isr_restore:
    371419
    372 # enable interrupts during most of restore
     420/*
     421 * enable interrupts during most of restore
     422 */
    373423        ssm        HPPA_PSW_I, %r0
    374424
    375 # Get a pointer to beginning of our stack frame
     425/*
     426 * Get a pointer to beginning of our stack frame
     427 */
    376428        ldo        -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1
    377429
    378 # restore float
     430/*
     431 * restore float
     432 */
    379433        .call ARGW0=GR
    380434        bl         _CPU_Restore_float_context,%r2
     
    383437        copy       %arg1, %arg0
    384438
    385 #   ********** FALL THRU **********
    386 
    387 # Jump here from bottom of Context_Switch
    388 # Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self
    389 # restore interrupt state
    390 #
     439/*
     440 *   ********** FALL THRU **********
     441 */
     442
     443/*
     444 * Jump here from bottom of Context_Switch
     445 * Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self
     446 * restore interrupt state
     447 */
    391448
    392449        .EXPORT _CPU_Context_restore
    393450_CPU_Context_restore:
    394451
    395 #
    396 # restore integer state
    397 #
     452/*
     453 * restore integer state
     454 */
    398455        ldw         R1_OFFSET(arg0),%r1
    399456        ldw         R2_OFFSET(arg0),%r2
     
    420477        ldw         R23_OFFSET(arg0),%r23
    421478        ldw         R24_OFFSET(arg0),%r24
    422 # skipping r25; used as scratch register below
    423 # skipping r26 (arg0) until we are done with it
     479/*
     480 * skipping r25; used as scratch register below
     481 * skipping r26 (arg0) until we are done with it
     482 */
    424483        ldw         R27_OFFSET(arg0),%r27
    425484        ldw         R28_OFFSET(arg0),%r28
    426485        ldw         R29_OFFSET(arg0),%r29
    427 # skipping r30 (sp) until we turn off interrupts
     486/*
     487 * skipping r30 (sp) until we turn off interrupts
     488 */
    428489        ldw         R31_OFFSET(arg0),%r31
    429490
    430 # Turn off Q & R & I so we can write r30 and interrupt control registers
     491/*
     492 * Turn off Q & R & I so we can write r30 and interrupt control registers
     493 */
    431494        rsm        HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0
    432495
    433 # now safe to restore r30
     496/*
     497 * now safe to restore r30
     498 */
    434499        ldw         R30_OFFSET(arg0),%r30
    435500
     
    446511        mtctl      %r25, pcoq
    447512
    448 # Load r25 with interrupts off
     513/*
     514 * Load r25 with interrupts off
     515 */
    449516        ldw         R25_OFFSET(arg0),%r25
    450 # Must load r26 (arg0) last
     517/*
     518 * Must load r26 (arg0) last
     519 */
    451520        ldw         R26_OFFSET(arg0),%r26
    452521
     
    456525        .PROCEND
    457526
    458 #
    459 #  This section is used to context switch floating point registers.
    460 #  Ref:  6-35 of Architecture 1.1
    461 #
    462 #  NOTE:    since integer multiply uses the floating point unit,
    463 #           we have to save/restore fp on every trap.  We cannot
    464 #           just try to keep track of fp usage.
     527/*
     528 *  This section is used to context switch floating point registers.
     529 *  Ref:  6-35 of Architecture 1.1
     530 *
     531 *  NOTE:    since integer multiply uses the floating point unit,
     532 *           we have to save/restore fp on every trap.  We cannot
     533 *           just try to keep track of fp usage.
     534 */
    465535
    466536        .align 32
     
    550620        .PROCEND
    551621
    552 #
    553 # These 2 small routines are unused right now.
    554 # Normally we just go thru _CPU_Save_float_context (and Restore)
    555 #
    556 # Here we just deref the ptr and jump up, letting _CPU_Save_float_context
    557 #  do the return for us.
    558 #
     622/*
     623 * These 2 small routines are unused right now.
     624 * Normally we just go thru _CPU_Save_float_context (and Restore)
     625 *
     626 * Here we just deref the ptr and jump up, letting _CPU_Save_float_context
     627 *  do the return for us.
     628 */
     629
    559630        .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0
    560631_CPU_Context_save_fp:
     
    578649
    579650
    580 #  void _CPU_Context_switch( run_context, heir_context )
    581 #
    582 #  This routine performs a normal non-FP context switch.
    583 #
     651/*
     652 *  void _CPU_Context_switch( run_context, heir_context )
     653 *
     654 *  This routine performs a normal non-FP context switch.
     655 */
    584656
    585657        .align 32
     
    590662        .ENTRY
    591663
    592 # Save the integer context
     664/*
     665 * Save the integer context
     666 */
    593667        stw         %r1,R1_OFFSET(arg0)
    594668        stw         %r2,R2_OFFSET(arg0)
     
    623697        stw         %r31,R31_OFFSET(arg0)
    624698
    625 # fill in interrupt context section
     699/*
     700 * fill in interrupt context section
     701 */
    626702        stw         %r2, PCOQFRONT_OFFSET(%arg0)
    627703        ldo         4(%r2), %r2
    628704        stw         %r2, PCOQBACK_OFFSET(%arg0)
    629705
    630 # Generate a suitable IPSW by using the system default psw
    631 #  with the current low bits added in.
     706/*
     707 * Generate a suitable IPSW by using the system default psw
     708 *  with the current low bits added in.
     709 */
    632710
    633711        ldil        L%CPU_PSW_DEFAULT, %r2
     
    637715        stw         %r2, IPSW_OFFSET(%arg0)
    638716
    639 # at this point, the running task context is completely saved
    640 # Now jump to the bottom of the interrupt handler to load the
    641 # heirs context
     717/*
     718 * at this point, the running task context is completely saved
     719 * Now jump to the bottom of the interrupt handler to load the
     720 * heirs context
     721 */
    642722
    643723        b           _CPU_Context_restore
  • c/src/exec/score/cpu/hppa1.1/hppa.h

    r467eae4d r254b4450  
    2828#define _INCLUDE_HPPA_H
    2929
     30#ifdef ASM
     31#include <rtems/score/targopts.h>
     32#endif
     33
    3034#if defined(__cplusplus)
    3135extern "C" {
     
    4044 */
    4145
    42 #if !defined(CPU_MODEL_NAME)
    43 
    4446#if defined(hppa7100)
    4547
     
    5254#else
    5355
    54 #define CPU_MODEL_NAME  Unsupported CPU Model        /* cause an error on usage */
     56#error "Unsupported CPU Model"
    5557
    5658#endif
    57 
    58 #endif /* !defined(CPU_MODEL_NAME) */
    5959         
    6060/*
     
    6969 * Processor Status Word (PSW) Masks
    7070 */
     71
    7172
    7273#define HPPA_PSW_Y      0x80000000    /* Data Debug Trap Disable */
  • c/src/exec/score/cpu/unix/cpu.c

    r467eae4d r254b4450  
    448448  *(addr + FP_OFF) = (unsigned32)(_stack_high);
    449449
    450 #elif defined(i386)
     450#elif defined(i386) || defined(__i386__)
    451451
    452452    /*
     
    818818  key_t        shm_key;
    819819  key_t        sem_key;
    820   int          status = 0;
     820  int          status;
    821821  int          shm_size;
    822822
  • c/src/exec/score/cpu/unix/cpu.h

    r467eae4d r254b4450  
    252252#if defined(hppa1_1)
    253253#define CPU_STACK_GROWS_UP               TRUE
    254 #elif defined(sparc) || defined(i386)
     254#elif defined(sparc) || defined(i386) || defined(__i386__)
    255255#define CPU_STACK_GROWS_UP               FALSE
    256256#else
     
    354354#endif
    355355
    356 #if defined(i386)
     356#if defined(i386) || defined(__i386__)
    357357 
    358358#ifdef RTEMS_NEWLIB
     
    545545#elif defined(sparc)
    546546#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
    547 #elif defined(i386)
     547#elif defined(i386) || defined(__i386__)
    548548#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
    549549#else
  • c/src/exec/score/cpu/unix/unix.h

    r467eae4d r254b4450  
    3939#define CPU_MODEL_NAME  "Solaris"
    4040 
     41#elif defined(__linux__)
     42 
     43#define CPU_MODEL_NAME  "Linux"
     44 
    4145#elif defined(linux)
    4246 
  • c/src/lib/libbsp/hppa1.1/simhppa/startup/bspstart.c

    r467eae4d r254b4450  
    349349    Cpu_table.itimer_clicks_per_microsecond = 1;
    350350
    351 #ifdef 0
     351#if 0
    352352    /*
    353353     * Commented by DIVISION INC.  External interrupt
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