Changeset 23e3ce64 in rtems


Ignore:
Timestamp:
08/02/00 16:28:06 (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
f3d9df08
Parents:
354d47f
Message:

Split out items shared with mvme167.

Location:
c/src/lib/libbsp/m68k
Files:
2 added
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/mvme162/include/Makefile.am

    r354d47f r23e3ce64  
    55AUTOMAKE_OPTIONS = foreign 1.4
    66
    7 H_FILES = bsp.h coverhd.h page_table.h tod.h
     7H_FILES = bsp.h coverhd.h mvme16x_hw.h page_table.h tod.h
    88
    99$(PROJECT_INCLUDE):
     
    1616        $(INSTALL_DATA) $< $@
    1717
     18$(PROJECT_INCLUDE)/mvme16x_hw.h: mvme16x_hw.h
     19        $(INSTALL_DATA) $< $@
     20
    1821$(PROJECT_INCLUDE)/page_table.h: page_table.h
    1922        $(INSTALL_DATA) $< $@
     
    2326
    2427TMPINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp.h \
    25     $(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/page_table.h \
    26     $(PROJECT_INCLUDE)/tod.h
     28    $(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/mvme16x_hw.h \
     29    $(PROJECT_INCLUDE)/page_table.h $(PROJECT_INCLUDE)/tod.h
    2730
    2831all-local: $(TMPINSTALL_FILES)
  • c/src/lib/libbsp/m68k/mvme162/include/bsp.h

    r354d47f r23e3ce64  
    4141#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
    4242
    43 /*
    44  * Following defines must reflect the setup of the particular MVME162
    45  */
    46 
    47 #define GROUP_BASE_ADDRESS    0x0000F200
    48 #define BOARD_BASE_ADDRESS    0xFFFF0000
    49 
    50 /* Base for local interrupters' vectors (with enable bit set) */
    51 
    52 #define MASK_INT              0x00800000
    53 #define VBR0                  0x6
    54 #define VBR1                  0x7
    55 
    56 /* RAM limits */
    57 
    58 #define RAM_START             0x00100000
    59 #define RAM_END               0x00200000
    60 
    61 /*
    62  * ----------------------------------
    63  */
     43#include <mvme16x_hw.h>
     44
     45
     46/*----------------------------------------------------------------*/
    6447
    6548typedef volatile struct {
    66   unsigned long     slave_adr[2];
    67   unsigned long     slave_trn[2];
    68   unsigned long     slave_ctl;
    69   unsigned long     mastr_adr[4];
    70   unsigned long     mastr_trn;
    71   unsigned long     mastr_att;
    72   unsigned long     mastr_ctl;
    73   unsigned long     dma_ctl_1;
    74   unsigned long     dma_ctl_2;
    75   unsigned long     dma_loc_cnt;
    76   unsigned long     dma_vme_cnt;
    77   unsigned long     dma_byte_cnt;
    78   unsigned long     dma_adr_cnt;
    79   unsigned long     dma_status;
    80   unsigned long     to_ctl;
     49
     50  unsigned char     chipID;
     51  unsigned char     chipREV;
     52  unsigned char     gen_control;
     53  unsigned char     vector_base;
     54 
    8155  unsigned long     timer_cmp_1;
    8256  unsigned long     timer_cnt_1;
    8357  unsigned long     timer_cmp_2;
    8458  unsigned long     timer_cnt_2;
    85   unsigned long     board_ctl;
    86   unsigned long     prescaler_cnt;
    87   unsigned long     intr_stat;
    88   unsigned long     intr_ena;
    89   unsigned long     intr_soft_set;
    90   unsigned long     intr_clear;
    91   unsigned long     intr_level[4];
    92   unsigned long     vector_base;
    93 } lcsr_regs;
    94 
    95 #define lcsr      ((lcsr_regs * const) 0xFFF40000)
    96 
    97 typedef volatile struct {
    98 
    99   unsigned char     chipID;
    100   unsigned char     chipREV;
    101   unsigned char     gen_control;
    102   unsigned char     vector_base;
    103  
    104   unsigned long     timer_cmp_1;
    105   unsigned long     timer_cnt_1;
    106   unsigned long     timer_cmp_2;
    107   unsigned long     timer_cnt_2;
    10859 
    10960  unsigned char     LSB_prescaler_count;
     
    163114 
    164115} mcchip_regs;
    165 
     116 
    166117#define mcchip      ((mcchip_regs * const) 0xFFF42000)
    167118
     
    214165
    215166/*
    216  * The following registers are located in the VMEbus short
    217  * IO space and respond to address modifier codes $29 and $2D.
    218  * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
    219 */
    220 typedef volatile struct {
    221   unsigned char       chip_revision;
    222   unsigned char       chip_id;
    223   unsigned char       lmsig;
    224   unsigned char       board_scr;
    225   unsigned short      gpr[6];
    226 } gcsr_regs;
    227 
    228 #define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
    229 #define gcsr     ((gcsr_regs * const) 0xFFF40100)
    230 
    231 /*
    232167 *  Define the time limits for RTEMS Test Suite test durations.
    233168 *  Long test and short test duration limits are provided.  These
  • c/src/lib/libbsp/m68k/mvme167/include/Makefile.am

    r354d47f r23e3ce64  
    55AUTOMAKE_OPTIONS = foreign 1.4
    66
    7 H_FILES = bsp.h coverhd.h page_table.h fatal.h
     7H_FILES = bsp.h coverhd.h $(srcdir)/../../mvme162/include/mvme16x_hw.h \
     8    page_table.h fatal.h
    89
    910$(PROJECT_INCLUDE):
     
    1617        $(INSTALL_DATA) $< $@
    1718
     19$(PROJECT_INCLUDE)/mvme16x_hw.h: $(srcdir)/../../mvme162/include/mvme16x_hw.h
     20        $(INSTALL_DATA) $< $@
     21
    1822$(PROJECT_INCLUDE)/page_table.h: page_table.h
    1923        $(INSTALL_DATA) $< $@
     
    2327
    2428TMPINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp.h \
    25     $(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/page_table.h \
    26     $(PROJECT_INCLUDE)/fatal.h
     29    $(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/mvme16x_hw.h \
     30    $(PROJECT_INCLUDE)/page_table.h $(PROJECT_INCLUDE)/tod.h
    2731
    2832all: $(TMPINSTALL_FILES)
  • c/src/lib/libbsp/m68k/mvme167/include/bsp.h

    r354d47f r23e3ce64  
    4242#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
    4343 
    44 /*
    45  * Network driver configuration
    46  */
    47  
    48 struct rtems_bsdnet_ifconfig;
    49 int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
    50 #define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
    51 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
    52 
    53 /*
    54  *  This is NOT the base address of local RAM!
    55  *  This is the base local address of the VMEbus short I/O space. A local
    56  *  access to this space results in a A16 VMEbus I/O cycle. This base address
    57  *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
    58  *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
    59  *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
    60  *  GCSRs of other boards are accessible only through the VMEbus short I/O
    61  *  space. See pages 2-45 and 2-7.
    62  */
    63 #define BOARD_BASE_ADDRESS 0xFFFF0000
    64 
    65 
    66 /*
    67  *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
    68  *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
    69  *  VMEbus short I/O space. It also should represent the group address of this
    70  *  MVME167! The group address is configurable, and must match the address
    71  *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
    72  *  recommended by Motorola. It is arbitrary.
    73  *  See pages 2-42 and 2-97 to 2-104.
    74  */
    75 #define GROUP_BASE_ADDRESS 0x0000CC00
    76 
    77 
    78 /*
    79  *  Representation of the GCSR
    80  */
    81 typedef volatile struct gcsr_regs_ {
    82   unsigned char     chip_revision;
    83   unsigned char     chip_id;
    84   unsigned char     lmsig;
    85   unsigned char     board_scr;
    86   unsigned short    gpr[6];
    87 } gcsr_regs;
    88 
    89 /* Address of GCSR in VMEbus space */
    90 #define gcsr_vme    ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
    91 
    92 /* Address of GCSR in local space */
    93 #define gcsr        ((gcsr_regs * const) 0xFFF40100)
    94 
    95 /*
    96  *  Representation of the VMEchip2 LCSR.
    97  *  Could be made more detailed.
    98  */
    99 typedef volatile struct lcsr_regs_ {
    100   unsigned long     slave_adr[2];       /* 0xFFF40000 */
    101   unsigned long     slave_trn[2];       /* 0xFFF40008 */
    102   unsigned long     slave_ctl;          /* 0xFFF40010 */
    103   unsigned long     mastr_adr[4];       /* 0xFFF40014 */
    104   unsigned long     mastr_trn;          /* 0xFFF40024 */
    105   unsigned long     mastr_att;          /* 0xFFF40028 */
    106   unsigned long     mastr_ctl;          /* 0xFFF4002C */
    107   unsigned long     dma_ctl_1;          /* 0xFFF40030 */
    108   unsigned long     dma_ctl_2;          /* 0xFFF40034 */
    109   unsigned long     dma_loc_cnt;        /* 0xFFF40038 */
    110   unsigned long     dma_vme_cnt;        /* 0xFFF4003C */
    111   unsigned long     dma_byte_cnt;       /* 0xFFF40040 */
    112   unsigned long     dma_adr_cnt;        /* 0xFFF40044 */
    113   unsigned long     dma_status;         /* 0xFFF40048 */
    114   unsigned long     to_ctl;             /* 0xFFF4004C */
    115   unsigned long     timer_cmp_1;        /* 0xFFF40050 */
    116   unsigned long     timer_cnt_1;        /* 0xFFF40054 */
    117   unsigned long     timer_cmp_2;        /* 0xFFF40058 */
    118   unsigned long     timer_cnt_2;        /* 0xFFF4005C */
    119   unsigned long     board_ctl;          /* 0xFFF40060 */
    120   unsigned long     prescaler_cnt;      /* 0xFFF40064 */
    121   unsigned long     intr_stat;          /* 0xFFF40068 */
    122   unsigned long     intr_ena;           /* 0xFFF4006C */
    123   unsigned long     intr_soft_set;      /* 0xFFF40070 */
    124   unsigned long     intr_clear;         /* 0xFFF40074 */
    125   unsigned long     intr_level[4];      /* 0xFFF40078 */
    126   unsigned long     vector_base;        /* 0xFFF40088 */
    127 } lcsr_regs;
    128 
    129 /*
    130  *  Base address of VMEchip2 LCSR
    131  *  Not configurable on the MVME167.
    132  */
    133 #define lcsr        ((lcsr_regs * const) 0xFFF40000)
    134 
    135 /*
    136  *  Vector numbers for the interrupts from the VMEchip2. Use the values
    137  *  "recommended" by Motorola.
    138  *  See pages 2-70 to 2-92, and table 2-3.
    139  */
    140 
    141 /* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
    142 #define MASK_INT    0x00800000
    143 
    144 /* The content of VBR0 corresponds to "X" in table 2-3 */
    145 #define VBR0        0x6
    146 
    147 /* The content of VBR1 corresponds to "Y" in table 2-3 */
    148 #define VBR1        0x7
    149 
     44#include <mvme16x_hw.h>
     45
     46/* GCSR is in mvme16x_hw.h */
     47/* LCSR is in mvme16x_hw.h */
     48/* i82596 is in mvme16x_hw.h */
     49/* NVRAM is in mvme16x_hw.h */
    15050
    15151/*
     
    208108#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
    209109
    210 /*
    211  * Vector numbers for the interrupts from the PCCchip2. Use the values
    212  * "recommended" by Motorola.
    213  * See page 3-15.
    214  */
    215 #define PCCCHIP2_VBR    0x5
    216 
    217 
    218110/*
    219111 * The MVME167 is equiped with one or two MEMC040 memory controllers at
     
    416308 *  Debug print functions: implemented in console.c
    417309 */
    418 void printk( char *fmt, ... );
    419310void BSP_output_string( char * buf );
    420 
    421 /*
    422  *  Representation of 82596CA LAN controller: Memory Map
    423  */
    424 typedef volatile struct i82596_regs_ {
    425   unsigned short        port_lower;             /* 0xFFF46000 */
    426   unsigned short        port_upper;             /* 0xFFF46002 */
    427   unsigned long         chan_attn;              /* 0xFFF46004 */
    428 } i82596_regs;
    429 
    430 /*
    431  *  Base address of the 82596.
    432  */
    433 #define i82596    ((i82596_regs * const) 0xFFF46000)
    434 
    435 /*
    436  *  Representation of initialization data in NVRAM
    437  */
    438 typedef volatile struct nvram_config_ {
    439   unsigned char  dcache_enable;                         /* 0xFFFC0000 */
    440   unsigned char  icache_enable;                         /* 0xFFFC0001 */
    441   unsigned short cache_mode;                            /* 0xFFFC0002 */
    442   unsigned long  ipaddr;                                        /* 0xFFFC0004 */
    443   unsigned long  netmask;                                       /* 0xFFFC0008 */
    444   unsigned char  enaddr[6];                                     /* 0xFFFC000C */
    445   unsigned short processor_id;                          /* 0xFFFC0012 */
    446   unsigned long  rma_start;                                     /* 0xFFFC0014 */
    447   unsigned long  vma_start;                                     /* 0xFFFC0018 */
    448   unsigned long  ramsize;                                       /* 0xFFFC001C */
    449 } nvram_config;
    450 
    451 /*
    452  *  Pointer to the base of User Area NVRAM
    453  */
    454 #define nvram                   ((nvram_config * const) 0xFFFC0000)
    455 
    456311
    457312/* BSP-wide functions */
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