Changeset 22c0e4d in rtems for c


Ignore:
Timestamp:
Aug 25, 2008, 12:50:29 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
e03c37a
Parents:
28041b67
Message:

Changed invalid usage of a boolean type to a proper integer type in calc_dbat_regvals().

Location:
c/src/lib/libbsp/powerpc/gen5200
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/ChangeLog

    r28041b67 r22c0e4d  
     12008-08-25      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * startup/cpuinit.h: Uses now powerpc-utility.h.  Changed invalid usage
     4        of a boolean type to a proper integer type in calc_dbat_regvals().
     5
    162008-08-20      Ralf Corsépius <ralf.corsepius@rtems.org>
    27
  • c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c

    r28041b67 r22c0e4d  
    6666/***********************************************************************/
    6767
     68#include <stdbool.h>
     69#include <string.h>
     70
     71#include <libcpu/powerpc-utility.h>
     72#include <libcpu/mmu.h>
     73
    6874#include <bsp.h>
    69 #include <rtems/powerpc/registers.h>
    70 #include "../include/mpc5200.h"
    71 
    72 #include <libcpu/mmu.h>
    73 #include <libcpu/spr.h>
    74 #include <string.h>
    75 
    76 /* Macros for HID0 access */
    77 #define SET_HID0(r)   __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r))
    78 #define GET_HID0(r)   __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r))
    79 
    80 #define DBAT_MTSPR(val,name) __MTSPR(val,name);
    81 #define SET_DBAT(n,uv,lv) {DBAT_MTSPR(uv,DBAT##n##U);DBAT_MTSPR(lv,DBAT##n##L);}
    82 void calc_dbat_regvals(BAT *bat_ptr,
    83                        uint32_t base_addr,
    84                        uint32_t size,
    85                        boolean flg_w,
    86                        boolean flg_i,
    87                        boolean flg_m,
    88                        boolean flg_g,
    89                        boolean flg_bpp)
    90 {
    91   uint32_t block_mask;
    92   uint32_t end_addr;
    93 
    94   /*
    95    * clear dbat
    96    */
    97   memset(bat_ptr, 0,sizeof(BAT));
    98 
    99   /*
    100    * determine block mask, that overlaps the whole block
    101    */
    102   end_addr = base_addr+size-1;
    103   block_mask = ~0;
     75#include <bsp/mpc5200.h>
     76
     77#define SET_DBAT( n, uv, lv) \
     78  do { \
     79    PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
     80    PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
     81  } while (0)
     82
     83static void calc_dbat_regvals(
     84  BAT *bat_ptr,
     85  uint32_t base_addr,
     86  uint32_t size,
     87  bool flg_w,
     88  bool flg_i,
     89  bool flg_m,
     90  bool flg_g,
     91  uint32_t flg_bpp
     92)
     93{
     94  uint32_t block_mask = 0xffffffff;
     95  uint32_t end_addr = base_addr + size - 1;
     96
     97  /* Determine block mask, that overlaps the whole block */
    10498  while ((end_addr & block_mask) != (base_addr & block_mask)) {
    10599    block_mask <<= 1;
    106100  }
    107101 
    108   bat_ptr->batu.bepi  = base_addr  >> (32-15);
    109   bat_ptr->batu.bl    = ~(block_mask >> (28-11));
    110   bat_ptr->batu.vs    = 1;
    111   bat_ptr->batu.vp    = 1;
     102  bat_ptr->batu.bepi = base_addr >> (32 - 15);
     103  bat_ptr->batu.bl   = ~(block_mask >> (28 - 11));
     104  bat_ptr->batu.vs   = 1;
     105  bat_ptr->batu.vp   = 1;
    112106 
    113   bat_ptr->batl.brpn  = base_addr  >> (32-15);
    114   bat_ptr->batl.w  = flg_w;
    115   bat_ptr->batl.i  = flg_i;
    116   bat_ptr->batl.m  = flg_m;
    117   bat_ptr->batl.g  = flg_g;
    118   bat_ptr->batl.pp = flg_bpp;
     107  bat_ptr->batl.brpn = base_addr  >> (32 - 15);
     108  bat_ptr->batl.w    = flg_w;
     109  bat_ptr->batl.i    = flg_i;
     110  bat_ptr->batl.m    = flg_m;
     111  bat_ptr->batl.g    = flg_g;
     112  bat_ptr->batl.pp   = flg_bpp;
    119113}
    120114
     
    191185#endif
    192186
    193 
    194 
    195187void cpu_init(void)
    196188{
    197   register unsigned long reg;
    198 
    199   /*
    200    * Enable instruction cache
    201    */
    202   GET_HID0(reg);
    203   reg |= HID0_ICE;
    204   SET_HID0(reg);
    205 
    206   /*
    207    * set up DBAT registers in MMU
    208    */
     189  uint32_t msr;
     190
     191  /* Enable instruction cache */
     192  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE);
     193
     194  /* Set up DBAT registers in MMU */
    209195  cpu_init_bsp();
    210196
     
    215201  #endif
    216202
    217   /*
    218    * enable data MMU in MSR
    219    */
    220   _write_MSR(_read_MSR() | MSR_DR);
     203  /* Read MSR */
     204  msr = ppc_machine_state_register();
     205
     206  /* Enable data MMU in MSR */
     207  msr |= MSR_DR;
     208
     209  /* Update MSR */
     210  ppc_set_machine_state_register( msr);
    221211
    222212  /*
    223    * enable data cache
     213   * Enable data cache.
    224214   *
    225    * NOTE: TRACE32 now supports data cache for MGT5x00
    226    */
    227   GET_HID0(reg);
    228   reg |= HID0_DCE;
    229   SET_HID0(reg);
    230 }
     215   * NOTE: TRACE32 now supports data cache for MGT5x00.
     216   */
     217  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE);
     218}
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