Changeset 21dd58d9 in rtems


Ignore:
Timestamp:
Dec 22, 2013, 11:18:34 PM (5 years ago)
Author:
Daniel Ramirez <javamonn@…>
Branches:
4.11, master
Children:
b7212b9
Parents:
9543fdbb
git-author:
Daniel Ramirez <javamonn@…> (12/22/13 23:18:34)
git-committer:
Gedare Bloom <gedare@…> (12/23/13 01:55:04)
Message:

arm_xilinx-zynq: added new doxygen

Location:
c/src/lib/libbsp/arm/xilinx-zynq/include
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h

    r9543fdbb r21dd58d9  
     1/**
     2 * @file
     3 * @ingroup arm_zynq
     4 * @brief Global BSP definitions.
     5 */
     6
    17/*
    28 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     
    3339#endif /* __cplusplus */
    3440
     41/**
     42 * @defgroup arm_zynq Xilinx-Zynq Support
     43 * @ingroup bsp_arm
     44 * @brief Xilinz-Zynq Board Support Package
     45 * @{
     46 */
     47
    3548#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000
    3649
     
    4861void zynq_fatal(zynq_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
    4962
    50 /*
    51  * Zynq specific set up of the MMU. Provide in the application to override
     63/**
     64 * @brief Zynq specific set up of the MMU.
     65 *
     66 * Provide in the application to override
    5267 * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1
    5368 * AXI ports. You should add the specific regions that map into your
     
    5570 */
    5671BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
     72
     73/** @} */
    5774
    5875#ifdef __cplusplus
  • c/src/lib/libbsp/arm/xilinx-zynq/include/cache_.h

    r9543fdbb r21dd58d9  
     1/**
     2 * @file
     3 * @ingroup zynq_cache
     4 * @brief Cache definitions and functions.
     5 */
     6
    17/*
    28 * Authorship
     
    5965#define ZYNQ_L2_CACHE_LINE_SIZE 32
    6066
    61 /* L2CC Register Offsets */
     67/**
     68 * @defgroup zynq_cache Cache Support
     69 * @ingroup arm_zynq
     70 * @brief Cache Functions and Defitions
     71 * @{
     72 */
     73
     74/**
     75 * @brief L2CC Register Offsets
     76 */
    6277typedef struct {
    6378  uint32_t cache_id;                                    /* Cache ID */
     
    6681  uint8_t  reserved_8[0x100 - 8];
    6782  uint32_t ctrl;                                        /* Control */
    68 #define L2CC_ENABLE_MASK                 0x00000001     /* Enables the L2CC */
    69 
    70   uint32_t aux_ctrl;                                    /* Auxiliary control */
    71 #define L2CC_AUX_EBRESPE_MASK            0x40000000     /* Early BRESP Enable */
    72 #define L2CC_AUX_IPFE_MASK               0x20000000     /* Instruction Prefetch Enable */
    73 #define L2CC_AUX_DPFE_MASK               0x10000000     /* Data Prefetch Enable */
    74 #define L2CC_AUX_NSIC_MASK               0x08000000     /* Non-secure interrupt access control */
    75 #define L2CC_AUX_NSLE_MASK               0x04000000     /* Non-secure lockdown enable */
    76 #define L2CC_AUX_CRP_MASK                0x02000000     /* Cache replacement policy */
    77 #define L2CC_AUX_FWE_MASK                0x01800000     /* Force write allocate */
    78 #define L2CC_AUX_SAOE_MASK               0x00400000     /* Shared attribute override enable */
    79 #define L2CC_AUX_PE_MASK                 0x00200000     /* Parity enable */
    80 #define L2CC_AUX_EMBE_MASK               0x00100000     /* Event monitor bus enable */
    81 #define L2CC_AUX_WAY_SIZE_MASK           0x000E0000     /* Way-size */
    82 #define L2CC_AUX_ASSOC_MASK              0x00010000     /* Associativity */
    83 #define L2CC_AUX_SAIE_MASK               0x00002000     /* Shared attribute invalidate enable */
    84 #define L2CC_AUX_EXCL_CACHE_MASK         0x00001000     /* Exclusive cache configuration */
    85 #define L2CC_AUX_SBDLE_MASK              0x00000800     /* Store buffer device limitation Enable */
    86 #define L2CC_AUX_HPSODRE_MASK            0x00000400     /* High Priority for SO and Dev Reads Enable */
    87 #define L2CC_AUX_FLZE_MASK               0x00000001     /* Full line of zero enable */
    88 
    89 #define L2CC_AUX_REG_DEFAULT_MASK        0x72360000     /* Enable all prefetching, */
    90                                                         /* Cache replacement policy, Parity enable, */
    91                                                         /* Event monitor bus enable and Way Size (64 KB) */
     83/** @brief Enables the L2CC */
     84#define L2CC_ENABLE_MASK                 0x00000001
     85
     86  /** @brief Auxiliary control */
     87  uint32_t aux_ctrl;
     88/** @brief Early BRESP Enable */
     89#define L2CC_AUX_EBRESPE_MASK            0x40000000
     90/** @brief Instruction Prefetch Enable */
     91#define L2CC_AUX_IPFE_MASK               0x20000000
     92/** @brief Data Prefetch Enable */
     93#define L2CC_AUX_DPFE_MASK               0x10000000
     94/** @brief Non-secure interrupt access control */
     95#define L2CC_AUX_NSIC_MASK               0x08000000
     96/** @brief Non-secure lockdown enable */
     97#define L2CC_AUX_NSLE_MASK               0x04000000
     98/** @brief Cache replacement policy */
     99#define L2CC_AUX_CRP_MASK                0x02000000
     100/** @brief Force write allocate */
     101#define L2CC_AUX_FWE_MASK                0x01800000
     102/** @breif Shared attribute override enable */
     103#define L2CC_AUX_SAOE_MASK               0x00400000
     104/** @brief Parity enable */
     105#define L2CC_AUX_PE_MASK                 0x00200000
     106/** @brief Event monitor bus enable */
     107#define L2CC_AUX_EMBE_MASK               0x00100000
     108/** @brief Way-size */
     109#define L2CC_AUX_WAY_SIZE_MASK           0x000E0000
     110/** @brief Way-size */
     111#define L2CC_AUX_ASSOC_MASK              0x00010000
     112/** @brief Shared attribute invalidate enable */
     113#define L2CC_AUX_SAIE_MASK               0x00002000
     114/** @brief Exclusive cache configuration */
     115#define L2CC_AUX_EXCL_CACHE_MASK         0x00001000
     116/** @brief Store buffer device limitation Enable */
     117#define L2CC_AUX_SBDLE_MASK              0x00000800
     118/** @brief High Priority for SO and Dev Reads Enable */
     119#define L2CC_AUX_HPSODRE_MASK            0x00000400
     120
     121/** @brief Full line of zero enable */
     122#define L2CC_AUX_FLZE_MASK               0x00000001
     123
     124/** @brief Enable all prefetching, */
     125#define L2CC_AUX_REG_DEFAULT_MASK        0x72360000
    92126#define L2CC_AUX_REG_ZERO_MASK           0xFFF1FFFF
    93127
    94   uint32_t tag_ram_ctrl;
    95 #define L2CC_TAG_RAM_DEFAULT_MASK        0x00000111     /* Latency for tag RAM */
    96   uint32_t data_ram_ctrl;
    97 #define L2CC_DATA_RAM_DEFAULT_MASK       0x00000121     /* Latency for data RAM */
     128   /** @brief Latency for tag RAM */
     129   uint32_t tag_ram_ctrl;
     130#define L2CC_TAG_RAM_DEFAULT_MASK        0x00000111
     131   /** @brief Latency for data RAM */
     132   uint32_t data_ram_ctrl;
     133#define L2CC_DATA_RAM_DEFAULT_MASK       0x00000121
    98134
    99135  uint8_t  reserved_110[0x200 - 0x110];
    100   uint32_t ev_ctrl;                                     /* Event counter control */
    101   uint32_t ev_cnt1_cfg;                                 /* Event counter 1 configuration */
    102   uint32_t ev_cnt0_cfg;                                 /* Event counter 0 configuration */
    103   uint32_t ev_cnt1;                                     /* Event counter 1 value */
    104   uint32_t ev_cnt0;                                     /* Event counter 0 value */
    105   uint32_t int_mask;                                    /* Interrupt enable mask */
    106   uint32_t int_mask_status;                             /* Masked   interrupt status (read-only)*/
    107   uint32_t int_raw_status;                              /* Unmasked interrupt status */
    108   uint32_t int_clr;                                     /* Interrupt clear */
    109 /* Interrupt bit masks */
    110 #define L2CC_INT_DECERR_MASK             0x00000100     /* DECERR from L3 */
    111 #define L2CC_INT_SLVERR_MASK             0x00000080     /* SLVERR from L3 */
    112 #define L2CC_INT_ERRRD_MASK              0x00000040     /* Error on L2 data RAM (Read) */
    113 #define L2CC_INT_ERRRT_MASK              0x00000020     /* Error on L2 tag RAM (Read) */
    114 #define L2CC_INT_ERRWD_MASK              0x00000010     /* Error on L2 data RAM (Write) */
    115 #define L2CC_INT_ERRWT_MASK              0x00000008     /* Error on L2 tag RAM (Write) */
    116 #define L2CC_INT_PARRD_MASK              0x00000004     /* Parity Error on L2 data RAM (Read) */
    117 #define L2CC_INT_PARRT_MASK              0x00000002     /* Parity Error on L2 tag RAM (Read) */
    118 #define L2CC_INT_ECNTR_MASK              0x00000001     /* Event Counter1/0 Overflow Increment */
    119 
     136  /** @brief Event counter control */
     137  uint32_t ev_ctrl;
     138  /** @brief Event counter 1 configuration */
     139  uint32_t ev_cnt1_cfg;
     140  /** @brief Event counter 0 configuration */
     141  uint32_t ev_cnt0_cfg;
     142  /** @brief Event counter 1 value */
     143  uint32_t ev_cnt1;
     144  /** @brief Event counter 0 value */
     145  uint32_t ev_cnt0;
     146  /** @brief Interrupt enable mask */
     147  uint32_t int_mask;
     148  /** @brief Masked   interrupt status (read-only)*/
     149  uint32_t int_mask_status;
     150  /** @brief Unmasked interrupt status */
     151  uint32_t int_raw_status;
     152  /** @brief Interrupt clear */
     153  uint32_t int_clr;
     154
     155/**
     156 * @name Interrupt bit masks
     157 *
     158 * @{
     159 */
     160 
     161/** @brief DECERR from L3 */
     162#define L2CC_INT_DECERR_MASK             0x00000100
     163/** @brief SLVERR from L3 */
     164#define L2CC_INT_SLVERR_MASK             0x00000080
     165/** @brief Error on L2 data RAM (Read) */
     166#define L2CC_INT_ERRRD_MASK              0x00000040
     167/** @brief Error on L2 tag RAM (Read) */
     168#define L2CC_INT_ERRRT_MASK              0x00000020
     169/** @brief Error on L2 data RAM (Write) */
     170#define L2CC_INT_ERRWD_MASK              0x00000010
     171/** @brief Error on L2 tag RAM (Write) */
     172#define L2CC_INT_ERRWT_MASK              0x00000008
     173/** @brief Parity Error on L2 data RAM (Read) */
     174#define L2CC_INT_PARRD_MASK              0x00000004
     175/** @brief Parity Error on L2 tag RAM (Read) */
     176#define L2CC_INT_PARRT_MASK              0x00000002
     177/** @brief Event Counter1/0 Overflow Increment */
     178#define L2CC_INT_ECNTR_MASK              0x00000001
     179
     180/** @} */
     181 
    120182  uint8_t  reserved_224[0x730 - 0x224];
    121   uint32_t cache_sync;                                  /* Drain the STB */
     183  /** @brief Drain the STB */
     184  uint32_t cache_sync;
    122185  uint8_t  reserved_734[0x770 - 0x734];
    123   uint32_t inv_pa;                                      /* Invalidate line by PA */
     186  /** @brief Invalidate line by PA */
     187  uint32_t inv_pa;
    124188  uint8_t  reserved_774[0x77c - 0x774];
    125   uint32_t inv_way;                                     /* Invalidate by Way */
     189  /** @brief Invalidate by Way */
     190  uint32_t inv_way;
    126191  uint8_t  reserved_780[0x7b0 - 0x780];
    127   uint32_t clean_pa;                                    /* Clean Line by PA */
     192  /** @brief Clean Line by PA */
     193  uint32_t clean_pa;
    128194  uint8_t  reserved_7b4[0x7b8 - 0x7b4];
    129   uint32_t clean_index;                                 /* Clean Line by Set/Way */
    130   uint32_t clean_way;                                   /* Clean by Way */
     195  /** @brief Clean Line by Set/Way */
     196  uint32_t clean_index;
     197  /** @brief Clean by Way */
     198  uint32_t clean_way;
    131199  uint8_t  reserved_7c0[0x7f0 - 0x7c0];
    132   uint32_t clean_inv_pa;                                /* Clean and Invalidate Line by PA */
     200  /** @brief Clean and Invalidate Line by PA */
     201  uint32_t clean_inv_pa;
    133202  uint8_t  reserved_7f4[0x7f8 - 0x7f4];
    134   uint32_t clean_inv_indx;                              /* Clean and Invalidate Line by Set/Way */
    135   uint32_t clean_inv_way;                               /* Clean and Invalidate by Way */
    136 
    137   uint8_t  reserved_800[0x900 - 0x800];
    138   uint32_t d_lockdown_0;                                /* Data        lock down 0 */
    139   uint32_t i_lockdown_0;                                /* Instruction lock down 0 */
    140   uint32_t d_lockdown_1;                                /* Data        lock down 1 */
    141   uint32_t i_lockdown_1;                                /* Instruction lock down 1 */
    142   uint32_t d_lockdown_2;                                /* Data        lock down 2 */
    143   uint32_t i_lockdown_2;                                /* Instruction lock down 2 */
    144   uint32_t d_lockdown_3;                                /* Data        lock down 3 */
    145   uint32_t i_lockdown_3;                                /* Instruction lock down 3 */
    146   uint32_t d_lockdown_4;                                /* Data        lock down 4 */
    147   uint32_t i_lockdown_4;                                /* Instruction lock down 4 */
    148   uint32_t d_lockdown_5;                                /* Data        lock down 5 */
    149   uint32_t i_lockdown_5;                                /* Instruction lock down 5 */
    150   uint32_t d_lockdown_6;                                /* Data        lock down 6 */
    151   uint32_t i_lockdown_6;                                /* Instruction lock down 6 */
    152   uint32_t d_lockdown_7;                                /* Data        lock down 7 */
    153   uint32_t i_lockdown_7;                                /* Instruction lock down 7 */
     203  /** @brief Clean and Invalidate Line by Set/Way */
     204  uint32_t clean_inv_indx;
     205  /** @brief Clean and Invalidate by Way */
     206  uint32_t clean_inv_way;
     207
     208  /** @brief Data        lock down 0 */
     209  uint32_t d_lockdown_0;
     210  /** @brief Instruction lock down 0 */
     211  uint32_t i_lockdown_0;
     212  /** @brief Data        lock down 1 */
     213  uint32_t d_lockdown_1;
     214  /** @brief Instruction lock down 1 */
     215  uint32_t i_lockdown_1;
     216  /** @brief Data        lock down 2 */
     217  uint32_t d_lockdown_2;
     218  /** @brief Instruction lock down 2 */
     219  uint32_t i_lockdown_2;
     220  /** @brief Data        lock down 3 */
     221  uint32_t d_lockdown_3;
     222  /** @brief Instruction lock down 3 */
     223  uint32_t i_lockdown_3;
     224  /** @brief Data        lock down 4 */
     225  uint32_t d_lockdown_4;
     226  /** @brief Instruction lock down 4 */
     227  uint32_t i_lockdown_4;
     228  /** @brief Data        lock down 5 */
     229  uint32_t d_lockdown_5;
     230  /** @brief Instruction lock down 5 */
     231  uint32_t i_lockdown_5;
     232  /** @brief Data        lock down 6 */
     233  uint32_t d_lockdown_6;
     234  /** @brief Instruction lock down 6 */
     235  uint32_t i_lockdown_6;
     236  /** @brief Data        lock down 7 */
     237  uint32_t d_lockdown_7;
     238  /** @brief Instruction lock down 7 */
     239  uint32_t i_lockdown_7;
    154240
    155241  uint8_t  reserved_940[0x950 - 0x940];
    156   uint32_t lock_line_en;                                /* Lockdown by Line Enable */
    157   uint32_t unlock_way;                                  /* Cache lockdown by way */
     242  /** @brief Lockdown by Line Enable */
     243  uint32_t lock_line_en;
     244  /** @brief Cache lockdown by way */
     245  uint32_t unlock_way;
    158246
    159247  uint8_t  reserved_958[0xc00 - 0x958];
    160   uint32_t addr_filtering_start;                        /* Address range redirect, part 1 */
    161   uint32_t addr_filtering_end;                          /* Address range redirect, part 2 */
    162 #define L2CC_ADDR_FILTER_VALID_MASK      0xFFF00000     /* Address filtering valid bits*/
    163 #define L2CC_ADDR_FILTER_ENABLE_MASK     0x00000001     /* Address filtering enable bit*/
     248  /** @brief Address range redirect, part 1 */
     249  uint32_t addr_filtering_start;
     250  /** @brief Address range redirect, part 2 */
     251  uint32_t addr_filtering_end;
     252/** @brief Address filtering valid bits*/
     253#define L2CC_ADDR_FILTER_VALID_MASK      0xFFF00000
     254/** @brief Address filtering enable bit*/
     255#define L2CC_ADDR_FILTER_ENABLE_MASK     0x00000001
    164256
    165257  uint8_t  reserved_c08[0xf40 - 0xc08];
    166   uint32_t debug_ctrl;                                  /* Debug control */
    167 #define L2CC_DEBUG_SPIDEN_MASK           0x00000004     /* Debug SPIDEN bit */
    168 #define L2CC_DEBUG_DWB_MASK              0x00000002     /* Debug DWB bit, forces write through */
    169 #define L2CC_DEBUG_DCL_MASK              0x00000002     /* Debug DCL bit, disables cache line fill */
     258  /** @brief Debug control */
     259  uint32_t debug_ctrl;
     260/** @brief Debug SPIDEN bit */
     261#define L2CC_DEBUG_SPIDEN_MASK           0x00000004
     262/** @brief Debug DWB bit, forces write through */
     263#define L2CC_DEBUG_DWB_MASK              0x00000002
     264/** @breif Debug DCL bit, disables cache line fill */
     265#define L2CC_DEBUG_DCL_MASK              0x00000002
    170266
    171267  uint8_t  reserved_f44[0xf60 - 0xf44];
    172   uint32_t prefetch_ctrl;                               /* Purpose prefetch enables */
     268  /** @brief Purpose prefetch enables */
     269  uint32_t prefetch_ctrl;
    173270  uint8_t  reserved_f64[0xf80 - 0xf64];
    174   uint32_t power_ctrl;                                  /* Purpose power controls */
     271  /** @brief Purpose power controls */
     272  uint32_t power_ctrl;
    175273} L2CC;
    176274
     
    884982}
    885983
     984/** @} */
     985
    886986#endif /* LIBBSP_ARM_ZYNQ_CACHE__H */
  • c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h

    r9543fdbb r21dd58d9  
     1/**
     2 * @file
     3 * @ingroup zynq_interrupt
     4 * @brief Interrupt definitions.
     5 */
     6
    17/*
    28 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     
    2733extern "C" {
    2834#endif /* __cplusplus */
     35
     36/**
     37 * @defgroup zynq_interrupt Interrupt Support
     38 * @ingroup arm_zynq
     39 * @brief Interrupt Support
     40 * @{
     41 */
    2942
    3043#define ZYNQ_IRQ_CPU_0 32
     
    92105#define BSP_INTERRUPT_VECTOR_MAX 92
    93106
     107/** @} */
     108
    94109#ifdef __cplusplus
    95110}
  • c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h

    r9543fdbb r21dd58d9  
     1/**
     2 * @file
     3 * @ingroup zynq_tm27
     4 * @brief Interrupt mechanisms for tm27 test.
     5 */
     6
    17/*
    28 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     
    2026#define __tm27_h
    2127
     28/**
     29 * @defgroup zynq_tm27 TM27 Test Support
     30 * @ingroup arm_zynq
     31 * @brief Interrupt Mechanisms for tm27 test
     32 */
     33
    2234#include <bsp/arm-gic-tm27.h>
    2335
  • c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart-regs.h

    r9543fdbb r21dd58d9  
     1/**
     2 * @file
     3 * @ingroup zynq_uart_regs
     4 * @brief UART register definitions.
     5 */
     6
    17/*
    28 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     
    1117 * found in the file LICENSE in this distribution or at
    1218 * http://www.rtems.com/license/LICENSE.
     19 */
     20
     21/**
     22 * @defgroup zynq_uart_regs UART Register Definitions
     23 * @ingroup zynq_uart
     24 * @brief UART Register Definitions
     25 * @{
    1326 */
    1427
     
    131144} zynq_uart;
    132145
     146/** @} */
     147
    133148#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
  • c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart.h

    r9543fdbb r21dd58d9  
     1/**
     2 * @file
     3 * @ingroup zynq_uart
     4 * @brief UART support.
     5 */
     6
    17/*
    28 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     
    2228#endif /* __cplusplus */
    2329
     30/**
     31 * @defgroup zynq_uart UART Support
     32 * @ingroup arm_zynq
     33 * @brief UART Support
     34 */
     35
    2436extern const console_fns zynq_uart_fns;
    2537
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