Changeset 21b54fc in rtems


Ignore:
Timestamp:
Nov 23, 2004, 3:31:19 PM (16 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
0bedb7ec
Parents:
9146692
Message:

2004-11-23 Richard Campbell <richard.campbell@…>

  • powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for mpc8240 and mpc8245.
Location:
c/src/lib/libcpu
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/ChangeLog

    r9146692 r21b54fc  
     12004-11-23      Richard Campbell <richard.campbell@oarcorp.com>
     2
     3        * powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for
     4        mpc8240 and mpc8245.
     5
    162003-09-04      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S

    r9146692 r21b54fc  
    1919#include <rtems/score/cpu.h>
    2020#include <libcpu/io.h>
     21#include <bspopts.h>
    2122
    2223/* Unfortunately, the CPU types defined in cpu.h are
     
    138139        mfspr   r11,HID0
    139140        andi.   r0,r11,HID0_DCE
    140         ori     r11,r11,HID0_ICE|HID0_DCE
     141#if defined(mpc8240) || defined(mpc8245)
     142        /*
     143         * Data cache is broken for mpc8240 and mpc8245,
     144         * enable instruction cache only.
     145         */
     146        ori     r11,r11,HID0_ICE
     147#else
     148        /*
     149         * Enable both instruction and data caches
     150         */
     151        ori     r11,r11,HID0_ICE|HID0_DCE
     152#endif
    141153        ori     r8,r11,HID0_ICFI
    142154        bne     3f                      /* don't invalidate the D-cache */
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