Changeset 219432f in rtems


Ignore:
Timestamp:
Jul 31, 2002, 12:14:42 AM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
52c5689e
Parents:
4b4d4fde
Message:

2002-07-30 Joel Sherrill <joel@…>

  • timeMVME136.t, timedata.t: Replaced XXX's with real info.
Location:
doc/supplements/m68k
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • doc/supplements/m68k/ChangeLog

    r4b4d4fde r219432f  
     12002-07-30      Joel Sherrill <joel@OARcorp.com>
     2
     3        * timeMVME136.t, timedata.t: Replaced XXX's with real info.
     4
    152002-07-26      Joel Sherrill <joel@OARcorp.com>
    26
  • doc/supplements/m68k/timeMVME136.t

    r4b4d4fde r219432f  
    2828All times reported except for the maximum period
    2929interrupts are disabled by RTEMS were measured using a Motorola
    30 MVME135 CPU board.  The MVME135 is a 20Mhz board with one wait
     30MVME135 CPU board.  The MVME135 is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     31Mhz board with one wait
    3132state dynamic memory and a MC68881 numeric coprocessor.  The
    3233Zilog 8036 countdown timer on this board was used to measure
     
    4243assumed.  The total CPU cycles executed with interrupts
    4344disabled, including the instructions to disable and enable
    44 interrupts, was divided by 20 to simulate a 20Mhz MC68020.  It
     45interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     46Mhz MC68020.  It
    4547should be noted that the worst case instruction times for the
    4648MC68020 assume that the internal cache is disabled and that no
     
    5961interrupt latency of less than
    6062RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
    61 microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
     63microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     64Mhz.  [NOTE:  The maximum period with interrupts
    6265disabled was last determined for Release
    6366RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
     
    6669interrupts disabled within RTEMS is hand-timed and based upon
    6770worst case (i.e. CPU cache disabled and no instruction overlap)
    68 times for a 20Mhz MC68020.  The interrupt vector and entry
     71times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     72Mhz MC68020.  The interrupt vector and entry
    6973overhead time was generated on an MVME135 benchmark platform
    7074using the Multiprocessing Communications registers to generate
  • doc/supplements/m68k/timedata.t

    r4b4d4fde r219432f  
    5959All times reported except for the maximum period
    6060interrupts are disabled by RTEMS were measured using a Motorola
    61 MVME135 CPU board.  The MVME135 is a 20Mhz board with one wait
     61MVME135 CPU board.  The MVME135 is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     62Mhz board with one wait
    6263state dynamic memory and a MC68881 numeric coprocessor.  The
    6364Zilog 8036 countdown timer on this board was used to measure
     
    7374assumed.  The total CPU cycles executed with interrupts
    7475disabled, including the instructions to disable and enable
    75 interrupts, was divided by 20 to simulate a 20Mhz MC68020.  It
     76interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     77Mhz MC68020.  It
    7678should be noted that the worst case instruction times for the
    7779MC68020 assume that the internal cache is disabled and that no
     
    9395interrupt latency of less than
    9496RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
    95 microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
     97microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     98Mhz.  [NOTE:  The maximum period with interrupts
    9699disabled was last determined for Release
    97100RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
     
    100103interrupts disabled within RTEMS is hand-timed and based upon
    101104worst case (i.e. CPU cache disabled and no instruction overlap)
    102 times for a 20Mhz MC68020.  The interrupt vector and entry
     105times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
     106Mhz MC68020.  The interrupt vector and entry
    103107overhead time was generated on an MVME135 benchmark platform
    104108using the Multiprocessing Communications registers to generate
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