Changeset 20d8237 in rtems


Ignore:
Timestamp:
Sep 4, 2020, 6:10:57 PM (4 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
4b767bd
Parents:
9979042
git-author:
Sebastian Huber <sebastian.huber@…> (09/04/20 18:10:57)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/17/20 06:20:35)
Message:

arm: Fix arm_cp15_set_translation_table_entries()

In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.

Close #4068.

Files:
2 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c

    r9979042 r20d8237  
    108108    const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity();
    109109    if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) {
    110       arm_cp15_tlb_invalidate_entry_all_asids(mva);
     110      arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(mva);
    111111    }
    112112    else
  • cpukit/score/cpu/arm/include/libcpu/arm-cp15.h

    r9979042 r20d8237  
    648648
    649649ARM_CP15_TEXT_SECTION static inline void
     650arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(const void *mva)
     651{
     652  ARM_SWITCH_REGISTERS;
     653
     654  mva = ARM_CP15_TLB_PREPARE_MVA(mva);
     655
     656  __asm__ volatile (
     657    ARM_SWITCH_TO_ARM
     658    "mcr p15, 0, %[mva], c8, c3, 3\n"
     659    ARM_SWITCH_BACK
     660    : ARM_SWITCH_OUTPUT
     661    : [mva] "r" (mva)
     662  );
     663}
     664
     665ARM_CP15_TEXT_SECTION static inline void
    650666arm_cp15_tlb_instruction_invalidate(void)
    651667{
Note: See TracChangeset for help on using the changeset viewer.