Ignore:
Timestamp:
May 11, 2018, 4:54:59 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
fe2cd01b
Parents:
853c5ef
git-author:
Sebastian Huber <sebastian.huber@…> (05/11/18 04:54:59)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/28/18 13:02:12)
Message:

riscv: Add dummy SMP support

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r853c5ef r2086948a  
    66
    77/*
    8  * Copyright (c) 2013 embedded brains GmbH
     8 * Copyright (c) 2013, 2018 embedded brains GmbH
    99 *
    1010 * Redistribution and use in source and binary forms, with or without
     
    3737#define CPU_PER_CPU_CONTROL_SIZE 0
    3838
     39#if __riscv_xlen == 32
     40
     41#define CPU_INTERRUPT_FRAME_SIZE 144
     42
     43#elif __riscv_xlen == 64
     44
     45#define CPU_INTERRUPT_FRAME_SIZE 288
     46
     47#endif /* __riscv_xlen */
     48
    3949#ifndef ASM
    4050
Note: See TracChangeset for help on using the changeset viewer.