Index: c/src/lib/libbsp/powerpc/gen5200/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/ChangeLog	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libbsp/powerpc/gen5200/ChangeLog	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -1,2 +1,7 @@
+2010-03-25      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* configure.ac, include/bsp.h, console/console.c, start/start.S:
+	move more configuration constants to configure.ac
+
 2010-03-16      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
 
Index: c/src/lib/libbsp/powerpc/gen5200/configure.ac
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/configure.ac	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libbsp/powerpc/gen5200/configure.ac	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -26,23 +26,66 @@
  is turned on.])
 
+RTEMS_BSPOPTS_SET([HAS_UBOOT],[icecube],[1])
+RTEMS_BSPOPTS_SET([HAS_UBOOT],[pm520_*],[1])
+RTEMS_BSPOPTS_HELP([HAS_UBOOT],
+[If defined, board boots via U-Boot])
+
 RTEMS_BSPOPTS_SET([BENCHMARK_IRQ_PROCESSING],[*],[0])
 RTEMS_BSPOPTS_HELP([BENCHMARK_IRQ_PROCESSING],
-[If defined, enable code to benchmark IRQ processing.])
+[If set to !0, enable code to benchmark IRQ processing.])
 
 RTEMS_BSPOPTS_SET([ALLOW_IRQ_NESTING],[icecube],[0])
 RTEMS_BSPOPTS_SET([ALLOW_IRQ_NESTING],[*],[1])
 RTEMS_BSPOPTS_HELP([ALLOW_IRQ_NESTING],
-[If defined, allow nested IRQ processing.])
+[If set to !0, allow nested IRQ processing.])
 
 RTEMS_BSPOPTS_SET([BSP_PRESS_KEY_FOR_RESET],[icecube],[1])
+RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_cr825],[1])
 RTEMS_BSPOPTS_SET([BSP_PRESS_KEY_FOR_RESET],[*],[0])
 RTEMS_BSPOPTS_HELP([BSP_PRESS_KEY_FOR_RESET],
-[If defined, print a message and wait until pressed before resetting
+[If set to !0, print a message and wait until pressed before resetting
  board when application exits.])
 
 RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[icecube],[1])
+RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_*],[1])
+RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs5l],[1])
 RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[*],[0])
 RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT],
-[If defined, reset the board when the application exits.])
+[If set to !0, reset the board when the application exits.])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_ze30],[0x337F3F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552114])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_cr825],[0x330F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_cr825],[0x01050444])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs5l],[0xb30F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs5l],[0x91050444])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[icecube],[0x330F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[icecube],[0x01050444])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[*],[0x330F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[*],[0x01050444])
+
+RTEMS_BSPOPTS_HELP([BSP_GPIOPCR_INITMASK],
+[defines the bits modified in the MPC5200 GPIOPCR register during init. 
+ Must match the hardware requirements])
+RTEMS_BSPOPTS_HELP([BSP_GPIOPCR_INITVAL],
+[defines the bit values written in the MPC5200 GPIOPCR register during init. 
+ Must match the hardware requirements])
+
+## on ze30, we have PSC1/4/5/6 ...
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_ze30],[0x39])
+## on cr825, we have PSC1/2/3
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_cr825],[0x07])
+## on brs5l, we have PSC1/2/3
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs5l],[0x07])
+## on icecube, we only have PSC1
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[icecube],[0x01])
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[*],[0x01])
+RTEMS_BSPOPTS_HELP([BSP_UART_AVAIL_MASK],
+[bit mask to specify the UARTS (PSCs), which should be enabled on this board. 
+ Must match the hardware requirements. PSC1 corresponds to the LSB])
 
 RTEMS_BSPOPTS_SET([PM520_ZE30],[pm520_ze30],[1])
Index: c/src/lib/libbsp/powerpc/gen5200/console/console.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/console/console.c	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libbsp/powerpc/gen5200/console/console.c	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -116,5 +116,5 @@
 #define PSC6_MINOR      5
 
-uint32_t mpc5200_uart_avail_mask = GEN5200_UART_AVAIL_MASK;
+uint32_t mpc5200_uart_avail_mask = BSP_UART_AVAIL_MASK;
 
 #if defined(UARTS_USE_TERMIOS_INT)
Index: c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/include/bsp.h	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libbsp/powerpc/gen5200/include/bsp.h	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -72,9 +72,4 @@
 #if defined(PM520_ZE30)
 #define PM520
-#define GPIOPCR_INITMASK 0x337F3F77
-#define GPIOPCR_INITVAL  0x01552114
-/* we have PSC1/4/5/6 */
-/* #define GEN5200_UART_AVAIL_MASK 0x39 */
-#define GEN5200_UART_AVAIL_MASK 0x39
 #endif
 /*
@@ -83,8 +78,4 @@
 #if defined(PM520_CR825)
 #define PM520
-#define GPIOPCR_INITMASK 0x330F0F77
-#define GPIOPCR_INITVAL  0x01050444
-/* we have PSC1/2/3*/
-#define GEN5200_UART_AVAIL_MASK 0x07
 #endif
 
@@ -93,16 +84,8 @@
  * IMD Custom Board BRS5L
  */
-#define GPIOPCR_INITMASK 0xb30F0F77
-#define GPIOPCR_INITVAL  0x91050444
-/* we have PSC1/2/3 */
-#define GEN5200_UART_AVAIL_MASK 0x07
-
-/* we need the low level initialization in start.S*/
-#define NEED_LOW_LEVEL_INIT
 
 #define HAS_NVRAM_93CXX
+
 #elif defined (PM520)
-
-#define HAS_UBOOT
 
 #elif defined (icecube)
@@ -113,13 +96,4 @@
  *     Embedded Planet EP5200
  */
-
-#define HAS_UBOOT
-
-/* These are copied from PM520 but seem to work so OK */
-#define GPIOPCR_INITMASK 0x330F0F77
-#define GPIOPCR_INITVAL  0x01050444
-
-/* we only have PSC1 */
-#define GEN5200_UART_AVAIL_MASK 0x01
 
 #else
@@ -148,4 +122,10 @@
 
 extern bd_t bsp_uboot_board_info;
+#else
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+
+
 #endif
 
Index: c/src/lib/libbsp/powerpc/gen5200/start/start.S
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/start/start.S	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libbsp/powerpc/gen5200/start/start.S	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -183,8 +183,8 @@
 	/* init GPIOPCR */
 	lwz	r29,GPIOPCR(r31)
-	LWI	r30, GPIOPCR_INITMASK
+	LWI	r30, BSP_GPIOPCR_INITMASK
 	not	r30,r30
 	and	r29,r29,r30
-	LWI	r30, GPIOPCR_INITVAL
+	LWI	r30, BSP_GPIOPCR_INITVAL
 	or	r29,r29,r30
 	stw	r29, GPIOPCR(r31)
@@ -238,5 +238,5 @@
 
 
-#endif
+#endif /* BRS5L */
 
 
@@ -398,5 +398,5 @@
         bl      clr_mem				/* Clear onchip SRAM */
 
-#endif /* defined(BRS5L) */
+#endif /* defined(NEED_LOW_LEVEL_INIT) */
 /* clear .bss section (unique for ROM startup) */
 	LWI	r30, bsp_section_bss_start	/* get start address of bss section */
@@ -426,11 +426,11 @@
         bl      SYM (boot_card)			/* Call the first C routine */
 
-#if defined(BRS5L)
 twiddle:
 	b	twiddle				/* We don't expect to return from boot_card but if we do */
 						/* wait here for watchdog to kick us into hard reset     */
 
+#if defined(NEED_LOW_LEVEL_INIT)
 SDRAM_init:
-#if defined (BRS5L)
+#if defined(BRS5L)
       /* set GPIO_WKUP7 pin low for 66MHz buffering */
       /* or high for 133MHz registered buffering    */
@@ -459,9 +459,4 @@
 
 #endif
-#if 0
-	LWI	r30, 0xC2222600			/* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
-	stw	r30, CFG1(r31)			/* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
-						/* Refr.2No-Read delay=0x06, Write latency=0x0 */
-#else
 	/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf:	*/
 	/* set 5 delays to their maximum to support two banks           */
@@ -469,5 +464,4 @@
 	stw	r30, CFG1(r31)			/* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
 						/* Refr.2No-Read delay=0x06, Write latency=0x0 */
-#endif
 
 	LWI	r30, 0xCCC70004			/* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
@@ -560,5 +554,5 @@
 copy_image_end:
 	blr
-#endif /* defined(BRS5L) */
+#endif /* defined(NEED_LOW_LEVEL_INIT) */
 
 FID_DCache:
@@ -643,9 +637,4 @@
 	SETBITS r30, r29, MSR_FP
 	mtmsr	r30				/* enable FPU and FPU exceptions */
-
-#if 0
-	LA	r29, bsp_ram_start
-	stw	r29, 0x0(r29)
-#endif
 
 	lfd 	f0, 0(r29)
Index: c/src/lib/libcpu/powerpc/ChangeLog
===================================================================
--- c/src/lib/libcpu/powerpc/ChangeLog	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libcpu/powerpc/ChangeLog	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -1,2 +1,14 @@
+2010-03-25      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* Makefile.am, mpc55xx/include/siu.h, mpc55xx/siu/siu.c:
+	add generic SIU support
+	add timer support, on timebase
+	* mpc55xx/edma/edma.c: fix init call to be prototype
+	* mpc55xx/esci/esci.c: adapted to new prototype for *_write function
+	* mpc55xx/include/reg-defs.h, mpc55xx/include/regs.h,
+	mpc55xx/misc/fmpll.S:
+	add support for mpc551x registers
+	* mpc6xx/timer/timer.c: fix typo
+
 2009-12-17      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
 
Index: c/src/lib/libcpu/powerpc/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/Makefile.am	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libcpu/powerpc/Makefile.am	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -417,4 +417,5 @@
 	mpc55xx/include/mpc55xx.h \
 	mpc55xx/include/esci.h \
+	mpc55xx/include/siu.h \
 	mpc55xx/include/watchdog.h
 
@@ -426,4 +427,10 @@
 mpc55xx_irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 
+# mpc6xx/timer
+noinst_PROGRAMS += mpc55xx/timer.rel
+mpc55xx_timer_rel_SOURCES = mpc6xx/timer/timer.c
+mpc55xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
+mpc55xx_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
 # FEC
 noinst_PROGRAMS += mpc55xx/fec.rel
@@ -440,4 +447,9 @@
 mpc55xx_emios_rel_SOURCES = mpc55xx/emios/emios.c
 mpc55xx_emios_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+# SIU
+noinst_PROGRAMS += mpc55xx/siu.rel
+mpc55xx_siu_rel_SOURCES = mpc55xx/siu/siu.c
+mpc55xx_siu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 
 # eSCI
Index: c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -1,5 +1,5 @@
 /*  timer.c
  *
- *  This file implements a benchmark timer using the General Purpose Timer.
+ *  This file implements a benchmark timer using the PPC Timebase
  *
  *  Notes: NONE
Index: c/src/lib/libcpu/powerpc/preinstall.am
===================================================================
--- c/src/lib/libcpu/powerpc/preinstall.am	(revision 2f5435a42fbca8d6845c06fca77ec1dfeb831e12)
+++ c/src/lib/libcpu/powerpc/preinstall.am	(revision 1f4db180af76c320984dda1fc371c993bfadad35)
@@ -275,4 +275,8 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/esci.h
 
+$(PROJECT_INCLUDE)/mpc55xx/siu.h: mpc55xx/include/siu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/siu.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/siu.h
+
 $(PROJECT_INCLUDE)/mpc55xx/watchdog.h: mpc55xx/include/watchdog.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
